KR20010073744A - cell power line layout method in semiconductor memory device - Google Patents

Abstract

PURPOSE: A method for arraying cell power lines of a semiconductor device is provided to enhance efficiency in a laser repair process, reduce a number of contacts, conduct the laser repair by taking a column as a unit, cut off a power voltage by using a column as a unit, and efficiently reduce a number of contacts necessary for forming a memory unit cell. CONSTITUTION: Cell power lines are arranged between bit line pair in parallel to bit line pair direction to provide a power voltage to memory cells of a semiconductor memory device by taking each bit line pair as a unit. If there is a defect in the memory cells, the cell power line corresponding to a repair process is fuse-cut, so that the power voltage is cut off to the defective memory cells. Drains of a PMOS and NMOS transistors that form each inverter in the memory cell are formed as active regions. Gate polysilicon layers for forming gates of the transistors are respectively connected by corresponding local interconnection layers through two contacts. The repair of column unit is enabled, such that the cell power voltage can be cut off through the power line. When a current failure is happened in the cell included in one column, a sorting can be carried out by using a chip that is capable of repairing. Consequently, manufacturing yield is increased.

Description

Cell power line layout method in semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to power line arrangement of semiconductor memory devices, and more particularly, to a cell power line arrangement method of static random access memory (SRAM).

In a typical peninsula memory device, a power supply voltage is directly applied to a cell of a static random access memory for storing and maintaining data. That is, since one unit memory cell is a flip-flop type composed of two inverter latches, each of the inverters has a high load resistance, a thin film transistor, or a morph transistor. As shown in FIG. 1, the cell has a layout structure connected to a power line to receive a power supply voltage VCC.

FIG. 1 is a diagram showing a conventional static memory cell related arrangement structure synthesized with an equivalent circuit. In FIG. 1, in the case of a full CMOS cell, one memory cell is composed of six transistors P1, P2, PM1, PM2, NM1, and NM2. The N-type transistors P1 and P2 whose word lines WL become their gates are called access transistors or pass gates. PMOS transistors PM1 and PM2 and NMOS transistors NM1 and NM2 respectively referred to as driving transistors correspond to each other to form one inverter. In the MOS transistor PM1 and the NMOS transistor NM1 forming one inverter, the gates of the transistors are formed of a polysilicon layer, and the polysilicon layer of the MOS transistor PM2 in the opposite inverter is formed. Is connected to the local interconnect (LI) layer that contacts the drain. The gates of the transistors in the PMOS transistor PM2 and the NMOS transistor NM2 forming the remaining inverter are also formed of a polysilicon layer, and the polysilicon layer (G-poly) is formed in the opposing MOS transistor PM1 in the opposite inverter. Is connected to the local interconnect (LI) layer that contacts the drain.

In FIG. 1, when the power lines VCC1 and VCC2 of the metal layer Metal-1 are disposed, the power lines VCC1 and VCC2 are arranged in parallel with bit line pairs BL and BLB, and two power lines are disposed in parallel. It can be seen that the structure has a power supply voltage applied to one cell. Here, the power supply line VCC1 applies a power supply voltage to a source of the PMOS transistor PM1 that is the active region 10, and also supplies the power supply voltage to the active region of the inverters on one side of the memory cells on the left side of the drawing. The power supply voltage is applied through the metal contact MC3. The power supply line VCC2 also applies a power supply voltage to the source of the PMOS transistor PM2 which is the active region 11, and also contacts the active region of the other inverters of the memory cells not shown on the right side with reference to the drawings. Note that the supply voltage is applied via (MC4).

As described with reference to FIG. 1, when the bit line and the power line are vertically configured in the same direction in the same layer, there are the following problems. First, since one power line disposed between a bit line and an adjacent bit line applies a power supply voltage to the inverters of memory cells in two columns in common, a cell power supply voltage is supplied through the power line during column-by-column repair. It becomes difficult to block. In other words, since the power supply lines supplying the power supply voltage are shared by the cells belonging to different columns, the cell power supply voltage cannot be blocked during the laser repair of each column, so even if a standby current fails in a cell belonging to one column It is classified as impossible chip. In addition, since power lines are disposed between bit lines and adjacent bit lines, manufacturing yields have been hindered due to poor connection between layers due to the unopening of pattern bridges and contact holes. In addition, the number of nest contacts (NC1-1 to NC1-6) connecting each driving transistor to form a memory cell is six, which causes high integration of the cell and complicates the manufacturing process. do.

Therefore, it is possible to perform laser repair on a column basis, cut off the standby current power supply voltage on a column basis, reduce contact defects on the power line, and efficiently reduce the number of contacts required to form a memory unit cell. Techniques for reducing are desired.

Accordingly, it is an object of the present invention to provide a method capable of solving the above problem.

Another object of the present invention is to provide a cell power line arrangement method of a semiconductor memory device for increasing the efficiency of the laser repair process and reducing the number of contacts.

It is still another object of the present invention to provide a cell power line arrangement method of a semiconductor memory device capable of performing laser repair on a column basis.

Another object of the present invention is to provide a method for arranging cell power lines of a semiconductor memory device which can cut off a power supply voltage in a column unit when a standby current fails.

It is still another object of the present invention to provide a cell power line arrangement method of a semiconductor memory device capable of reducing contact failure of a power line and efficiently reducing the number of contacts required to form a memory unit cell.

According to the cell power line arrangement method of the present invention for achieving the above objects, the cell power line for providing a power supply voltage to the memory cells of the semiconductor memory device in parallel with the bit line pair direction between the bit line pair Each bit line pair is arranged one by one.

Preferably, when a defect occurs among the memory cells, the corresponding cell power line in the repair process is fused to block the supply of the power voltage to the defective memory cells. In addition, in order to reduce the number of cell contacts, drains of PMOS and NMOS transistors forming each inverter in the memory cell are respectively formed as active regions, and gate polys forming the active regions and gates of the transistors are formed. The silicon layers are each connected through two contacts by respective corresponding local interconnect layers.

1 is a diagram showing a conventional static memory cell related layout structure synthesized with an equivalent circuit.

FIG. 2 is a diagram illustrating a static memory cell related arrangement according to an embodiment of the present invention, synthesized with an equivalent circuit. FIG.

The above and other objects, features, and other advantages of the present invention will become apparent from the following detailed description of the preferred embodiments of the present invention described below with reference to the accompanying drawings. It should be noted that the same or similar parts to each other in the drawings are described with the same or similar reference numerals for convenience of explanation and understanding.

FIG. 2 is a diagram illustrating a static memory cell related arrangement according to an exemplary embodiment of the present invention, combined with an equivalent circuit. Referring to FIG.

Referring to the drawings, a cell power supply line VCC for providing a power supply voltage to memory cells of a semiconductor memory device is disposed substantially parallel to the bit line pair BL and BLB directions between the bit line pairs BL and BLB. Structure is shown. Although the arrangement including the word line and the bit line is shown in the figure, the memory cells can be expanded and arranged in the row and column directions. Therefore, since the cell power supply line VCC is disposed one by one between the bit line pairs BL and BLB in the semiconductor memory, the cell power line VCC exists in each bit line pair unit.

In FIG. 2, portions that are vertically the same layer and are made of the metal layer Metal-1 in the same direction are the power line VCC and the bit line pairs BL and BLB. Referring to the arrangement of FIG. 2, one power line parallel to the bit line pairs BL and BLB and disposed therebetween has a structure in which a power supply voltage is applied to only one cell. Accordingly, the power supply line VCC is connected to the metal contact MC3 to apply a power supply voltage to the source of the PMOS transistor PM1 which is the active region 20 and at the same time, the PMOS transistor PM2 which is the active region 21. Apply a power supply voltage to the source of. By arranging the power lines as described above, the laser repair can be performed in units of columns, and when the standby current fails, the power supply voltage can be cut in units of columns. That is, when a defect occurs among the memory cells, the fuse of the cell power line connected to the corresponding column is cut by a laser or a current in a repair process so that the power supply voltage is no longer provided to the defective memory cells. In addition, since the power supply line is disposed between the bit line pairs BL and BLB, the placement margin is improved, and thus, the contact failure is reduced because the probability of the interlayer connection failure due to the pattern bridge or the unopening of the contact hole is smaller than in the conventional case.

Meanwhile, in order to efficiently reduce the number of contacts required to form a memory unit cell, as shown in FIG. 2, PMOS and NMOS transistors forming each inverter in the memory cell (PM1, NM1, PM2, NM2). And drain gates of each of the active regions ACT, and gate polysilicon layers G-Polys forming the gates of the active regions ACT and the transistors, respectively. By connecting each of the two contacts (NC1-1, NC1-2) (NC1-3, NC1-4) by the local interconnection layer, a total of four nest contacts (NC1-1), which are two fewer than the conventional case. NC1-4) is required. Therefore, it is advantageous for high integration of the memory cell, and the contact manufacturing process is simplified.

In the drawing, in the order of manufacturing process, active (ACT)-gate poly (G-Poly)-nest contact (NC1)-local interconnect layer (LI)-metal contact (MC1)-metal 1 (METAL 1)-via (VIA)-Metal 2 proceeds in order. The manufacturing process sequence of FIG. 2 may be the same as that of FIG. That is, it should be understood that only the layout structure, that is, layout, with the prior art is different regardless of the order of manufacturing processes.

The present invention has been described based on the embodiments based on the illustrated drawings, but is not limited thereto, and various changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is obvious that other embodiments may be modified, as well as equivalent embodiments.

As described above, according to the cell power line arrangement method of the present invention, it is possible to cut the cell power supply voltage through the power supply line by enabling column-by-column repair, and when a standby current fails in a cell belonging to one column Since it can be sorted into a repairable chip, there is an effect that improvement in manufacturing yield is expected. In addition, since the power lines are disposed between the bit line pairs, interlayer connection defects are reduced due to the pattern bridge or the non-opening of the contact hole, and the number of nest contacts connected between the driving transistors to form a memory cell is reduced. have. As a result, since the efficiency of the laser repair process is increased and the number of contacts is reduced, the manufacturing yield is improved and the manufacturing cost is reduced.

Claims (3)

In the cell power line arrangement method of the semiconductor memory device, And arranging cell power lines for supplying power voltages to the memory cells of the semiconductor memory device, one by one bit line pair, between the bit line pairs, substantially parallel to the bit line pair direction. The method of claim 1, wherein when a defect occurs among the memory cells, the corresponding cell power line is fuse cut in a repair process so that the supply voltage is not provided to defective memory cells. 2. The semiconductor memory device according to claim 1, wherein drains of PMOS and NMOS transistors forming each inverter in the memory cell are respectively formed into active regions, and gate polysilicon layers respectively forming the active regions and gates of the transistors. Connecting through two contacts, respectively, by corresponding local interconnect layers of the plurality of contacts.