CN114126213A - Wiring board - Google Patents
Wiring board Download PDFInfo
- Publication number
- CN114126213A CN114126213A CN202110920243.7A CN202110920243A CN114126213A CN 114126213 A CN114126213 A CN 114126213A CN 202110920243 A CN202110920243 A CN 202110920243A CN 114126213 A CN114126213 A CN 114126213A
- Authority
- CN
- China
- Prior art keywords
- pad
- cavity
- substrate
- base
- main surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 239000000919 ceramic Substances 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 abstract description 30
- 230000000052 comparative effect Effects 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 238000000034 method Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 239000002904 solvent Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 238000007639 printing Methods 0.000 description 7
- 238000010304 firing Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 244000208734 Pisonia aculeata Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000005456 alcohol based solvent Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000005453 ketone based solvent Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002861 polymer material Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
Abstract
The invention provides a wiring substrate which can restrain the enlargement of a semiconductor device. The wiring substrate includes a base body and a pad, wherein the base body includes: a cavity having a bottom surface and cavity side surfaces; and an electrode arrangement surface on which a pad is arranged, the electrode arrangement surface being a surface on which an opening of the cavity is formed, the pad having: a 1 st main surface; a 2 nd main surface which is a back surface of the 1 st main surface; and a plurality of side surfaces connecting the 1 st main surface and the 2 nd main surface, at least a part of the pad itself being embedded in the substrate, the 1 st main surface being exposed on the electrode arrangement surface side of the substrate, the 1 st side surface of the plurality of side surfaces protruding into the cavity, or the 1 st side surface being aligned with the cavity side surface of the substrate, the substrate being exposed between the 2 nd main surface of the pad and an outer periphery of the bottom surface of the cavity on the cavity side surface of the substrate.
Description
Technical Field
The present invention relates to a wiring board.
Background
As a method for electrically connecting a semiconductor chip and a wiring of a wiring board, a wire bonding technique using a conductive pad disposed on the wiring board has been known (for example, see patent document 1).
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open No. 2005-86200
Disclosure of Invention
Problems to be solved by the invention
In addition, a semiconductor device in which a semiconductor chip is mounted in a recess (cavity) formed in a ceramic package has been used. In this ceramic package, as in patent document 1, the bonding pads are mounted on the surface of the ceramic package. With such a ceramic package, the pad is spaced apart from the opening of the cavity by a predetermined distance, in other words, the pad is formed to retreat from the opening of the cavity.
In recent years, there has been a demand for a technique for suppressing an increase in size of a semiconductor device while increasing performance and an increase in size of a semiconductor chip.
The present invention has been made to solve the above-described problems, and an object thereof is to provide a technique for suppressing an increase in size of a semiconductor device.
Means for solving the problems
(1) According to an aspect of the present invention, there is provided a wiring board including a base containing ceramic as a main component and a conductive pad disposed on the base. In the wiring board, the base body has: a cavity having a bottom surface and a cavity side surface connected to an outer periphery of the bottom surface and erected on the bottom surface; and an electrode arrangement surface on which the pad is arranged, the electrode arrangement surface being a surface on which an opening of the cavity is formed, the pad having: a 1 st main surface; a 2 nd main surface which is a back surface of the 1 st main surface; and a plurality of side surfaces which connect the 1 st main surface and the 2 nd main surface, at least a part of the pad itself being embedded in the substrate, the 1 st main surface being exposed on the electrode arrangement surface side of the substrate, a 1 st side surface of the plurality of side surfaces protruding into the cavity, or the 1 st side surface being aligned with the cavity side surface of the substrate, the substrate being exposed between the 2 nd main surface of the pad and an outer periphery of the bottom surface of the cavity on the cavity side surface of the substrate.
According to this structure, at least a part of the pad itself is embedded in the base, the side surface of the pad is in contact with the base, and the pad is bonded to the base via these surfaces. Further, the land is sandwiched and pressed from the side surface side by the base body due to thermal shrinkage at the time of firing in the manufacturing process of the wiring substrate. Therefore, peeling of the pad 20 can be suppressed.
Further, since the 1 st side surface of the pad protrudes into the cavity or the 1 st side surface is aligned with the cavity side surface of the base, the distance between the opening of the cavity and the pad can be shortened, and thus, for example, the opening area of the cavity can be increased without changing the outer dimension of the wiring board, and a semiconductor chip having an increased size can be mounted. In addition, for example, the outer shape of the wiring substrate can be reduced in size. That is, the semiconductor device can be prevented from being enlarged.
Further, since the substrate is exposed between the 2 nd main surface of the pad and the outer periphery of the bottom surface of the cavity on the cavity side surface of the substrate, for example, a metal portion such as a via is not disposed, peeling of the pad accompanying pushing up of the pad tip due to the via or the like can be suppressed.
(2) In the wiring board according to the above aspect, 60% or more of the pad itself may be embedded in the base. In this case, the peeling of the pad can be appropriately suppressed.
(3) In the wiring board according to the above-described aspect, a distance between the 1 st side surface of the pad and the cavity side surface of the cavity of the base in a direction along the 1 st main surface may be 10 μm or less. In this case, the peeling of the pad can be appropriately suppressed, and the increase in size of the wiring board can be suppressed.
(4) In the wiring board according to the above aspect, the wiring board may include: an internal wiring layer formed inside the base; and a via formed inside the base body and connecting the pad and the internal wiring layer. In this case, the peeling of the pad can be appropriately suppressed as compared with the case where the via is disposed inside the side surface of the cavity.
The present invention can be realized in various forms, for example, a product including a wiring board, a method for manufacturing a product including a wiring board, and the like.
Drawings
Fig. 1 is a diagram showing a schematic configuration of a wiring board according to embodiment 1.
Fig. 2 is a diagram schematically showing a state in which the pad is viewed from the cavity side.
Fig. 3 is an explanatory view of a semiconductor device using the wiring board of the present embodiment.
Fig. 4 is a flowchart of the method for manufacturing the ceramic wiring substrate according to the present embodiment.
Fig. 5 is a diagram showing a schematic configuration of a wiring board of a comparative example.
Fig. 6 is an explanatory diagram comparing the sizes of the wiring substrate of the embodiment and the wiring substrate of the comparative example.
Fig. 7 is a diagram showing a schematic configuration of the wiring board according to embodiment 2.
Fig. 8 is a diagram showing a schematic configuration of the wiring board according to embodiment 3.
Description of the reference numerals
10. A substrate; 12. a cavity; 12L, an opening; 14. 14P, an electrode arrangement surface; 15. a frame portion; 16. an internal wiring layer; 18. a passage; 20. 20P, a bonding pad; 21. a 1 st main surface; 22. a 2 nd main surface; 22P, bottom surface; 23. a side surface; 100. 100A, 100B, 100P, a wiring substrate; 122. a bottom surface; 122L, outer periphery; 124. a cavity side; 200. a semiconductor chip; 231. the 1 st side; l1, distance; w, lead wire
Detailed Description
< embodiment 1 >
Fig. 1 is a diagram showing a schematic configuration of a wiring board 100 according to embodiment 1. Fig. 1 (a) is a plan view, and fig. 1 (b) is a cross-section a-a of fig. 1 (a). In order to specify the direction, an X axis, a Y axis, and a Z axis orthogonal to each other are shown in the drawing. In this specification, the positive Z-axis direction is referred to as an upward direction and the negative Z-axis direction is referred to as a downward direction for convenience, but the wiring substrate 100 may be provided in an orientation different from this orientation. In fig. 1 (a), the direction toward the front side of the drawing is a positive Z-axis direction, and in fig. 1 (b), the direction toward the back side of the drawing is a positive Y-axis direction.
As shown in fig. 1, the wiring board 100 includes a base 10 mainly composed of ceramic and a plurality of pads 20 having conductivity. The base body 10 is a flat plate having a substantially square outer shape as a whole, and a cavity 12 is formed in the center of the square. The cavity 12 has a bottom surface 122 and a cavity side surface 124 connected to an outer periphery 122L (fig. 1 b) of the bottom surface 122 and standing on the bottom surface 122. The base body 10 further has an electrode arrangement surface 14, the electrode arrangement surface 14 is a surface on which an opening 12L (fig. 1 (a)) of the cavity 12 is formed, and the pad 20 is arranged on the electrode arrangement surface 14. The electrode arrangement face 14 is also referred to as a "shelf (japanese: シェルフ)". The wiring substrate 100 has a frame portion 15 in a substantially square frame shape protruding in the Z-axis positive direction from the electrode arrangement surface 14 on the outer periphery of the electrode arrangement surface 14. The base 10 is made of an insulating material containing ceramic as a main component, and in the present embodiment, is made of, for example, alumina. The wiring board 100 of the present embodiment is a so-called semiconductor package, and a semiconductor chip is mounted in the cavity 12 to constitute a semiconductor device (described later).
Fig. 2 is a diagram schematically showing the pad 20 viewed from the cavity 12 side. The pad 20 is a conductive body mainly composed of metal, and has a flat plate shape having a substantially rectangular outer shape in a plan view (fig. 1). The pad 20 has: the 1 st main surface 21 (fig. 1 (b)); a 2 nd main surface 22 which is a back surface of the 1 st main surface 21; and a plurality of side surfaces 23 connecting the 1 st main surface 21 and the 2 nd main surface 22. In the present embodiment, the wiring board 100 has 28 pads 20, but the number of pads 20 is not limited to the present embodiment.
The pads 20 are disposed on the electrode disposition surface 14 of the base 10. As shown in fig. 2, in the present embodiment, the pad 20 is entirely embedded in the substrate 10, the surface position of the 1 st main surface 21 of the pad 20 is aligned with the electrode arrangement surface 14 of the substrate 10, and the 1 st main surface 21 is exposed. In addition, the face position of the 1 st side 231 among the 4 sides 23 of the pad 20 is aligned with the cavity side 124 of the cavity 12 of the base 10, and the 1 st side 231 is exposed (fig. 1 (b), fig. 2).
A metal having high conductivity, such as copper, silver, gold, aluminum, tungsten, molybdenum, or an alloy containing each of these metals as a main component, can be used as the metal that is the main component of the pad 20. Various conductive materials other than metals such as carbon and conductive polymer materials can also be used.
As shown in fig. 1 (b), the wiring substrate 100 includes: an internal wiring layer 16 formed inside the base 10; and a via 18 formed inside the base 10 and connecting the pad 20 and the internal wiring layer 16. The internal wiring layer 16 and the via 18 are formed of a material mainly composed of the same conductive material as the pad 20.
Fig. 3 is an explanatory diagram of a semiconductor device using the wiring substrate 100 of the present embodiment. In the semiconductor device shown in fig. 3, the semiconductor chip 200 is mounted in the cavity 12 of the wiring board 100, and the electrode of the semiconductor chip 200 and the pad 20 are electrically connected by the wire W. Thereby, the semiconductor chip 200 is electrically connected to the internal wiring layer 16 of the wiring substrate 100. Note that the sealing material is not illustrated in fig. 3.
As the semiconductor chip 200, various semiconductor chips such as a Logic circuit chip, an image sensor chip, a crystal oscillator, and a passive element can be used.
Next, a method for manufacturing the wiring substrate 100 of the present embodiment will be described.
Fig. 4 is a flowchart of the method for manufacturing the ceramic wiring substrate according to the present embodiment. In this embodiment, the pad pattern is transferred to the ceramic green sheet using the carrier film on which the pad pattern is formed. An example of manufacturing the wiring substrate 100 by stacking 3 green sheets will be described below. The 3 green sheets were: a 1 st green sheet having a substantially square shape in plan view and having a surface serving as a bottom surface 122 (fig. 1 (b)); a 2 nd green sheet having a substantially square frame shape in plan view and having a surface (hereinafter, also referred to as "green sheet electrode mounting surface") to be an electrode arrangement surface 14 (fig. 1 (a)); and a 3 rd green sheet having a substantially square frame shape in a plan view, which becomes the frame portion 15.
In the preparation step (P11), 3 green sheets, a solvent, and a carrier film on which a land pattern is formed are prepared. The 3 green sheets include green sheets on which a metal film to be a wiring pattern and a metal to be a via are formed. The metal film may be formed by printing, vapor deposition, or the like, or may be formed by transfer. The pad pattern is formed on the carrier film using, for example, photolithography.
In the solvent coating step (P12), a solvent is applied to the green sheet electrode mounting surface of the 2 nd green sheet by a known method such as printing or spraying. As the solvent, various solvents that can make the green sheet plastic can be used. The solvent is desirably selected according to the organic binder contained in the green sheet, and for example, an alcohol-based solvent, an acetone-based solvent, or a ketone-based solvent can be used. The amount of solvent applied can be set appropriately. Since the solvent is applied to the green sheet electrode mounting surface of the 2 nd green sheet, the solvent penetrates from the green sheet electrode mounting surface and a part of the 2 nd green sheet is dissolved, the part of the 2 nd green sheet which is a predetermined distance away from the green sheet electrode mounting surface is softer than the other parts, and is easily deformed.
In the transfer step (P13), the land pattern formed on the carrier film is transferred to the 2 nd green sheet. Specifically, the land pattern formed on the carrier film was formed on the 2 nd green sheet by placing the land pattern on the green sheet electrode placement surface of the 2 nd green sheet, pressing and heating the land pattern, and then peeling off the carrier film.
In the laminating step (P14), the 2 nd green sheet is laminated on the 1 st green sheet, and the 3 rd green sheet is further laminated on the 2 nd green sheet to form a green sheet laminated body. At this time, a land pattern was transferred to the green sheet electrode mounting surface of the 2 nd green sheet.
In the pressing step (P15), the green sheet laminated body is pressed in a direction substantially perpendicular to the green sheet electrode arrangement surface by a pressing plate having a projection fitted in a stepped shape formed by laminating the 1 st green sheet, the 2 nd green sheet, and the 3 rd green sheet. The green sheet laminate was pressed to press the land pattern into the 2 nd green sheet.
In the firing step (P16), the green sheet laminate is fired. Specifically, for example, the green sheet laminate is put in a pressurized state into a case made of aluminum nitride, and is placed in a carbon furnace. Then, for example, the mixture is fired at a predetermined temperature for a predetermined time in a nitrogen atmosphere at normal pressure. Thereby, the wiring substrate 100 is manufactured. In the manufactured wiring board 100, the pad 20 is embedded in the base 10.
Fig. 5 is a diagram showing a schematic configuration of a wiring board 100P of a comparative example. In fig. 5, similarly to fig. 1, (a) of fig. 5 shows a plan view, and (b) of fig. 5 shows an a-a cross section of fig. 5 (a). Fig. 5 (b) shows a state where the semiconductor chip 200 is mounted. In the wiring substrate 100P of the comparative example, the pads 20P were produced by printing using screen printing. Therefore, as shown in fig. 5 (b), the pad 20P is formed in a state of being placed on the electrode arrangement surface 14 of the base 10. The pad 20P is formed to be spaced apart from the end of the electrode arrangement surface 14 (the surface position of the cavity side surface 124 of the cavity 12) by a distance L1. In other words, the pad 20P of the comparative example is formed so as to be set back from the end of the electrode arrangement surface 14 by the distance L1. In the wiring board 100P of the comparative example, the land 20P was formed by the printing method as described above, and when the ink after printing was removed, the edge portion of the land was captured by the emulsion of the mask, and therefore, as shown in fig. 5 (b), the cross-sectional shape was a fish cake shape (japanese: かまぼこ形状). In the wiring board 100P of the comparative example, the pad 20P is bonded to the base 10 mainly via the bottom surface 22P.
In contrast, in the wiring board 100 of the present embodiment, the surface position of the 1 st side surface 231 of the land 20 is aligned with the cavity side surface 124 of the cavity 12 of the base 10 (fig. 1 (b), fig. 2). In other words, the tip of the pad 20 extends to the end of the electrode arrangement surface 14, and the pull-back distance is "0". In addition, according to the wiring board 100 of the present embodiment, the land 20 is embedded in the base 10. Therefore, the 2 nd main surface 22 and the 3 side surfaces 23 of the main pad 20 are in contact with the base 10, and the pad 20 is bonded to the base 10 via these surfaces. Further, the land 20 is sandwiched and pressed by the base 10 from the side surface 23 side due to thermal shrinkage at the time of firing in the manufacturing process of the wiring substrate 100. Therefore, according to the wiring board 100 of the present embodiment, even if the land 20 is disposed such that the surface position of the 1 st side surface 231 is aligned with the cavity side surface 124 of the cavity 12 of the base 10, the land 20 can be inhibited from peeling.
In addition, in the wiring substrate 100, the via 18 connecting the internal wiring layer 16 and the pad 20 formed inside the base 10 is formed inside the base 10 (fig. 1 (b)). For example, in the case where the via 18 is provided so as to be exposed to the inside of the cavity 12 along the cavity side surface 124 of the cavity 12, the pad 20 becomes easily peeled off from the tip due to the via 18 pushing up the tip (the vicinity of the 1 st side surface 231) of the pad 20. In contrast, in the wiring board 100 of the present embodiment, the via 18 is formed inside the base 10, and the base 10 is exposed between the 2 nd main surface 22 of the pad 20 and the outer periphery 122L of the bottom surface 122 of the cavity 12 on the cavity side surface 124 of the base 10, so that the pad 20 can be prevented from being peeled off due to the via 18 pushing up the tip of the pad 20.
In addition, according to the method of manufacturing the wiring substrate 100 of the present embodiment, since the lands 20 are formed by transfer, the surface flatness can be improved as compared with the wiring substrate 100P of the comparative example. Therefore, connection failure of wire bonding due to irregularities on the surface of the pad can be suppressed.
In the method of manufacturing the wiring board 100 according to the present embodiment, the land 20 is formed of a photosensitive metallization paste and embedded in the base 10 by transfer. Therefore, it is possible to make the wiring substrate 100P finer than the case where the pads are formed by the printing technique as in the case of the comparative example. Therefore, the semiconductor chip with a large number of terminals and the substrate electrode can be connected by wire bonding. This allows the heat generated by the semiconductor chip to be directly dissipated from the substrate 10 containing ceramic as a main component.
Fig. 6 is an explanatory diagram for comparing the dimensions of the wiring substrate 100 of the embodiment and the wiring substrate 100P of the comparative example. Fig. 6 (a) shows a wiring board 100 according to the present embodiment, and fig. 6 (b) shows a wiring board 100P according to a comparative example. As shown in the drawing, the same semiconductor chip 200 is mounted on the wiring substrate 100 and the wiring substrate 100P. Wiring substrate 100 and wiring substrate 100P have cavity 12 of the same size and frame 15 of the same width. In addition, the pad 20 and the pad 20P have different widths but the same length.
As described above, in the wiring substrate 100P of the comparative example, the pads 20P are formed to be spaced apart (withdrawn) from the end portions of the electrode arrangement surface 14P. Since the length of the land 20P is the same as that of the land 20, the width of the electrode arrangement surface 14P of the wiring substrate 100P of the comparative example is wider than that of the electrode arrangement surface 14 of the wiring substrate 100 of the present embodiment. Therefore, the external shape of the wiring substrate 100P of the comparative example is larger than that of the wiring substrate 100 of the present embodiment. That is, according to the wiring substrate 100 of the present embodiment, since the tip of the pad 20 extends to the end of the electrode arrangement surface 14 and the retreat distance is "0", even when the semiconductor chip is complicated and large-sized, it is possible to suppress the semiconductor device from being large-sized. Further, since the cavity can be enlarged without changing the outer shape of the wiring board (semiconductor package) and a semiconductor chip having an increased size can be mounted, it is not necessary to change the space in a PC board (printed-circuit board), for example.
< embodiment 2 >
Fig. 7 is a diagram showing a schematic configuration of a wiring board 100A according to embodiment 2. Fig. 7 (a) is a plan view, and fig. 7 (b) is an a-a cross section of fig. 7 (a), similar to fig. 1.
In the wiring board 100A of the present embodiment, a part of the pad 20 itself is buried in the base 10. In fig. 7 (b), a portion of the pad 20 buried in the base 10 is indicated by a dotted line, and a portion protruding upward from the electrode arrangement surface 14 is indicated by hatching. In the present embodiment, 60% or more of the pad 20 itself is buried in the base 10.
The wiring board 100A of the present embodiment can also suppress the peeling of the pad 20, as in the wiring board 100 of embodiment 1.
< embodiment 3 >
Fig. 8 is a diagram showing a schematic configuration of a wiring board 100B according to embodiment 3. Fig. 8 (a) shows a plan view, and fig. 8 (b) shows a cross-section a-a of fig. 8 (a), similarly to fig. 1.
In the wiring board 100B of the present embodiment, the 1 st side surface 231 of the pad 20 protrudes into the cavity 12. In the present embodiment, the distance between the 1 st side surface 231 of the land 20 and the cavity side surface 124 of the cavity 12 of the substrate 10 in the direction along the 1 st main surface 21 (the X-axis direction in fig. 7 (b)) is 10 μm or less.
The wiring board 100B of the present embodiment can also suppress the peeling of the pad 20, as in the wiring board 100 of embodiment 1.
< modification of the present embodiment >
The present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the scope of the invention.
In the above-described embodiment, an example (embodiment 1) in which the entire pad is buried in the base, an example (example) in which the tip end of the pad is aligned with the side surface of the cavity and the 1 st main surface of the pad is projected from the electrode mounting surface (embodiment 2) in which the tip end of the pad (the 1 st side surface) is projected into the cavity and the surface position of the 1 st main surface of the pad is aligned with the electrode mounting surface (example) in which the tip end of the pad (the 1 st side surface) is buried in the base (embodiment 3) are shown. At least a part of the pad may be embedded in the base, and for example, the tip (1 st side surface) of the pad may protrude into the cavity, and the 1 st main surface of the pad may protrude from the electrode mounting surface.
The ratio of the pad buried in the base is not limited to the above embodiment. For example, the concentration may be 50% or 40%. When 60% or more of the land is embedded in the base, peeling between the land and the base can be further suppressed, which is preferable.
The distance between the 1 st side surface of the pad and the cavity side surface of the cavity of the base in the direction along the 1 st main surface is not limited to the above embodiment. For example, the distance may be 15 μm or 20 μm. When the distance is 10 μm, peeling of the pad can be appropriately suppressed, which contributes to suppressing an increase in size of the semiconductor device, and is preferable.
The shape of the pad in plan view is not limited to the above embodiment. For example, a square shape, a hexagonal shape, or the like is also possible.
The shape of the substrate is not limited to the above embodiment. For example, the shape of the cavity may be rectangular in plan view, the opening shape of the cavity may be rectangular, or the frame may not be provided.
The method of manufacturing the wiring board is not limited to the above embodiment. For example, the pad may be formed by printing, vapor deposition, or the like.
The substrate may be aluminum nitride (AlN) or zirconium oxide (ZrO)2) Silicon nitride (Si)3N4) And silicon carbide (SiC) as an insulating material containing a ceramic as a main component.
The present invention has been described above based on the embodiments and the modified examples, but the embodiments of the above-described forms are only for easy understanding of the present invention and do not limit the present invention. The present invention can be modified and improved without departing from the gist and the claims, and the present invention includes equivalents thereof. Note that, if this technical feature is not described as an essential feature in the present specification, it can be appropriately deleted.
Claims (4)
1. A wiring board having a base body containing ceramic as a main component and a pad having conductivity arranged on the base body,
the base body has:
a cavity having a bottom surface and a cavity side surface connected to an outer periphery of the bottom surface and erected on the bottom surface; and
an electrode arrangement surface on which the pad is arranged, the electrode arrangement surface being a surface on which an opening of the cavity is formed,
the pad has:
a 1 st main surface; a 2 nd main surface which is a back surface of the 1 st main surface; and a plurality of side surfaces connecting the 1 st main surface and the 2 nd main surface,
at least a portion of the pad itself is embedded in the substrate,
the 1 st main surface is exposed on the electrode arrangement surface side of the substrate,
a 1 st side of the plurality of sides protrudes into the cavity, or the 1 st side is aligned with the cavity side of the substrate,
the base is exposed between the 2 nd main surface of the pad and an outer periphery of the bottom surface of the cavity on the cavity side surface of the base.
2. The wiring substrate according to claim 1,
more than 60% of the bonding pad is buried in the base body.
3. The wiring substrate according to claim 1 or 2,
the distance between the 1 st side surface of the pad and the cavity side surface of the cavity of the base body in the direction along the 1 st main surface is 10 [ mu ] m or less.
4. The wiring substrate according to any one of claims 1 to 3,
the wiring substrate includes:
an internal wiring layer formed inside the base; and
and a via formed inside the base body and connecting the pad and the internal wiring layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020141374A JP7446950B2 (en) | 2020-08-25 | 2020-08-25 | wiring board |
| JP2020-141374 | 2020-08-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114126213A true CN114126213A (en) | 2022-03-01 |
| CN114126213B CN114126213B (en) | 2024-08-09 |
Family
ID=80440880
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110920243.7A Active CN114126213B (en) | 2020-08-25 | 2021-08-11 | Wiring substrate |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP7446950B2 (en) |
| CN (1) | CN114126213B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232466A (en) * | 1996-02-23 | 1997-09-05 | Kyocera Corp | Manufacture of package for semiconductor chip |
| JP2000165043A (en) * | 1998-11-26 | 2000-06-16 | Kyocera Corp | Circuit board |
| JP2005252074A (en) * | 2004-03-05 | 2005-09-15 | Renesas Technology Corp | Semiconductor device and electronic apparatus |
| JP2006186396A (en) * | 2004-07-07 | 2006-07-13 | Nec Corp | Wiring substrate for mounting semiconductor |
| WO2011138949A1 (en) * | 2010-05-07 | 2011-11-10 | 旭硝子株式会社 | Substrate on which element is to be mounted, and process for production thereof |
| CN106463465A (en) * | 2014-05-28 | 2017-02-22 | 日本特殊陶业株式会社 | Wiring substrate |
| CN106604567A (en) * | 2015-10-15 | 2017-04-26 | 日本特殊陶业株式会社 | Wiring board and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0917906A (en) * | 1995-06-28 | 1997-01-17 | Toshiba Corp | Semiconductor package |
-
2020
- 2020-08-25 JP JP2020141374A patent/JP7446950B2/en active Active
-
2021
- 2021-08-11 CN CN202110920243.7A patent/CN114126213B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09232466A (en) * | 1996-02-23 | 1997-09-05 | Kyocera Corp | Manufacture of package for semiconductor chip |
| JP2000165043A (en) * | 1998-11-26 | 2000-06-16 | Kyocera Corp | Circuit board |
| JP2005252074A (en) * | 2004-03-05 | 2005-09-15 | Renesas Technology Corp | Semiconductor device and electronic apparatus |
| JP2006186396A (en) * | 2004-07-07 | 2006-07-13 | Nec Corp | Wiring substrate for mounting semiconductor |
| WO2011138949A1 (en) * | 2010-05-07 | 2011-11-10 | 旭硝子株式会社 | Substrate on which element is to be mounted, and process for production thereof |
| CN106463465A (en) * | 2014-05-28 | 2017-02-22 | 日本特殊陶业株式会社 | Wiring substrate |
| CN106604567A (en) * | 2015-10-15 | 2017-04-26 | 日本特殊陶业株式会社 | Wiring board and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP7446950B2 (en) | 2024-03-11 |
| JP2022037312A (en) | 2022-03-09 |
| CN114126213B (en) | 2024-08-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7358445B1 (en) | Circuit substrate and apparatus including the circuit substrate | |
| US5484963A (en) | Ceramic substrate provided with metallized layers for connection with chip, circuit board, or the like | |
| US20080079829A1 (en) | Camera module and method for manufacturing same | |
| EP1843391A1 (en) | Stacked electronic component, electronic device and method for manufacturing stacked electronic component | |
| JP5278149B2 (en) | Circuit board and circuit module | |
| JP4334054B2 (en) | Ceramic circuit board | |
| EP3633719A1 (en) | Electronic component mounting substrate, electronic device, and electronic module | |
| EP2184960A1 (en) | Circuit board and method for manufacturing circuit board | |
| CN114126213B (en) | Wiring substrate | |
| JP2007048844A (en) | Ceramic electronic component and manufacturing method thereof | |
| KR20090051627A (en) | Multilayer ceramic substrate and manufacturing method of the same | |
| JP3091378B2 (en) | Ceramic multilayer substrate | |
| KR100882101B1 (en) | Method of manufacturing the non-shrinkage ceramic substrate | |
| JP6921708B2 (en) | Ceramic substrate | |
| JP7491829B2 (en) | Wiring Board | |
| US20210227690A1 (en) | Ceramic substrate and method for manufacturing ceramic substrate | |
| US12052821B2 (en) | Stacked-layer board, electronic component module, and method of manufacturing stacked-layer board | |
| JP2002033555A (en) | Multiple-piece ceramic substrate | |
| EP3889321B1 (en) | Method for producing a semiconductor substrate arrangement | |
| JP3894841B2 (en) | Multiple wiring board | |
| JP4733061B2 (en) | Plural wiring base, wiring base and electronic device, and division method of multiple wiring base | |
| JP3973727B2 (en) | Ceramic circuit board | |
| JP3850343B2 (en) | Electronic component mounting board | |
| JP2006278808A (en) | Multiple unit wiring board | |
| KR100935973B1 (en) | Method for manufacturing non-shrinkage ceramic substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |