CN114125461A

CN114125461A - Universal video coding conversion circuit and universal video coding equipment

Info

Publication number: CN114125461A
Application number: CN202111435475.XA
Authority: CN
Inventors: 王曦林
Original assignee: Chengdu Goke Microelectronics Co ltd
Current assignee: Chengdu Goke Microelectronics Co ltd
Priority date: 2021-11-29
Filing date: 2021-11-29
Publication date: 2022-03-01
Anticipated expiration: 2041-11-29
Also published as: CN114125461B

Abstract

The application discloses general video coding transform circuit and general video coding equipment, transform circuit includes: the device comprises an eight-point odd line calculation unit, a sixteen-point odd line calculation unit, a thirty-two-point odd line calculation unit, a sixty-four-point odd line calculation unit, a four-point odd line cosine calculation unit, a four-point even line cosine calculation unit, a transformation type selection end, a point number selection end, an input end and an output end; and according to the transformation type selection signal input by the transformation type selection end and the point number selection signal input by the point number selection end, multiplexing of an eight-point odd line calculation unit, a sixteen-point odd line calculation unit, a thirty-two-point odd line calculation unit, a sixty-four-point odd line calculation unit, a four-point odd line cosine calculation unit and a four-point even line cosine calculation unit is realized. The circuit can realize universal video coding conversion, and has the advantages of simple design, easy realization and low research and development cost.

Description

Universal video coding conversion circuit and universal video coding equipment

Technical Field

The invention relates to the technical field of video coding and decoding, in particular to a universal video coding and converting circuit and universal video coding equipment.

Background

General Video Coding equipment (VVC), also known as h.266, is a new generation of Video Coding standard determined by the joint Video experts group following Advanced Video Coding (AVC) and High Efficiency Video Coding (HEVC). Among them, advanced video coding is also referred to as h.264, and high-efficiency video coding is also referred to as h.265. Similar to the previous standard, the VVC adopts a mixed coding framework based on a block structure, and integrates intra-frame and inter-frame prediction, change coding, entropy coding and other modules. In addition to the DCT-II transform in HEVC, VVC allows the maximum size of the transform to be 64x64, and two new transform modes DST-VII and DCT-VIII have been introduced. Namely, the VVC conversion circuit needs to support 4-point, 8-point, 16-point, 32-point, 64-point DCT-II conversion, 4-point, 8-point, 16-point, 32-point DCT-VIII conversion and 4-point, 8-point, 16-point, 32-point DST-VII conversion. The DCT is Discrete Cosine Transform (DCT-II), the DCT-VIII is eighth type DCT-VIII, and the DST-VII is seventh type DCT (DCT sine Transform).

VVC is a new standard that is being developed and is continuously perfected, and because of the difference in transform size and type, the related work on HEVC transform cannot be directly applied to VVC transform. Some researches are made on the basis of the existing HEVC conversion, for example, in the existing design scheme of the general video coding equipment, a 4-32-point DCT-VIII conversion module, a 4-32-point DST-VII conversion module and a 64-point DCT-II conversion module of the existing HEVC are not modified, but the design causes the circuit area of the general video coding equipment to be greatly increased; or, the existing 4-32 point DCT-II conversion module of HEVC is not modified, only a 64 point DCT-II conversion module, a 4-32 point DCT-VIII and a 4-32 point DST-VII multiplexing 64 point DCT-II conversion module are added, but the design scheme is difficult to design and high in research and development cost.

Disclosure of Invention

In view of the above problems, the present application proposes a general video encoding conversion circuit and a general video encoding apparatus.

The embodiment of the present application provides a general video coding conversion circuit, where the conversion circuit includes:

the video coding device comprises an eight-point odd-numbered line calculating unit, a sixteen-point odd-numbered line calculating unit, a thirty-two-point odd-numbered line calculating unit, a sixty-four-point odd-numbered line calculating unit, a four-point odd-numbered line cosine calculating unit, a four-point even-numbered line cosine calculating unit, a transformation type selecting end, a point number selecting end, an input end for inputting a residual matrix and a transformation coefficient matrix and an output end for outputting a video coding result;

the conversion type selection end is used for inputting a conversion type selection signal, and the point number selection end is used for inputting a point number selection signal so as to enable the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit, the sixty-four-point odd line calculation unit, the four-point odd line cosine calculation unit and the four-point even line cosine calculation unit to be multiplexed during the video coding conversion calculation according to the conversion type selection signal and the point number selection signal.

The embodiment of the application discloses a general video coding conversion circuit, eight point odd number line computing units, sixteen point odd number line computing units, thirty-two point odd number line computing units and sixty-four point odd number line computing units all include a plurality of four point odd number line computing units, four point odd number line computing units include a plurality of selectors, and one end of each selector is used for receiving a conversion type selection signal.

The embodiment of the application provides a general video coding transform circuit, eight some odd number row calculating units include 4 four odd number row calculating units, sixteen some odd number row calculating units include 8 four odd number row calculating units, thirty-two some odd number row calculating units include 16 four odd number row calculating units, sixty four-point odd number row calculating units include 32 four odd number row calculating units.

In the general video coding conversion circuit according to the embodiment of the present application, the four-odd-line calculation unit further includes: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders;

each first subtracter is used for performing first subtraction operation on two residual error elements of the residual error matrix and inputting the result of the first subtraction operation to a corresponding selector;

each first multiplier is used for carrying out first multiplication operation on the selection result output by the corresponding selector and the coefficient value of the transformation coefficient matrix;

each first adder is used for performing first addition operation on the multiplication result of the two first multiplication operations.

In the general video coding conversion circuit according to the embodiment of the present application, the four-odd-line calculation unit includes 2 first subtractors, 4 selectors, 4 first multipliers, and 2 first adders.

In the general video coding conversion circuit according to the embodiment of the present application, the four-odd-line calculation unit includes 4 first subtractors, 4 selectors, 4 first multipliers, and 2 first adders.

In the general video coding conversion circuit according to the embodiment of the present application, the four-point even-numbered line cosine calculation unit includes 2 second adders, 2 second multipliers, 1 third adder, and 1 second subtractor;

each second adder is used for performing second addition operation on two residual error elements of the residual error matrix;

each second multiplier is configured to perform a second multiplication operation on a result of the second addition operation output by the corresponding second adder and a coefficient value of the transform coefficient matrix;

the third adder is used for performing third addition operation on the multiplication result of the two second multiplication operations;

the second subtracter is used for carrying out second subtraction operation on the multiplication result of the two second multiplication operations.

In the general video coding conversion circuit according to the embodiment of the present application, the four-point odd line cosine calculating unit includes a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors;

each third subtracter is used for carrying out third subtraction operation on two residual error elements of the residual error matrix;

each third multiplier is configured to perform a third multiplication operation on a result of the third subtraction operation output by the corresponding third subtractor and a coefficient value of the transform coefficient matrix;

each fourth adder is configured to perform a fourth addition operation on a multiplication result of the two third multiplication operations.

In the general video coding conversion circuit according to the embodiment of the present application, the conversion type selection signal includes at least one of a DCT-II type selection signal, a DST-VII type selection signal, and a DCT-VIII type selection signal;

the point number selection signal includes at least one of a four-point selection signal, an eight-point selection signal, a sixteen-point selection signal, a thirty-two-point selection signal, and a sixty-four-point selection signal.

The embodiment of the application also comprises a universal video coding device which comprises the universal video coding conversion circuit.

The method comprises the following steps that an eight-point odd-numbered line calculation unit, a sixteen-point odd-numbered line calculation unit, a thirty-two-point odd-numbered line calculation unit, a sixty-four-point odd-numbered line calculation unit, a four-point odd-numbered line cosine calculation unit, a four-point even-numbered line cosine calculation unit, a transformation type selection end, a point number selection end, an input end for inputting a residual error matrix and a transformation coefficient matrix and an output end for outputting a video coding result are adopted; the conversion type selection end is used for inputting a conversion type selection signal, and the point number selection end is used for inputting a point number selection signal so as to realize multiplexing of the eight-point odd-numbered line calculation unit, the sixteen-point odd-numbered line calculation unit, the thirty-two-point odd-numbered line calculation unit, the sixty-four-point odd-numbered line calculation unit, the four-point odd-numbered line cosine calculation unit and the four-point even-numbered line cosine calculation unit according to the conversion type selection signal and the point number selection signal. The universal video coding circuit can realize universal video coding transformation, is simple in design, easy to realize and low in research and development cost.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the drawings required to be used in the embodiments will be briefly described below, and it should be understood that the following drawings only illustrate some embodiments of the present invention, and therefore should not be considered as limiting the scope of the present invention. Like components are numbered similarly in the various figures.

Fig. 1 is a schematic structural diagram of a general video transcoding circuit according to an embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a four-odd-row calculation unit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram illustrating a structure of another four-odd-row calculating unit according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a four-point even-row cosine calculating unit according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a four-point odd row cosine calculating unit according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of another four-point odd row cosine calculating unit according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an eight-point even-row cosine calculating unit according to an embodiment of the present application;

FIG. 8 is a schematic diagram illustrating an eight-point odd-numbered line calculating unit according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of another eight-point odd-row calculation unit proposed in the embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

Hereinafter, the terms "including", "having", and their derivatives, which may be used in various embodiments of the present invention, are only intended to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing, and should not be construed as first excluding the existence of, or adding to, one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing.

Furthermore, the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which various embodiments of the present invention belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their contextual meaning in the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments of the present invention.

The input of the universal video coding conversion circuit is a residual matrix, the residual matrix is obtained by subtracting a predicted value from an original YUV pixel, and because most images contain more flat areas with slowly converted contents, the image energy can be converted from the dispersed distribution of a spatial domain into the relatively concentrated distribution of a conversion domain through the conversion coding calculation: the low frequency components in the transformed coefficients are concentrated in the upper left corner of the block and the high frequency components are concentrated in the lower right corner of the block. Therefore, the purpose of further removing the spatial redundancy can be achieved through the subsequent quantization and entropy coding processes.

As known from the introduction of the background art, HEVC video coding calculation includes 4-point DCT-II, 8-point DCT-II, 16-point DCT-II, and 32-point DCT-II. VVC video coding includes, in addition to all computations in HEVC video coding, 64-point DCT-II and 4-point DCT-VIII, 8-point DCT-VIII, 16-point DCT-VIII, 32-point DCT-VIII, 4-point DST-VII, 8-point DST-VII, 16-point DST-VII, and 32-point DST-VII.

In general, the transformation circuit of VVC needs to support 4-point, 8-point, 16-point, 32-point, 64-point DCT-II, 4-point, 8-point, 16-point, 32-point DCT-VIII and DST-VII. The DCT is Discrete Cosine Transform (Discrete Cosine Transform), the second type Discrete Cosine Transform (DCT-II) has a different matrix of Transform coefficients than the eighth type Discrete Cosine Transform (DCT-VIII), and the DST is Discrete sine Transform (Discrete Cosine Transform). One-dimensional DCT-II computation of VVC is exactly the same as HEVC except that a 64-point transform is added.

Specifically, the four-point EVEN-row cosine calculating unit (EVEN4), the four-point ODD-row cosine calculating unit (ODD4), the eight-point ODD-row cosine calculating unit (ODD8), the sixteen-point ODD-row cosine calculating unit (ODD16), the thirty-two-point ODD-row cosine calculating unit (ODD32) and the sixty-four-point ODD-row cosine calculating unit (ODD64) are obtained according to the symmetric factorization matrix multiplication of the DCT-II transformation coefficient matrix.

According to the inclusion characteristics of the DCT-II transformation coefficient matrix, an eight-point EVEN row cosine calculating unit (EVEN8) can be realized by EVEN4+ ODD4, a sixteen-point EVEN row cosine calculating unit (EVEN16) can be realized by EVEN8+ ODD8, a thirty-two-point EVEN row cosine calculating unit (EVEN32) can be realized by EVEN16+ ODD16, and a sixty-four-point EVEN row cosine calculating unit (EVEN64) can be realized by EVEN32+ ODD 32.

Referring to fig. 1, the present application shows a general video transcoding circuit comprising: the video coding device comprises an eight-point odd line calculation unit, a sixteen-point odd line calculation unit, a thirty-two-point odd line calculation unit, a sixty-four-point odd line calculation unit, a four-point even line cosine calculation unit, a four-point odd line cosine calculation unit, a transformation type selection end, a point number selection end, an input end for inputting a residual matrix and a transformation coefficient matrix and an output end for outputting a video coding result.

The conversion type selection end is used for inputting a conversion type selection signal, and the point number selection end is used for inputting a point number selection signal, so that the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit, the sixty-four-point odd line calculation unit, the four-point odd line cosine calculation unit and the four-point even line cosine calculation unit are multiplexed during the video coding conversion calculation according to the conversion type selection signal and the point number selection signal.

The general video coding circuit provided by the application can realize VVC video coding conversion, namely, a conversion type selection signal input by a conversion type selection end of the general video coding circuit can be at least one of a DCT-II type selection signal, a DST-VII type selection signal and a DCT-VIII type selection signal, and a point number selection signal input by a point number selection end of the general video coding circuit can be at least one of a four-point selection signal, an eight-point selection signal, a sixteen-point selection signal, a thirty-two-point selection signal and a sixty-four-point selection signal.

The following describes, by way of example, a multiplexing process of each module of the general video coding/conversion circuit in the VVC video coding process:

for example, in the calculation process of the 64-point DCT-II, the type selection signal of the transform type selection end is DCT-II, the input point selection signal of the point selection end is 64 points, and the calculation units determined to be used according to the type selection signal and the point selection signal include a sixty-four-point odd-numbered line calculation unit, a thirty-two-point odd-numbered line calculation unit, a sixteen-point odd-numbered line calculation unit, an eight-point odd-numbered line calculation unit, a four-point odd-numbered line cosine calculation unit, and a four-point even-numbered line cosine calculation unit.

In the calculation process of the 32-point DCT-II, a type selection signal of a transformation type selection end is DCT-II, a point selection signal input by the point selection end is 32 points, and the calculation units determined to be used according to the type selection signal and the point selection signal comprise a thirty-two point odd line calculation unit, a sixteen point odd line calculation unit, an eight point odd line calculation unit, a four point odd line cosine calculation unit and a four point even line cosine calculation unit.

In the calculation process of the 16-point DCT-II, the type selection signal of the transformation type selection end is DCT-II, the point selection signal input by the point selection end is 16 points, and the calculation units determined to be used according to the type selection signal and the point selection signal comprise a sixteen-point odd line calculation unit, an eight-point odd line calculation unit, a four-point odd line cosine calculation unit and a four-point even line cosine calculation unit.

In the calculation process of the 8-point DCT-II, the type selection signal of the transformation type selection end is DCT-II, the point selection signal input by the point selection end is 8 points, and the calculation units determined to be used according to the type selection signal and the point selection signal comprise an eight-point odd line calculation unit, a four-point odd line cosine calculation unit and a four-point even line cosine calculation unit.

In the 4-point DCT-II calculation process, the type selection signal of the transformation type selection end is DCT-II, the point selection signal input by the point selection end is 4 points, and the calculation units required to be used are determined according to the type selection signal and the point selection signal and comprise a four-point odd-numbered line cosine calculation unit and a four-point even-numbered line cosine calculation unit.

In the 32-point DST-VII calculation process, the type selection signal of the conversion type selection end is DST-VII, the point selection signal input by the point selection end is 32 points, and the calculation units required by the type selection signal and the point selection signal comprise sixty-four-point odd-line calculation units.

In the calculation process of the 16-point DST-VII, the type selection signal of the conversion type selection end is DST-VII, the point selection signal input by the point selection end is 16 points, and the calculation units required to be used are determined to comprise 32-point odd-numbered line calculation units according to the type selection signal and the point selection signal.

In the 8-point DST-VII calculation process, the type selection signal of the conversion type selection end is DST-VII, the point selection signal input by the point selection end is 8 points, and the calculation units required to be used are determined to comprise 16-point odd-numbered line calculation units according to the type selection signal and the point selection signal.

In the calculation process of the 4-point DST-VII, the type selection signal of the conversion type selection end is DST-VII, the point selection signal input by the point selection end is 4 points, and the calculation unit required to be used is determined to comprise an 8-point odd-numbered line calculation unit according to the type selection signal and the point selection signal.

In the 32-point DCT-VIII calculation process, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 32 points, and the calculation units required to be used are determined according to the type selection signal and the point selection signal and comprise sixty-four-point odd line calculation units.

In the calculation process of the 16-point DCT-VIII, the type selection signal of the transformation type selection end is DCT-VIII, the input point selection signal of the point selection end is 16 points, and the calculation units required to be used are determined according to the type selection signal and the point selection signal and comprise 32-point odd-numbered line calculation units.

In the 8-point DCT-VIII calculation process, the type selection signal of the transformation type selection end is DCT-VIII, the input point selection signal of the point selection end is 8 points, and the calculation units required to be used are determined according to the type selection signal and the point selection signal and comprise 16-point odd-numbered line calculation units.

In the 4-point DCT-VIII calculation process, the type selection signal of the transformation type selection end is DCT-VIII, the point selection signal input by the point selection end is 4 points, and the calculation units required to be used are determined to comprise 8-point odd-numbered line calculation units according to the type selection signal and the point selection signal.

In a specific video coding process, after a required computing unit is determined according to a type selection signal and a point selection signal, a residual matrix and a transformation coefficient matrix at an input end can be obtained and input into the determined computing unit for corresponding computation, a video coding result is obtained and output to an output end, and different transformation types correspond to different transformation coefficient matrices.

Further, in the general video coding conversion circuit, each of the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit, and the sixty-four-point odd line calculation unit includes a plurality of four-point odd line calculation units, each of the four-point odd line calculation units includes a plurality of selectors, and one end of each of the selectors is configured to receive the conversion type selection signal.

Further, the eight-point odd-numbered line calculation unit includes 4 four-point odd-numbered line calculation units, the sixteen-point odd-numbered line calculation unit includes 8 four-point odd-numbered line calculation units, the thirty-two-point odd-numbered line calculation unit includes 16 four-point odd-numbered line calculation units, and the sixty-four-point odd-numbered line calculation unit includes 32 four-point odd-numbered line calculation units.

Further, the four-odd-row calculation unit includes, in addition to the plurality of selectors: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders; each first subtracter is used for performing first subtraction operation on two residual error elements of the residual error matrix and inputting the result of the first subtraction operation to a corresponding selector; each first multiplier is used for carrying out first multiplication operation on the selection result output by the corresponding selector and the coefficient value of the transformation coefficient matrix; each first adder is used for performing first addition operation on the multiplication result of the two first multiplication operations.

Exemplarily, taking the DCT-II transform of the 4x 4 residual matrix as an example, the transform coefficient matrix of the DCT-II transform is known

If the input residual matrix is

If the two-dimensional DCT-II transform calculation formula is Y ═ AXA ' ═ X ' a ') ' a ', the one-dimensional row transform and the one-dimensional column transform are unified into a matrix multiplication form of X ' a ', and the same circuit can be multiplexed in a time-division manner. Y0, y1, y2 and y3 in the 0 th row of the matrix multiplication result are y0 ═ 64(x0+ x3) +64(x1+ x2), y1 ═ 83(x0-x3) +36(x1-x2), y2 ═ 64(x0+ x3) -64(x1+ x2), y3 ═ 36(x0-x3) -83(x1-x2), respectively; the results of lines 1 to 3 were obtained by replacing x0 to x3 with x4 to x7, x8 to x11, and x12 to x 15.

It will be appreciated that the 4-point DST-VII transform coefficient matrix is

A 4-point DCT-VIII transform coefficient matrix of

Based on the above transformation calculation formulas, in order to enable the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit, and the sixty-four-point odd line calculation unit to perform any one of the transformations of DCT-II, DST-VII, and DCT-VIII, an embodiment of the present application, please refer to fig. 2, proposes a four-point odd line calculation unit composed of 4 first subtractors (J11, J12, J13, J14), 4 selectors (Xz1, Xz2, Xz3, Xz4), 4 first multipliers (X11, X12, X13, X14), and 2 first adders (G11 and G12).

Further, considering that the residual elements input by the first subtractor J11 and the third subtractor J13 shown in fig. 2 are the same, and the residual elements input by the second subtractor J12 and the fourth subtractor J14 are the same, the use of the first subtractor can be reduced.

For example, referring to fig. 3, an embodiment of the present application provides a four-point odd line calculation unit including 2 first subtractors (J11, J12), 4 selectors (Xz1, Xz2, Xz3, Xz4), 4 first multipliers (X11, X12, X13, X14), and 2 first adders (G11 and G12).

Specifically, each selector in each four-point odd-row calculation unit includes a transformation type selection terminal (is-dct2), each selector is configured to control an output terminal of the selector to output information received by a first receiving terminal of the selector or information received by a second receiving terminal of the selector according to a transformation type selection signal received by the transformation type selection terminal (is-dct2), and each multiplier performs a transformation calculation of a corresponding transformation type according to a transformation matrix coefficient value received by the other input terminal.

For example, when the transform type select signal input from the transform type select terminal (is _ DCT2) in fig. 3 is 1, the output terminals of Xz1 and Xz3 output the information received by the respective first receiving terminals 1 (i.e., the difference between x0 and x3), and the output terminals of Xz2 and Xz4 output the information received by the respective first receiving terminals 1 (i.e., the difference between x1 and x2), to perform DCT-II transform based on the output information of the output terminals of the respective selectors and the input transform matrix coefficients; when the transform type select signal input from the transform type select terminal (is _ DCT2) is 0, the output terminals of Xz1 and Xz3 output the information received by the respective second receiving terminals 0 (i.e., x0), and the output terminals of Xz2 and Xz4 output the information received by the respective second receiving terminals 0 (i.e., x1), so as to perform DST-VII transform and/or DCT-VIII transform based on the output information of the output terminals of the respective selectors and the input transform matrix coefficients.

Based on the above transform calculation formula, referring to fig. 4, an embodiment of the present application proposes a four-point even line cosine calculation unit including 2 second adders (G21 and G22), 2 second multipliers (X21 and X22), 1 third adder G31 and 1 second subtractor J21, for performing even line cosine transform in the above calculation, i.e., y0 ═ 64(X0+ X3) +64(X1+ X2) and y2 ═ 64(X0+ X3) -64(X1+ X2).

Each second adder is used for performing second addition operation on two residual error elements of the residual error matrix; each second multiplier is configured to perform a second multiplication operation on a result of the second addition operation output by the corresponding second adder and a coefficient value of the transform coefficient matrix; the third adder is used for performing third addition operation on the multiplication result of the two second multiplication operations; the second subtracter is used for carrying out second subtraction operation on the multiplication result of the two second multiplication operations.

Based on the above transformation calculation formula, the embodiment of the present application provides a four-point odd line cosine calculation unit, which includes a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors; each third subtracter is used for carrying out third subtraction operation on two residual error elements of the residual error matrix; each third multiplier is configured to perform a third multiplication operation on a result of the third subtraction operation output by the corresponding third subtractor and a coefficient value of the transform coefficient matrix; each fourth adder is configured to perform a fourth addition operation on a multiplication result of the two third multiplication operations.

For example, referring to fig. 5, the four-point odd-row cosine calculation unit is composed of 2 fourth adders (G41 and G42), 4 third multipliers (X31, X32, X33, X34), and 4 third subtractors (J31, J32, J33, J34) to perform odd-row cosine transforms in the above calculation, i.e., y1 ═ 83(X0-X3) +36(X1-X2), and y3 ═ 36(X0-X3) -83 (X1-X2).

Further, considering that the residual elements input by the first third subtracter J31 and the third subtracter J33 shown in fig. 5 are the same, and the residual elements input by the second third subtracter J32 and the fourth third subtracter J34 are the same, the use of the third subtracter can be reduced. Therefore, in an embodiment of the present application, please refer to fig. 6, which proposes a four-point odd-row cosine calculating unit further comprising 2 fourth adders (G41 and G42), 4 third multipliers (X31, X32, X33, X34), and 2 third subtractors (J31, J32) for performing odd-row cosine transforms in the above calculation, i.e., y1 ═ 83(X0-X3) +36(X1-X2) and y3 ═ 36(X0-X3) -83 (X1-X2).

It can be understood that the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit and the sixty-four-point odd line calculation unit can selectively perform any one of DCT-II, DST-VII and DCT-VIII conversion through selectors in the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit and the sixty-four-point odd line calculation unit, can be modified on the basis of the DCT-II circuit of the original HEVC, is very simple in circuit modification, and does not need to modify multipliers, adders and output paths of the DCT-II circuit of the original HEVC.

In the four-odd-line calculation unit: the values of the transform matrix coefficients received at the other input of each multiplier vary with the type of transform.

Exemplarily, the transform coefficient matrix of the known 8-point DCT-II is:

comparing a4 and A8 shows that the first 4 columns of the even rows of A8 taken together are equal to a4, the last 4 columns of the 0 th and 4 th rows are equal to the first 4 columns, and the last 4 columns of the 2 nd and 6 th rows are equal in number and opposite in sign to the first 4 columns.

Therefore, the four-point EVEN-row cosine calculating unit (EVEN4) and the four-point ODD-row cosine calculating unit (ODD4) may be configured to perform DCT-II transformation on EVEN rows of the residual matrix of 8 × 8, that is, the eight-point EVEN-row cosine calculating unit (EVEN4) may be configured by two four-point EVEN-row cosine calculating units (EVEN4) and two four-point ODD-row cosine calculating units (ODD4), that is, y4 corresponding to the first EVEN row of the residual matrix of 8 × 8 is 64(x4+ x 4) +64(x4+ x 4) +64(x4+ x 4) +64(x4+ x 4), y4 corresponding to the second EVEN row of the residual matrix of 8 × 8 is 83(x4-x 4) +36(x 4) +83 (x4+ x 4) -x 4+ x + 4+ x + 4+ x + 4+ x + 4+ x + 4+ three x + 4+ three of the residual matrix of the residue matrix of 8+ 4+ x + 4+ x + 4+ x + three x + 4+ x + 4+ x + three x + 4+ x + 4+ three x + 4+ three x + 4+ three x + 4+ three, the specific circuit of y6 ═ 36(x0-x3) -83(x1-x2) +36(x4-x7) -83(x5-x6) corresponding to the fourth even row of the residual matrix 8 × 8 is shown in fig. 7.

Further, referring to fig. 8, the eight-point ODD row calculating unit composed of 4 four-point ODD row calculating units (ODD4') may perform DCT-II transform on the ODD rows of the 8 × 8 residual matrix, may also perform DCT-VIII transform on the ODD rows of the 8 × 8 residual matrix, and may also perform DST-VII transform on the ODD rows of the 8 × 8 residual matrix.

It is understood that since the inputs corresponding to y1 and y5 are the same, and since the inputs corresponding to y3 and y7 are the same, the four-point ODD row calculation unit (ODD4') corresponding to y5 may multiplex the subtractors of the four-point ODD row calculation unit (ODD4') of y1, the four-point ODD row calculation unit (ODD4') corresponding to y7 may multiplex the subtractors of the four-point ODD row calculation unit (ODD4') of y3, two subtractors may be omitted from the four-point ODD row calculation units (ODD4') corresponding to y5 and y7, and the four-point ODD row calculation unit from which the subtractors are omitted may be represented as ODD4 "as shown in fig. 9.

In the example of the DCT-II transform, the eight-point odd-row calculation unit has different values of the transform matrix coefficients from the DCT-II transform in the four-point odd-row calculation unit, for example, the values of the transform coefficients of the DCT-II transform in the original four-point odd-row calculation unit are [83, 36, 36, -83], whereas in the eight-point odd-row calculation unit, the input coefficient matrices of the left two four-point odd-row calculation units should be [89, 75, 75, 18] and [50, 18, -89, -50], and the input coefficient matrices of the right two four-point odd-row calculation units should be [50, -89, 18, -50] and [18, 75, 75, -89 ].

It should be noted that, since the eight-point ODD line calculation unit has the function of the eight-point ODD line cosine calculation unit (ODD8), the function of the sixteen-point EVEN line cosine calculation unit (EVEN16) can be realized based on the eight-point EVEN line cosine calculation unit (EVEN8) shown in fig. 7 and the eight-point ODD line calculation unit shown in fig. 8 (or fig. 9); likewise, the sixteen-point EVEN-row cosine calculating unit (EVEN16) and the sixteen-point odd-row calculating unit may implement the function of the thirty-two-point EVEN-row cosine calculating unit (EVEN 32); thirty-two EVEN-row cosine calculating unit (EVEN32) and thirty-two odd-row calculating unit may realize the function of sixty-four EVEN-row cosine calculating unit (EVEN 64).

It should be noted that, when the eight-point ODD row calculating unit shown in fig. 8 (or fig. 9) is used to calculate the 4-point DST-VII, the left two ODD lines 4 'calculate the upper two rows, the input transform coefficient matrix should be [29, 55, 74, 74] and [74, 84, 0, -74], the right two ODD lines 4' (or ODD4 ") calculate the lower two rows, and the input transform coefficient matrix should be [84, -29, 55, -84] and [ -74, 55, 74, -29 ]; similarly, when computing the 4-point DCT-VIII, the input transform coefficient matrices for the left two ODDs 4 'should be [84, 74, 74, 0] and [55, 29, -74, -74], and the input coefficient matrices for the right two ODDs 4' (or ODD4 ") should be [55, -74, 29, -74] and [ -29, 84, 84, -55 ].

Similarly, 32-point DCT-VIII/DST-VII can be multiplexed with sixty-four-point odd line calculation units, 16-point DCT-VIII/DST-VII can be multiplexed with thirty-two-point odd line calculation units, and 8-point DCT-VIII/DST-VII can be multiplexed with sixteen-point odd line calculation units.

It can be understood that the general video coding conversion circuit provided by the application comprises an eight-point odd-numbered line calculation unit, a sixteen-point odd-numbered line calculation unit, a thirty-two-point odd-numbered line calculation unit, a sixty-four-point odd-numbered line calculation unit, a four-point odd-numbered line cosine calculation unit and a four-point even-numbered line cosine calculation unit, a conversion type selection end, a point number selection end, an input end for inputting a residual matrix and a conversion coefficient matrix, and an output end for outputting a video coding result; the conversion type selection end is used for inputting a conversion type selection signal, and the point number selection end is used for inputting a point number selection signal so as to realize that the eight-point odd line calculation unit, the sixteen-point odd line calculation unit, the thirty-two-point odd line calculation unit, the sixty-four-point odd line calculation unit, the four-point odd line cosine calculation unit and the four-point even line cosine calculation unit are multiplexed during the video coding conversion calculation according to the conversion type selection signal and the point number selection signal. The video coding circuit is obtained by modifying the DCT-II circuit of the original HEVC, universal video coding conversion can be realized on the circuit, and the circuit is simple in design, easy to realize and low in research and development cost.

Further, the present application provides a generic video coding apparatus, including the generic video coding conversion circuit described in the above embodiments of the present application.

In the several embodiments provided in the present application, it should be understood that the disclosed circuits and devices may be implemented in other manners. The embodiments described above are merely illustrative, and the block diagrams in the figures, for example, illustrate the architecture, functionality, and operation of possible implementations of articles of manufacture according to various embodiments of the present invention. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, each functional module or unit in each embodiment of the present invention may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solution of the present invention or a part of the technical solution that contributes to the prior art in essence can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention.

Claims

1. A general purpose video transcoding circuit, said conversion circuit comprising:

2. The universal video coding conversion circuit according to claim 1, wherein the eight-point odd-numbered line calculation unit, the sixteen-point odd-numbered line calculation unit, the thirty-two-point odd-numbered line calculation unit, and the sixty-four-point odd-numbered line calculation unit each include a plurality of four-point odd-numbered line calculation units, and the four-point odd-numbered line calculation unit includes a plurality of selectors, one end of each selector being configured to receive the conversion type selection signal.

3. The universal video coding conversion circuit according to claim 2, wherein said eight-point odd-numbered line calculation unit comprises 4 said four-point odd-numbered line calculation units, said sixteen-point odd-numbered line calculation unit comprises 8 said four-point odd-numbered line calculation units, said thirty-two-point odd-numbered line calculation unit comprises 16 said four-point odd-numbered line calculation units, and said sixty-four-point odd-numbered line calculation unit comprises 32 said four-point odd-numbered line calculation units.

4. The universal video transcoding circuit of claim 2 wherein the four odd row calculation unit further comprises: a plurality of first subtractors, a plurality of first multipliers and a plurality of first adders;

5. The universal video transcoding circuit of claim 4 wherein said four-odd row calculation unit comprises 2 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.

6. The universal video transcoding circuit of claim 4 wherein said four-odd row calculation unit comprises 4 first subtractors, 4 selectors, 4 first multipliers and 2 first adders.

7. The universal video transcoding circuit of claim 1 wherein said four-even line cosine calculation unit comprises 2 second adders, 2 second multipliers, 1 third adder and 1 second subtractor;

8. The universal video transcoding circuit of claim 1 wherein said four-odd row cosine calculation unit comprises a plurality of fourth adders, a plurality of third multipliers and a plurality of third subtractors;

9. The generic video transcoding circuit of any of claims 1 to 8 wherein the transform type selection signal comprises at least one of a DCT-II type selection signal, a DST-VII type selection signal, and a DCT-VIII type selection signal;

10. A general video coding device, comprising the general video transcoding circuit of any of claims 1 to 9.