CN114123731A - Multi-parallel IPM fault protection device, system and method - Google Patents

Abstract

The invention discloses a multi-parallel IPM fault protection device, a system and a method, wherein the device comprises a main control module and a fault identification positioning module which are mutually connected, the fault identification positioning module comprises a first level conversion unit and a latch unit which are mutually connected, the input end of the latch unit is accessed to a plurality of fault signals of the parallel IPM for latching, the latch signals are output to the main control module after being subjected to level conversion by the first level conversion unit, and the main control module is used for carrying out fault identification positioning. The invention can realize the fault protection of a plurality of IPMs connected in parallel at the same time, and has the advantages of simple structure, low cost, high fault protection efficiency and precision and the like.

Description

Multi-parallel IPM fault protection device, system and method

Technical Field

The invention relates to the technical field of IPM (Intelligent Power Module) fault protection, in particular to a multi-parallel IPM fault protection device, system and method.

Background

The IPM (intelligent power module) integrates a power switch device and a driving circuit together, and also integrates a short-circuit protection, an under-voltage protection and other fault output circuits and a device temperature output function inside, so that the IPM has the advantages of not only high current density, low saturation voltage and high voltage resistance of a GTR (high-power transistor), but also high input impedance, high switching frequency and low driving power of a MOSFET (field effect transistor). The IPM also has the functions of fault self-diagnosis and protection, and can output a fault signal when a fault occurs so as to ensure that the IPM is not damaged.

In load-specific situations, IPM typically requires multiple parallel connections to be used together to drive the load together. Because numerous components are integrated in the IPM, the components are mutually associated and influenced, various faults can occur in the use process, the anti-interference capability of the IPM after parallel connection is worse, once the IPM fails, the stable reliability of the whole system can be influenced, the stable operation of the whole system is not facilitated, and therefore precise and effective fault protection on the parallel IPM is very necessary.

For the fault protection of the IPM, currently, the fault protection method is usually directed at a single IPM, that is, a fault signal output by each single IPM is monitored and identified, but when the method is applied to a situation where a plurality of IPMs are connected in parallel, each IPM continuously outputs a signal, the output signal may be a normal signal output by the IPM or a fault feedback signal, the time for maintaining the fault feedback signal sent by the IPM is usually short, the maintaining time is microsecond (greater than or equal to 20us), a certain time is required for sending the fault feedback signal from the fault feedback signal to a detection and identification end of the processor to be transmitted to the detection and identification end of the processor, and since the operating cycle of the processor program has a certain time, the fault feedback signal which cannot be detected for a short maintaining time is easily generated at the detection and identification end, so that the detection is missed, and the purpose of protecting the IPM in time cannot be achieved.

For example, chinese patent application CN201210298006.2 discloses a DSP-based variable frequency speed control system for an induction motor, which uses DSP to send a driving signal to IPM, and uses DSP to receive and process an error signal of IPM, so that when IPM is in error or has other abnormality, DSP can shut off the sending of IPM driving signal, thereby realizing protection of IPM. The scheme is only aiming at the fault protection of a single IPM, when the scheme is applied to the condition that a plurality of IPMs are connected in parallel, because each IPM connected in parallel can continuously output signals at the same time, and the fault feedback signals are easy to cause the condition of missing detection due to short duration, the scheme is not suitable for realizing the fault protection identification of the plurality of IPMs connected in parallel actually.

The fault protection of the multiple parallel IPMs also needs to be low in cost, and the system is simple and reliable, so that the engineering low-cost reliable application is realized. For example, chinese patent application CN201010204616.2 discloses a method for driving and protecting IPM in a motor control system, in the scheme, an FPGA is used to send a driving signal to the IPM, and the FPGA is used to receive and process an error signal of the IPM, so that the FPGA can shut off the sending of the IPM driving signal when the IPM is in error or has other abnormality, thereby protecting the IPM. In the scheme, the computing capability of the FPGA is limited, and a complex motor control algorithm cannot be operated in engineering, so that other control chips are additionally added in the control system for auxiliary processing, the complexity of the system is increased, and the cost is high.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a multi-parallel IPM fault protection device, system and method with simple structure, low cost, high fault protection efficiency and high precision, and the fault protection of a plurality of parallel IPMs can be realized simultaneously.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

the utility model provides a many parallelly connected IPM fault protection device, includes interconnect's main control module, fault identification orientation module includes interconnect's first level switch unit and latch unit, latch unit's input inserts the fault signal of a plurality of parallel connection IPMs and latches, latches the signal process first level switch unit carries out level conversion back, exports for main control module, by main control module carries out fault identification location.

Furthermore, the fault identification and positioning module further comprises a latch reset control unit connected with the latch unit, the latch reset control unit accesses the fault signal of each IPM to perform logic processing, and outputs a logic processing result to a latch reset control end of the latch unit after time delay so as to control the latch unit to perform latch reset.

Further, the latch reset control unit includes a logic processing subunit for performing logic processing and a delay subunit for performing delay, an input end of the logic processing subunit is connected to the fault signal of each IPM, and an output end of the logic processing subunit is connected to the latch reset control end of the latch unit through the delay subunit.

Further, the logic processing subunit includes a plurality of and gates and a nand gate, each and gate is connected to the nand gate, each and gate is connected to two IPM fault signals for and operation, the nand gate performs nand operation on the result output by each and gate, and the output result is provided to the delay subunit.

Furthermore, the delay subunit is any one of a delay circuit based on a capacitor, a delay circuit based on an RC, a delay circuit based on an operational amplifier, and a delay circuit based on a transistor.

The intelligent IPM fault detection system comprises a main control module and a fault detection module, wherein the main control module is connected with the fault detection module, the fault detection module comprises a second level conversion unit and a fault signal logic processing unit which are connected with each other, the fault signal logic processing unit is used for accessing each IPM and carrying out logic processing on fault signals, and logic processing results are output to a detection end of the main control module after being subjected to level conversion by the second level conversion unit so as to realize fault detection.

Further, when the detection end of the main control module receives the signal, the IPM is judged to have a fault, and PWM pulses sent to each IPM are controlled to be blocked.

Further, the fault detection module comprises a plurality of and gates, and each and gate is connected to the fault signals of the two IPMs for and operation and then output.

Furthermore, the main control module adopts a DSP.

Further, the latch unit is a flip-flop or a latch.

Furthermore, the system also comprises an isolation protection circuit arranged between the IPM and the main control module, so as to realize the isolation protection of data interaction between the IPM and the main control module.

Furthermore, the isolation protection circuit comprises an isolation optocoupler and/or an isolation operational amplifier, signals output by the main control module and/or fault signals output by the IPM are transmitted through the isolation optocoupler, and temperature signals output by the IPM are transmitted to the main control module through the isolation operational amplifier.

Further, a multi-parallel IPM system includes a plurality of IPMs for driving a load, each two IPMs constituting a group of IPMs, each of the IPMs being connected in parallel, and a fault protection device as described above connected to each of the IPMs.

Further, every two IPMs share one drive isolation power supply.

A multi-parallel IPM fault protection method is characterized by comprising the following steps:

s01, receiving fault signals of a plurality of IPMs connected in parallel;

s02, latching the received fault signal of each IPM by a latch unit and then outputting the fault signal;

and S03, performing level conversion on the latched output fault signal, and then performing fault identification and positioning.

Further, the step S03 includes a latch reset control step, including: and accessing the fault signal of each IPM for logic processing, and outputting a logic processing result to the reset control end of the latch unit after delaying so as to control the latch unit to latch and reset.

Further, in step S02, the logic processing result is obtained by performing an and operation on the failure signals of every two IPMs, and performing an and operation on all the and operation results.

Further, the method also comprises a fault detection step, which comprises the following steps: accessing the fault signal of each IPM for logic processing, and outputting a logic processing result to a detection end after level conversion; and when the detection end detects the signal, judging that the IPM has a fault.

Further, in the fault detection step, specifically, an and operation is performed on every two fault signals in the fault signals of each IPM to obtain the logic processing node.

Compared with the prior art, the invention has the advantages that:

1. according to the invention, the latch unit receives fault signals of each IPM connected in parallel, the fault signals are output to the main control module after being latched through level conversion, the main control module 1 performs fault identification, meanwhile, the fault signals of each IPM connected in parallel are accessed to the latch reset control unit, the logic processing result is output to the reset control end of the latch unit after being delayed after logic processing, when the IPM feeds back the fault signals, effective control signals are generated to the latch reset control unit after logic processing for a certain time, as the fault signals are latched, the fault identification and positioning can be effectively ensured to be accurately identified, and meanwhile, the continuous execution of fault identification and positioning can be realized through delayed latch reset control, so that the problem of accurate positioning and identification of a plurality of IPM fault signals can be effectively solved.

2. The invention realizes the fault identification and positioning by the hardware circuits such as the latch unit, the latch reset control unit and the like, has simple circuit structure, can reduce the complexity and the cost of realization, realizes the fault identification and positioning by means of hardware, and can improve the reliability and the efficiency of the identification and positioning.

3. The invention further realizes a rapid fault detection function based on a hardware detection mode, when IPM faults exist, fault signals of each IPM are subjected to logic processing and then directly subjected to level conversion by the second level conversion unit and then sent to the detection end of the main control module, so that the fault signals can be rapidly judged as long as the detection end of the main control module receives effective signals.

Drawings

Fig. 1 is a schematic structural diagram of a multi-parallel IPM fault protection apparatus according to embodiment 1 of the present invention.

Fig. 2 is a schematic diagram of the isolation protection circuit arrangement in embodiment 1 of the present invention.

FIG. 3 is a schematic diagram of two groups of IPMs in a multi-parallel IPM system according to embodiment 1 of the present invention.

Fig. 4 is a schematic structural diagram of a multi-parallel IPM fault protection apparatus in embodiment 2 of the present invention.

Illustration of the drawings: 1. a main control module; 2. a fault identification and positioning module; 201. a first level conversion unit; 202. a latch unit; 203. a latch reset control unit; 231. a logical processing subunit; 232. a delay subunit; 3. a fault detection module; 301. a second level conversion unit; (ii) a 302. And a fault signal logic processing unit.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

Example 1:

as shown in fig. 1, the multi-parallel IPM fault protection apparatus of this embodiment includes a main control module 1 and a fault identification and location module 2 that are connected to each other, where the fault identification and location module 2 includes a first level shifter 201 and a latch unit 202 that are connected to each other, an input end of the latch unit 202 is connected to fault signals of multiple parallel IPMs for latching, the latch signals are subjected to level shifting by the first level shifter 201, and then output to the main control module 1, and the main control module 1 performs fault identification and location.

In the embodiment, the latch unit 202 receives the fault signal of each IPM connected in parallel (if a fault occurs, the fault signal corresponds to an effective signal state, and if no fault occurs, the fault signal corresponds to an invalid signal state), the latched signal is subjected to level conversion by the smoothing module 2 and is output to the main control module 1, and the main control module 1 performs fault identification.

In this embodiment, the failure identification and location module 2 further includes a latch reset control unit 203 connected to the latch unit 202, where the latch reset control unit 203 accesses the failure signal of each IPM to perform logic processing, and outputs a logic processing result to a latch reset control terminal of the latch unit 202 after a delay, so as to control the latch unit 202 to perform latch reset. The logic processing is to perform logic operation on each fault signal to obtain a result of whether a fault signal exists (if an IPM fault signal exists, an effective signal is obtained correspondingly after the logic processing, otherwise, an invalid signal is obtained correspondingly), and when an IPM feeds back the fault signal, an effective control signal is generated to the latch reset control unit 203 after the logic processing. Since the logic processing result received by the latch reset control unit 203 is subjected to the delay processing, the fault signal is latched by the latch unit 202, the main control module 1 performs fault identification, and after a period of time, the latch unit 202 is controlled to perform latch reset to wait for the main control module 1 to perform reset after identification is completed, and to wait for the next fault. According to the embodiment, continuous execution of fault identification and positioning can be realized through delayed latch reset control, and the problem of accurate positioning and identification of a plurality of IPM fault signals can be effectively solved by combining the fault signal latch. In this embodiment, the latch reset control unit 203 includes a logic processing subunit 231 for performing logic processing and a delay subunit 232 for performing delay, an input end of the logic processing subunit 231 accesses the fault signal of each IPM, and an output end is connected to the latch reset control end of the latch unit 202 through the delay subunit 232. The logic processing subunit 231 performs logic operation on each fault signal through logic processing to obtain a result of whether a fault signal exists, that is, if an IPM fault signal exists, a valid signal is obtained after the logic processing, otherwise, an invalid signal is obtained correspondingly. The valid signal and the invalid signal correspond to valid and invalid states of the latch reset control terminal of the latch reset control unit 203, that is, when the logic processing subunit 231 outputs a valid signal, it indicates that an IPM fault signal exists, and then the valid signal is sent to the latch reset control terminal after a delay to control the latch reset, otherwise, if the logic processing subunit 231 outputs an invalid signal, it indicates that the IPM fault signal does not exist, it is not necessary to send a signal to the latch reset control terminal.

In this embodiment, the logic processing subunit 231 specifically includes a plurality of and gates and a nand gate, each and gate is connected to the nand gate, each and gate accesses the fault signals of two IPMs to perform and operation, so as to perform and operation on the fault signals of every two IPMs, the nand gate performs nand operation on the result output by each and gate, and the output result is provided to the delay subunit 232. When an IPM sends a fault signal, at least one path of the fault signal after being processed by the and gate changes to a low level (no fault is corresponding to a high level, and a fault is corresponding to a low level), a rising edge can be generated after being processed by the nand gate, and the signal is output to the latch reset control unit 203 after passing through the delay subunit 232, so that latch control can be realized.

It can be understood that, if the latch reset control terminal of the latch reset control unit 203 is effective at the time of a falling edge, the structure of the logic processing subunit 231 may be adjusted accordingly, for example, the nand gate is replaced by an and gate, so that when there is a fault signal, the falling edge is generated to drive the latch unit 202 to reset, which may be determined according to actual requirements.

In this embodiment, the delay subunit 232 may adopt a capacitor-based delay circuit, an RC-based delay circuit, an operational amplifier-based delay circuit, a transistor-based delay circuit, and the like, which may be determined according to actual requirements. The delay time of the delay subunit 232 may be specifically determined according to the time required by the main control module 1 to implement fault identification, so that after the main control module 1 completes fault identification, the latch unit 202 is controlled to perform latch reset, and the specific delay time setting may be set according to actual requirements.

In this embodiment, the latch unit 202 may specifically be implemented by using a flip-flop or a latch, where the flip-flop may be implemented by using a D flip-flop, the latch may be implemented by using an SR latch, a signal output end of the flip-flop or the latch is connected to a fault signal output end of each IPM, an output end of the flip-flop or the latch is connected to an input end of the first level shifter 201, and a reset control end of the flip-flop or the latch is connected to an output end of the latch reset control unit 203. The latch unit 202 may be implemented by circuits and devices other than flip-flops and latches that can implement a latch function.

In this embodiment, the system further includes a fault detection module 3 connected to the main control module 1, the fault detection module 5 includes a second level shift unit 301 and a fault signal logic processing unit 302 that are connected to each other, the fault signal logic processing unit 302 is configured to access fault signals of each IPM for logic processing, and a logic processing result is output to the detection end of the main control module 1 after being subjected to level shift by the second level shift unit 301, so as to implement fault detection. The logic processing is to perform logic operation on each fault signal to obtain a result of whether a fault signal exists, if an IPM fault signal exists, the logic processing is performed and then a valid signal is obtained correspondingly, otherwise an invalid signal is obtained correspondingly, the logic processing is performed on each fault signal of the IPM, the fault signal is subjected to level conversion directly by the second level conversion unit 301 and then sent to the detection end of the main control module 1, when the fault signal is sent by the IPM, the valid signal is generated after the logic processing and then output to the detection end of the main control module 1, and the fault signal can be judged to exist only when the detection end of the main control module 1 receives the valid signal, so that the rapid fault detection of the fault can be realized. This fault detection compares and will be faster in above-mentioned fault identification location, because combine this fault detection and above-mentioned fault identification location, when having the IPM trouble, at first can the short-term test to the emergence of trouble to make can in time acquire this fault state, then can realize accurate fault identification location through the fault identification location, determine the position that the trouble took place, realize quick fault detection and the accurate discernment location dual function of trouble.

In this embodiment, when the detection end of the main control module 1 receives the signal, it is determined that the IPM fails, and the pulse blocking is controlled to be performed, so that the pulse output can be blocked quickly according to the failure signal, thereby achieving the effect of effectively protecting the IPM and the peripheral circuit.

In this embodiment, the fault signal logic processing unit 302 specifically includes a plurality of and gates, each and gate accesses the fault signals of two IPMs for and operation and outputs the fault signals of each two IPMs, so that when an IPM sends a fault signal, at least one path of the fault signals processed by the and gates is changed into a low level (no fault is corresponding to a high level, and a fault is corresponding to a low level), and the fault signals are output to the main control module 1 through the second level conversion unit 301.

In this embodiment, the first level shifter 201 and the second level shifter 301 are both configured to shift the received level signal to match detection of the main control module 1, and if there is a fault signal in the signal after logic processing, an effective level may be generated after the signal is shifted by the first level shifter 201 and the second level shifter 301 and provided to a signal input end or a detection end of the main control module 1, so that fault identification and location may be performed after the effective level is received at the signal input end of the main control module 1, and after the detection end detects the effective level, it may be determined that an IPM fault signal exists. The first level shift unit 201 and the second level shift unit 301 may be implemented by two separate conversion circuits, or may be implemented by one integrated conversion circuit.

In this embodiment, the system further includes an isolation protection circuit disposed between the IPM and the main control module 1, so as to implement isolation protection of data interaction between the IPM and the main control module 1, and further improve reliability of data interaction between the IPM and the main control module 1.

As shown in fig. 2, the isolation protection circuit in this embodiment includes an isolation optocoupler and an isolation operational amplifier, a signal output by the main control module 1 and a fault signal output by the IPM are transmitted through the isolation optocoupler, and a temperature signal output by the IPM is transmitted to the main control module 1 through the isolation operational amplifier. The embodiment specifically and respectively sets a first optical coupler to transmit a signal (PWM pulse signal) output by the main control module 1 to the IPM through the first optical coupler, and sets a second optical coupler to transmit a fault signal output by the IPM to the main control module 1 through the second optical coupler. The isolation optocoupler can specifically adopt a high-speed optocoupler with a high common mode rejection ratio, and can also adopt other types of optocouplers according to actual requirements. By adopting the full-isolation mode, the IPM and the DSP control signal side are completely isolated by utilizing the isolation optocoupler and the isolation operational amplifier for control, so that the anti-interference performance of the circuit can be greatly enhanced.

As shown in fig. 3, the present embodiment further includes a multi-parallel IPM system, where the multi-parallel IPM system includes a plurality of IPMs for driving a load, each two IPMs form a group of IPMs, and each IPM is connected in parallel, and the above-mentioned fault protection device connected to each IPM is further included, so that when an IPM fails, a fault and a fault location can be accurately identified, and the stable reliability of each parallel IPM can be ensured. When designing a PCB of a circuit, the path length of a current return path, namely the path length of the circuit (1) in figure 1, can be reduced, so as to meet the requirement of improving the anti-interference performance of the circuit.

In this embodiment, every two IPMs share one driving isolation power supply (e.g., +15V isolation power supply module in fig. 3), that is, a mode that 2 IPMs share one driving power supply is adopted, so that a PCB can be finely designed, and a current return path is reduced, thereby enhancing the anti-interference performance of a circuit, and reducing the number of isolation power supplies and the cost of equipment. Of course, other driving power supply providing modes may be adopted according to actual requirements, for example, an IPM is powered by one driving power supply to one IPM alone, and then a plurality of IPMs are processed in parallel.

The method for protecting the multiple parallel IPM faults in the embodiment comprises the following steps:

s01, receiving fault signals of a plurality of IPMs connected in parallel;

s02, latching the received fault signal of each IPM by the latch unit 202 and then outputting the fault signal;

and S03, performing level conversion on the latched output fault signal, and then performing fault identification and positioning.

In this embodiment, step S03 further includes a latch reset control step, which includes: the fault signal accessed to each IPM is logically processed, and the logic processing result is delayed and then output to the reset control end of the latch unit 202, so as to control the latch unit 202 to latch and reset.

In step S02, the logical processing result is obtained by performing and operation on the failure signals of every two IPMs and performing nand operation on all the and operation results.

The embodiment further comprises a fault detection step, which comprises the following steps: accessing fault signals of each IPM for logic processing, and outputting logic processing results to a detection end after level conversion; when the signal is detected by the detection end, the IPM is judged to be in fault.

In the step of detecting faults in this embodiment, two fault signals of each IPM are specifically and-operated to obtain a logic processing result.

The principle of the multi-parallel IPM fault protection method in this embodiment is the same as that of the multi-parallel IPM fault protection apparatus, and is not described herein again.

Example 2:

the multi-parallel IPM system of the present embodiment specifically includes 6 IPMs, each 2 IPMs is a group of IPMs, and the 6 IPMs are connected in parallel to drive the load. The 6 IPMs adopt the same direct-current high-voltage power supply and are connected in parallel to drive different coils of the magnetic suspension motor so as to reduce the length of a current backflow path and improve the anti-interference performance of a circuit, and meanwhile, the design cost is considered, 2 IPMs are adopted on the IPM driving power supply side to share one driving isolation power supply, namely, each 2 IPMs adopt the same IPM driving power supply, and the power supply on the control side is isolated from the driving power supply.

The multi-parallel IPM fault protection device comprises a main control module 1 and a fault identification positioning module 2 which are connected with each other, wherein the fault identification positioning module 2 comprises a first level conversion unit 201, a latch unit 202 and a latch reset control unit 203 which are connected in sequence, the input end of the latch unit 202 is accessed to fault signals of a plurality of IPMs connected in parallel for latching, the latch signals are output to the main control module 1 after being subjected to level conversion through the first level conversion unit 201, fault identification positioning is carried out by the main control module 1, the latch reset control unit 203 is accessed to the fault signals of each IPM for logic processing, and logic processing results are output to a latch reset control end of the latch unit 202 after being delayed so as to control the latch unit 202 to carry out latch reset. The specific main control module 1 is realized by adopting a DSP, the IPM is subjected to on-off control by the DSP, the latch unit 202 is realized by adopting a D trigger, and the high-efficiency driving and fault protection of the multi-parallel IPM can be effectively realized by fully utilizing the strong calculation performance of the DSP and combining the trigger and the like.

In this embodiment, the latch reset control unit 203 includes a logic processing subunit 231 for performing logic processing and a delay subunit 232 for performing delay, an input end of the logic processing subunit 231 accesses the fault signal of each IPM, and an output end is connected to the latch reset control end of the latch unit 202 through the delay subunit 232. The logic processing subunit 231 specifically includes 3 and gates and one nand gate, each and gate is connected to the two IPM fault signals for and operation, the nand gate performs nand operation on the result output by each and gate, and the output result is provided to the delay subunit 232. The delay subunit 232 is specifically a capacitor.

In this embodiment, the system further includes an isolation protection circuit disposed between the IPM and the main control module 1, so as to implement isolation protection of data interaction between the IPM and the main control module 1, and further improve reliability of data interaction between the IPM and the main control module 1. The isolation protection circuit comprises an isolation optocoupler and an isolation operational amplifier, and particularly, as shown in fig. 2, a signal output by the main control module 1 and a fault signal output by the IPM are transmitted through the isolation optocoupler, and a temperature signal output by the IPM is transmitted to the main control module 1 through the isolation operational amplifier. In order to enhance the anti-interference capability of the circuit, in the embodiment, the PWM signal is generated by the DSP and is sent to the IPM through optical coupler isolation, the fault feedback signal of the IPM is also sent back to the DSP after being isolated by the optical coupler, and the optical coupler is a high-speed optical coupler with a high common-mode rejection ratio, so as to enhance the anti-interference capability of the circuit. And the temperature feedback signal of the IPM is sent to an on-chip AD module of the DSP after being isolated by an isolation operational amplifier. The isolation operational amplifier is an isolation operational amplifier with single-side voltage input and differential voltage output, and has the performance of isolating 3KV voltage. Every 2 IPMs adopt the same isolation power supply to supply power for isolation devices (optical couplers and isolation operational amplifiers), as shown in the following figure +5V isolation power supply module 1. Capacitors are placed in the path of fault feedback and temperature feedback, close to the device pins, for filtering.

In this embodiment, the system further includes a fault detection module 3 connected to the DSP, the fault detection module 5 includes a second level conversion unit 301 and a fault signal logic processing unit 302 that are connected to each other, the fault signal logic processing unit 302 is configured to access fault signals of each IPM for logic processing, and a logic processing result is output to a detection end (TZ detection pipe) of the DSP after being subjected to level conversion by the second level conversion unit 301, so as to implement fault detection, that is, fault feedback detection is also completed by the DSP, and a TZ pin on the DSP can be used to quickly detect a fault, thereby implementing DSP pulse blocking, and protecting the IPM module. In this embodiment, the second level shift unit 301 and the first level shift unit 201 are implemented by using an integrated level shift chip.

Since there are 6 IPM fault feedback signals, as shown in fig. 4, the present embodiment divides the fault feedback signals of 6 IPMs into two parts for detection processing, including:

and one part is the rapid detection processing of the fault signal, which is used for rapidly blocking the PWM output pulse of the DSP after the IPM fault signal is detected. The part carries out AND processing on the fault feedback signals of 6 paths of IPMs pairwise by using a 2-input AND gate, and directly sends 3 processed signals to a TZ detection pin of the DSP through a level converter. The TZ pin of the DSP is a hardware detection pin, and when a signal is detected, the hardware directly blocks the output of the PWM pulse, so that the running time of the program blocking pulse is reduced. Because the part of the IPM fault feedback detection circuit is a quick fault detection circuit, which IPM reports the fault signal cannot be accurately judged, and the other part of the IPM fault feedback detection circuit completes the function.

The other part is the identification positioning detection processing of the fault signal. Because the maintenance time of the fault feedback signal of the IPM is short, in order to identify and position the fault IPM, the IPM fault signal is sent to the D trigger, and the signal from the D trigger is sent to the GPIO port of the DSP through the level converter for program judgment and identification; and the three fault feedback signals processed by the AND gate and the reset signal of the DSP pass through the NAND gate together, are subjected to capacitance delay processing and then are sent to a control pin of the D trigger. When a fault occurs, at least one path of signal of three paths of fault signals processed by the AND gate is changed into low level, the low level is processed by the NAND gate, and the low level is delayed by the capacitor, at this time, a rising edge is generated to a control pin of the D trigger, at this time, an input port signal of the D trigger is earlier than a control pin signal of the D trigger, so that a signal at the input end of the D trigger is latched and output to the DSP, and the DSP outputs a reset signal again after the DSP accurately identifies and positions the IPM fault, latches and resets the D trigger to wait for the next fault.

Through the device in the embodiment, the pulse output can be quickly blocked according to the fault signals to achieve the effect of protecting the IPM and peripheral circuits, and the accurate positioning and identification of a plurality of IPM fault signals can be realized, so that the problem of the accurate positioning and identification of the plurality of IPM fault signals is solved.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims (19)

1. A multi-parallel IPM fault protection device is characterized in that: the intelligent power supply device comprises a main control module (1) and a fault identification positioning module (2) which are connected with each other, wherein the fault identification positioning module (2) comprises a first level conversion unit (201) and a latch unit (202) which are connected with each other, the input end of the latch unit (202) is connected into fault signals of a plurality of IPMs connected in parallel to latch, the latch signals pass through the first level conversion unit (201) after level conversion, the output is given to the main control module (1), and the main control module (1) performs fault identification positioning.

2. The multi-parallel IPM fault protection device according to claim 1, wherein said fault identification and location module (2) further comprises a latch reset control unit (203) connected to said latch unit (202), said latch reset control unit (203) accesses said fault signal of each IPM for logic processing, and outputs the logic processing result to the latch reset control end of said latch unit (202) after a delay, so as to control said latch unit (202) to perform latch reset.

3. The multi-parallel IPM fault protection apparatus of claim 2, wherein: the latch reset control unit (203) comprises a logic processing subunit (231) for performing logic processing and a delay subunit (232) for performing delay, wherein the input end of the logic processing subunit (231) is connected to the fault signal of each IPM, and the output end of the logic processing subunit is connected to the latch reset control end of the latch unit (202) through the delay subunit (232).

4. The multi-parallel IPM fault protection device of claim 3, wherein: the logic processing subunit (231) comprises a plurality of AND gates and a NAND gate, each AND gate is connected with the NAND gate, each AND gate is connected with two IPM fault signals for AND operation, the NAND gate performs NAND operation on the result output by each AND gate, and the output result is provided for the delay subunit (232).

5. The multi-parallel IPM fault protection device of claim 3, wherein: the delay subunit (232) is any one of a delay circuit based on a capacitor, a delay circuit based on an RC, a delay circuit based on an operational amplifier and a delay circuit based on a transistor.

6. The multi-parallel IPM fault protection apparatus of claim 1, wherein: still include with fault detection module (3) that master control module (1) is connected, fault detection module (5) are including interconnect's second level switch unit (301) and trouble signal logic processing unit (302), trouble signal logic processing unit (302) are used for inserting each IPM the trouble signal carries out logic processing, and the logic processing result process second level switch unit (301) carry out the level conversion after output for the sense terminal of master control module (1) to realize fault detection.

7. The multi-parallel IPM fault protection device of claim 6, wherein: and when the detection end of the main control module (1) receives the signal, judging that IPM faults exist, and controlling and blocking PWM pulses sent to each IPM.

8. The multi-parallel IPM fault protection apparatus of claim 7, wherein: the fault detection module (3) comprises a plurality of AND gates, and each AND gate is connected with the fault signals of the two IPMs for AND operation and then outputs the fault signals.

9. The multi-parallel IPM fault protection device of any of claims 1 to 8, wherein: the main control module (1) adopts a DSP.

10. The multi-parallel IPM fault protection device of any of claims 1 to 8, wherein: the latch unit (202) is a flip-flop or a latch.

11. The multi-parallel IPM fault protection device of any of claims 1 to 8, wherein: the intelligent IPM data protection system further comprises an isolation protection circuit arranged between the IPM and the main control module (1) so as to realize isolation protection of data interaction between the IPM and the main control module (1).

12. The multi-parallel IPM fault protection apparatus of claim 11, wherein: the isolation protection circuit comprises an isolation optocoupler and/or an isolation operational amplifier, signals output by the main control module (1) and/or fault signals output by the IPM are transmitted through the isolation optocoupler, and temperature signals output by the IPM are transmitted to the main control module (1) through the isolation operational amplifier.

13. A multi-parallel IPM system comprising a plurality of IPMs for driving a load, each two IPMs constituting a group of IPMs, each of said IPMs being connected in parallel, further comprising a fault protection device according to claims 1 to 12 connected to each of said IPMs.

14. The multi-parallel IPM system of claim 13, wherein each two of said IPMs share a drive isolation power supply.

15. A multi-parallel IPM fault protection method is characterized by comprising the following steps:

s01, receiving fault signals of a plurality of IPMs connected in parallel;

s02, latching the received fault signal of each IPM by a latch unit (202) and then outputting the fault signal;

and S03, performing level conversion on the latched output fault signal, and then performing fault identification and positioning.

16. The multi-parallel IPM fault protection method of claim 15, wherein said step S03 further includes a latch reset control step comprising: and accessing the fault signal of each IPM for logic processing, and outputting a logic processing result to a reset control end of the latch unit (202) after delaying so as to control the latch unit (202) to carry out latch reset.

17. The method according to claim 15, wherein in step S02, the logic processing result is obtained by performing an and operation on the failure signals of every two IPMs, and performing an and operation on all the and operation results.

18. The multi-parallel IPM fault protection method of claim 15, 16 or 17, further comprising a fault detection step comprising: accessing the fault signal of each IPM for logic processing, and outputting a logic processing result to a detection end after level conversion; and when the detection end detects the signal, judging that the IPM has a fault.

19. The method according to claim 18, wherein in the fault detection step, the logical processing result is obtained by performing an and operation on every two fault signals of the fault signals of each IPM.

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