CN114122107A - P-GaN normally-closed power device with periodic gate structure - Google Patents

P-GaN normally-closed power device with periodic gate structure Download PDF

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CN114122107A
CN114122107A CN202111264534.1A CN202111264534A CN114122107A CN 114122107 A CN114122107 A CN 114122107A CN 202111264534 A CN202111264534 A CN 202111264534A CN 114122107 A CN114122107 A CN 114122107A
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gan
periodic
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power device
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CN114122107B (en
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王洪
高升
谢子敬
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South China University of Technology SCUT
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses a p-GaN normally closed power device with a periodic gate structure. The device comprises a substrate, a nucleating layer, a buffer layer, a channel layer, an insertion layer and a barrier layer from bottom to top; a source electrode and a drain electrode are arranged above the barrier layer, a periodic p-GaN/InGaN layer formed on the barrier layer is arranged between the source electrode and the drain electrode, and a grid electrode is arranged on the periodic p-GaN/InGaN layer. Multiple layers of In with low indium component are periodically distributed on the periodic p-GaN/InGaN layer from bottom to topbGa1‑bN layer and In of high indium compositionaGa1‑aN layer, and adjacent In of low indium compositionbGa1‑bN layer and In of high indium compositionaGa1‑aAnd p-GaN layers are arranged between the N layers. The invention can effectively improve the ionization efficiency of Mg in p-GaN, thereby ensuring the two-dimensional electron gas consumption under the gridThe doping concentration of Mg can be reduced on the basis.

Description

P-GaN normally-closed power device with periodic gate structure
Technical Field
The invention relates to the field of semiconductors, in particular to a p-GaN normally-closed power device with a periodic gate structure.
Background
With the rapid development of high-voltage switches and radio frequency circuits, high electron mobility transistors (GaN HEMTs) have received increasing attention. Normally-off devices are the mainstream trend for their applications in terms of safety and cost. From the current research, the groove type device and the fluorine ion implantation type device have a great bottleneck in the aspects of precise process control, damage caused by the process and the like, and although some schemes for reducing the damage have been proposed, the problems of the reliability and the process repeatability of the device are not well solved.
The existing mainstream scheme is to use a p-GaN layer device to deplete the two-dimensional electron gas under the gate by growing a p-GaN layer. There are still some problems: because the ionization efficiency of Mg in p-GaN is extremely low and is about 1% -2% of the doping concentration of Mg, the two-dimensional electron gas under the grid can be effectively exhausted by the higher doping concentration. This can cause Mg to diffuse readily into the barrier and channel layers, resulting in degraded device reliability (n.e. posthuma, et al, 201628)thISPSD conference). Therefore, on the one hand, there is a need to improve the ionization efficiency of Mg; on the other hand, it is necessary to reduce the doping hole concentration or to introduce a blocking layer to limit Mg down-diffusion.
Disclosure of Invention
Based on the above, in order to solve the problems in the prior art, the invention provides a p-GaN normally-closed power device with a periodic gate structure. The stepped polarization electric field among the p-GaN/InGaN layers with the variable indium components effectively improves the ionization efficiency of Mg, and the periodic InGaN layers also play a role in blocking Mg from diffusing to the barrier layer and the channel layer.
The object of the invention is at least achieved by one of the prior art solutions.
A p-GaN normally closed power device with a periodic gate structure comprises a substrate, a nucleating layer, a buffer layer, a channel layer, an insertion layer and a barrier layer from bottom to top;
a source electrode and a drain electrode are arranged above the barrier layer, a periodic p-GaN/InGaN layer formed on the barrier layer is arranged between the source electrode and the drain electrode, and a grid electrode is arranged on the periodic p-GaN/InGaN layer.
Further, the periodic p-GaN/InGaN layer is periodically distributed with a plurality of layers of In with low indium composition from bottom to topbGa1-bN layer and In of high indium compositionaGa1-aN layers of, and adjacent low indium groupsIn is dividedbGa1-bN layer and In of high indium compositionaGa1-aAnd p-GaN layers are arranged between the N layers.
Further, the p-GaN of the p-GaN layer is doped with Mg, and the hole concentration is 2E17-2E18 cm-3。
Further, the total thickness of the periodic p-GaN/InGaN layer is 80-120nm, wherein the total thickness of all the p-GaN layers is 60-90nm, and each layer has In with low indium componentbGa1-bThe thickness of the N layer is 5-10nm, and each layer of In with high indium compositionaGa1-aThe thickness of the N layer is 0.5-5 nm.
Further, In of the high indium compositionaGa1-aIn the N layer, 0.3<a<0.7, In of high indium compositionaGa1-aThe number of N layers is not less than 2; in of the low indium componentbGa1-bIn the N layer, 0.05<b<0.3, In of Low indium compositionbGa1-bThe number of N layers is not less than 2; in of high indium compositionaGa1-aN layer and In of low indium compositionbGa1-bThe number of N layers is the same.
Further, the substrate is silicon; the nucleating layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; the barrier layer is AlGaN.
Compared with the prior art, the invention has the following beneficial effects and advantages:
1. the periodic p-GaN/InGaN layer is adopted to replace the p-GaN layer, the ionization efficiency of Mg can be effectively improved by changing a step-type polarized electric field between the p-GaN/InGaN layers with indium components, on one hand, the doping concentration of Mg in the p-GaN can be reduced to a certain extent on the basis of meeting two-dimensional electron gas under a depletion grid, and the diffusion of Mg to a barrier layer and a channel layer is reduced, so that a leakage channel is reduced. On the other hand, In of low indium compositionbGa1-bN has a smaller forbidden band width, InbGa1-bN phase compared with InaGa1-aN, the former has less influence on the threshold voltage at the same thickness.
2. Because the p-GaN layer and the InGaN layer are arranged at intervals periodically, equivalently, a barrier layer is introduced under each layer of p-GaN with small thickness, the diffusion of Mg to the barrier layer and the channel layer can be further effectively reduced, and the reliability of the device is improved.
Drawings
Fig. 1 is a schematic structural diagram of a p-GaN normally-off power device de with a periodic gate structure in an embodiment of the present invention.
Fig. 2 is a simulated transfer curve of a p-GaN normally-off power device with a periodic gate structure corresponding to a control group, an embodiment 1 and an embodiment 2.
Detailed Description
The following examples are presented to further illustrate the practice of the invention, but the practice and protection of the invention is not limited thereto. It is noted that the processes described below, if not specifically described in detail, are all realizable or understandable by those skilled in the art with reference to the prior art.
Example 1:
a p-GaN normally-off power device with a periodic gate structure comprises a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, an insertion layer 105 and a barrier layer 106 from bottom to top as shown in FIG. 1;
a source electrode and a drain electrode are disposed above the barrier layer 106, a periodic p-GaN/InGaN layer 107 formed on the barrier layer is disposed between the source electrode and the drain electrode, and a gate electrode is disposed on the periodic p-GaN/InGaN layer.
In this embodiment, the substrate is silicon; the nucleating layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; the barrier layer is AlGaN;
the periodic p-GaN/InGaN layer 107 has multiple layers of In with low indium composition periodically distributed from bottom to topbGa1-bN layer and In of high indium compositionaGa1-aN layer, and adjacent In of low indium compositionbGa1-bN layer and In of high indium compositionaGa1-aAnd p-GaN layers are arranged between the N layers.
In the present example, In of the Low indium fractionbGa1-bN layers, wherein b is 0.06, the thickness is 10nm, and the number of layers is 2;
in the present example, In of the high indium compositionaGa1-aN layers, wherein a is 0.6, the thickness is 4nm, and the number of layers is 2;
in this example, the total thickness of all the p-GaN layers was 72nm, the number of the p-GaN layers was 4, Mg was doped into the p-GaN layers, and the hole concentration was 2E18 cm-3。
Example 2:
a p-GaN normally-off power device with a periodic gate structure comprises a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, an insertion layer 105 and a barrier layer 106 from bottom to top as shown in FIG. 1;
a source electrode and a drain electrode are disposed above the barrier layer 106, a periodic p-GaN/InGaN layer 107 formed on the barrier layer is disposed between the source electrode and the drain electrode, and a gate electrode is disposed on the periodic p-GaN/InGaN layer.
In this embodiment, the substrate is silicon; the nucleating layer is AlN; the buffer layer is AlGaN; the channel layer is GaN; the insertion layer is AlN; the barrier layer is AlGaN;
the periodic p-GaN/InGaN layer 107 has multiple layers of In with low indium composition periodically distributed from bottom to topbGa1-bN layer and In of high indium compositionaGa1-aN layer, and adjacent In of low indium compositionbGa1-bN layer and In of high indium compositionaGa1-ap-GaN layers are arranged between the N layers;
in the present example, In of the Low indium fractionbGa1-bN layers, wherein b is 0.06, the thickness is 5nm, and the number of layers is 4;
in the present example, In of the high indium compositionaGa1-aN layers, wherein a is 0.6, the thickness is 2nm, and the number of layers is 4;
in this example, the total thickness of all the p-GaN layers was 72nm, the number of the p-GaN layers was 8, Mg was doped into the p-GaN layers, and the hole concentration was 2E18 cm-3；
FIG. 2 is a simulated transfer curve corresponding to a control group, example 1 and example 2, wherein the control group has no InGaN layer, the total thickness of all p-GaN layers is consistent with that of all p-GaN layers in examples 1 and 2, and the concentration of Mg doped in p-GaN is also consistent; the InGaN composition in examples 1 and 2 were also correspondingly identical except for the thickness and period; it can be seen from fig. 2 that the threshold voltages of both example 1 and example 2 were positively shifted compared to the control group, and the threshold voltage of example 2 was larger relative to example 1. This indicates that the stepped polarization electric field between the p-GaN/InGaN layers 107 of varying indium composition effectively improves the ionization efficiency of Mg, thereby increasing the threshold voltage. And as the periodicity is increased, the interaction of the polarization electric field is stronger, and the threshold voltage is further improved.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features. Accordingly, it will be appreciated by those skilled in the art that changes, substitutions, modifications and the like can be made without departing from the spirit of the invention.

Claims (10)

1. A p-GaN normally-closed power device with a periodic gate structure is characterized by comprising a substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104), an insertion layer (105) and a barrier layer (106) from bottom to top;
a source electrode and a drain electrode are arranged above the barrier layer (106), a periodic p-GaN/InGaN layer (107) formed on the barrier layer is arranged between the source electrode and the drain electrode, and a grid electrode is arranged on the periodic p-GaN/InGaN layer.
2. The p-GaN normally-off power device with periodic gate structure as claimed In claim 1, wherein the periodic p-GaN/InGaN layer (107) has multiple layers of In with low indium composition periodically distributed from bottom to topbGa1-bN layer and In of high indium compositionaGa1-aN layer, and adjacent In of low indium compositionbGa1-bN layer and In of high indium compositionaGa1-aAnd p-GaN layers are arranged between the N layers.
3. A cycle according to claim 2The gate-structured p-GaN normally-closed power device is characterized in that Mg is doped in p-GaN of the p-GaN layer, and the hole concentration is 2E17-2E18 cm-3。
4. The p-GaN normally-off power device of periodic gate structure as claimed In claim 2, wherein the total thickness of the periodic p-GaN/InGaN layer (107) is 80-120nm, wherein the total thickness of all p-GaN layers is 60-90nm, and each layer is In with low indium compositionbGa1-bThe thickness of the N layer is 5-10nm, and each layer of In with high indium compositionaGa1-aThe thickness of the N layer is 0.5-5 nm.
5. The p-GaN normally-off power device with periodic gate structure of claim 2, wherein In with high indium compositionaGa1-aIn the N layer, 0.3<a<0.7, In of high indium compositionaGa1-aThe number of N layers is not less than 2.
6. The p-GaN normally-off power device with periodic gate structure as claimed In claim 2, wherein In with low indium contentbGa1-bIn the N layer, 0.05<b<0.3, In of Low indium compositionbGa1-bThe number of N layers is not less than 2.
7. The p-GaN normally-off power device of claim 2, wherein In is high In compositionaGa1-aN layer and In of low indium compositionbGa1-bThe number of N layers is the same.
8. A p-GaN normally-off power device of periodic gate structure according to claim 1, characterized in that the substrate (101) is silicon; the nucleation layer (102) is AlN.
9. The p-GaN normally-off power device with the periodic gate structure according to claim 1, wherein the buffer layer (103) is AlGaN; the channel layer (104) is GaN.
10. A p-GaN normally-off power device of periodic gate structure according to any of claims 1 to 9, characterized in that the insertion layer (105) is AlN; the barrier layer (106) is AlGaN.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023071028A1 (en) * 2021-10-28 2023-05-04 华南理工大学 P-gan normally-closed power device having periodic gate structure

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CN107393956A (en) * 2017-07-06 2017-11-24 中国科学院半导体研究所 Enhancement type high electron mobility transistor and preparation method comprising p-type superlattices
WO2020062221A1 (en) * 2018-09-30 2020-04-02 苏州晶湛半导体有限公司 Semiconductor structure and manufacturing method therefor
CN112510087A (en) * 2020-12-01 2021-03-16 晶能光电（江西）有限公司 P-type gate enhanced GaN-based HEMT device and preparation method thereof

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JP6189235B2 (en) * 2014-03-14 2017-08-30 株式会社東芝 Semiconductor device
JP6170007B2 (en) * 2014-04-10 2017-07-26 トヨタ自動車株式会社 Switching element
CN114122107B (en) * 2021-10-28 2023-07-18 华南理工大学 P-GaN normally-closed power device with periodic gate structure

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Publication number Priority date Publication date Assignee Title
CN107393956A (en) * 2017-07-06 2017-11-24 中国科学院半导体研究所 Enhancement type high electron mobility transistor and preparation method comprising p-type superlattices
WO2020062221A1 (en) * 2018-09-30 2020-04-02 苏州晶湛半导体有限公司 Semiconductor structure and manufacturing method therefor
CN112510087A (en) * 2020-12-01 2021-03-16 晶能光电（江西）有限公司 P-type gate enhanced GaN-based HEMT device and preparation method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023071028A1 (en) * 2021-10-28 2023-05-04 华南理工大学 P-gan normally-closed power device having periodic gate structure

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