CN114121684A - Semiconductor package and preparation method thereof - Google Patents
Semiconductor package and preparation method thereof Download PDFInfo
- Publication number
- CN114121684A CN114121684A CN202210078198.XA CN202210078198A CN114121684A CN 114121684 A CN114121684 A CN 114121684A CN 202210078198 A CN202210078198 A CN 202210078198A CN 114121684 A CN114121684 A CN 114121684A
- Authority
- CN
- China
- Prior art keywords
- component
- layer
- organic
- flexible
- capacitor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
Abstract
The invention relates to a semiconductor package and a preparation method thereof, and relates to the field of semiconductor packages. The first organic flexible layer is protected from being damaged in the subsequent process of stripping the first organic flexible layer by depositing an inorganic protective layer before forming the first organic flexible layer. And the ratio of the distance between the first tube cores to the side length of the first tube cores is set to be 5-20, so that the first organic flexible layer and the second organic flexible layer in the area between the adjacent first tube cores can be bent, the bending flexibility of the packaging structure is increased, the packaging structure with any size can be cut, and the subsequent bending and stacking of the packaging structures are facilitated.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a semiconductor package and a preparation method thereof.
Background
Conventional semiconductor packages include package forms such as DIP dual in-line package, BGA ball grid array package, QFP plastic square flat package, PFP plastic flat package, DSO double-sided lead small outline package, PGA pin grid array package, MCM multi-chip module, CSP chip size package, and the like. With the continuous development of integrated circuits toward microminiaturization, low power consumption, intelligence and high reliability, further improvement of the fabrication process of semiconductor packages and optimization of the specific structure of semiconductor packages are required to adapt to the development trend of integrated circuits, thereby facilitating the development of smart phones, computers, PADs and the like toward miniaturization and lightness.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies of the prior art and to providing a semiconductor package and a method for manufacturing the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a method of manufacturing a semiconductor package, the method comprising the steps of:
(1) providing a temporary packaging carrier substrate, arranging a temporary bonding layer on the temporary packaging carrier substrate, then depositing an inorganic protective layer on the temporary bonding layer, and then forming a first organic flexible layer on the inorganic protective layer.
(2) And spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution on the first organic flexible layer to form a flexible conductive circuit layer.
(3) And then installing a plurality of first tube cores on the flexible conductive circuit layer, wherein the first tube cores are arranged in a matrix, and the ratio of the distance between the adjacent first tube cores to the side length of the first tube cores is 5-20.
(4) And then forming a second organic flexible layer on the first organic flexible layer, wherein the second organic flexible layer wraps the plurality of first tube cores, and the first and second organic flexible layers in the area between the adjacent first tube cores can be bent.
(5) Then, a cutting process is performed to form a first, a second, a third and a fourth assembly.
(6) And then respectively forming a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element on the upper surfaces of the first assembly, the second assembly, the third assembly and the fourth assembly, wherein the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element respectively comprise a flexible lower electrode, an insulating medium layer and a flexible upper electrode which are arranged in a stacked mode.
(7) Providing a first package comprising a circuit substrate, a second die disposed on the circuit substrate, and an organic package completely encapsulating the second die and covering a portion of the circuit substrate.
(8) And then, a first component is attached to the side surface and the upper surface of the organic packaging body, and the flexible conducting circuit layer in the first component is electrically connected with the circuit substrate.
(9) Then, a second component is attached to the first component, and the flexible conductive circuit layer in the second component is electrically connected with the circuit substrate.
(10) Then, a third component is attached to the second component, and the flexible conductive circuit layer in the third component is electrically connected with the circuit substrate.
(11) A fourth component is then applied over the third component, and the flexible conductive trace layer in the fourth component is electrically connected to the circuit substrate.
In a more preferred embodiment, the material of the inorganic protective layer is one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, and the material of the first and second organic flexible layers includes one or more of polyimide, polycarbonate, polyethylene terephthalate, polyphenylene ether sulfone, thermoplastic polyurethane and polydimethylsiloxane.
In a more preferred embodiment, the size of the first module is smaller than the size of the second module, the size of the second module is smaller than the size of the third module, and the size of the third module is smaller than the size of the fourth module.
In a more preferred embodiment, in the step (6), first, second, third, and fourth cavities are formed on the upper surfaces of the first, second, third, and fourth components, respectively, and the first, second, third, and fourth capacitive elements are embedded in the corresponding first, second, third, and fourth cavities, respectively.
In a more preferred embodiment, in the step (7), the second die is electrically connected to the circuit substrate through a wire bonding process or a flip-chip process, and the organic package includes an epoxy resin.
In a more preferred embodiment, the bottom surfaces of the two end portions of the first component are provided with protrusions, the two side surfaces of the organic package are provided with recesses, and the protrusions are embedded into the recesses in the process of attaching the first component to the side surfaces and the upper surface of the organic package.
In a more preferred embodiment, the present invention further provides a semiconductor package formed by the above manufacturing method.
Compared with the prior art, the semiconductor package and the preparation method thereof have the following beneficial effects:
the first organic flexible layer is protected from being damaged in the subsequent process of stripping the first organic flexible layer by depositing an inorganic protective layer before forming the first organic flexible layer. And the ratio of the distance between the first tube cores to the side length of the first tube cores is set to be 5-20, so that the first organic flexible layer and the second organic flexible layer in the area between the adjacent first tube cores can be bent, the bending flexibility of the packaging structure is increased, the packaging structure with any size can be cut, and the subsequent bending and stacking of the packaging structures are facilitated.
The flexible conductive circuit layer is formed by spin-coating the metal nanowire suspension liquid and the black phosphorus nanosheet solution, the existence of the black phosphorus nanosheet in the flexible conductive circuit layer can increase the joint tightness between the central line and the line of the metal nanowire layer, namely the black phosphorus nanosheet can tightly weld the joint of the metal nanowire and the metal nanowire together, so that the conductivity of the flexible conductive circuit layer can be improved, the flexible lower electrode and the flexible upper electrode of each capacitor element are formed by utilizing the spin-coating metal nanowire suspension liquid and the black phosphorus nanosheet solution, so that the flexible conductive circuit layer has excellent bending performance, and the prepared packaging structure cannot break the conductive circuit layer and the electrodes in the subsequent folding/bending process.
In the subsequent packaging process, the size of the first assembly is smaller than that of the second assembly, the size of the second assembly is smaller than that of the third assembly, the size of the third assembly is smaller than that of the fourth assembly, and the first assembly, the second assembly, the third assembly and the fourth assembly are sequentially stacked on the first packaging body, so that the integration level of semiconductor packaging is effectively improved.
Drawings
Fig. 1 to 8 are schematic structural views of steps in a method for manufacturing a semiconductor package according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a preparation method of a semiconductor package, which comprises the following steps:
(1) providing a temporary packaging carrier substrate, arranging a temporary bonding layer on the temporary packaging carrier substrate, then depositing an inorganic protective layer on the temporary bonding layer, and then forming a first organic flexible layer on the inorganic protective layer.
(2) And spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution on the first organic flexible layer to form a flexible conductive circuit layer.
(3) And then installing a plurality of first tube cores on the flexible conductive circuit layer, wherein the first tube cores are arranged in a matrix, and the ratio of the distance between the adjacent first tube cores to the side length of the first tube cores is 5-20.
(4) And then forming a second organic flexible layer on the first organic flexible layer, wherein the second organic flexible layer wraps the plurality of first tube cores, and the first and second organic flexible layers in the area between the adjacent first tube cores can be bent.
(5) Then, a cutting process is performed to form a first, a second, a third and a fourth assembly.
(6) And then respectively forming a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element on the upper surfaces of the first assembly, the second assembly, the third assembly and the fourth assembly, wherein the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element respectively comprise a flexible lower electrode, an insulating medium layer and a flexible upper electrode which are arranged in a stacked mode.
(7) Providing a first package comprising a circuit substrate, a second die disposed on the circuit substrate, and an organic package completely encapsulating the second die and covering a portion of the circuit substrate.
(8) And then, a first component is attached to the side surface and the upper surface of the organic packaging body, and the flexible conducting circuit layer in the first component is electrically connected with the circuit substrate.
(9) Then, a second component is attached to the first component, and the flexible conductive circuit layer in the second component is electrically connected with the circuit substrate.
(10) Then, a third component is attached to the second component, and the flexible conductive circuit layer in the third component is electrically connected with the circuit substrate.
(11) A fourth component is then applied over the third component, and the flexible conductive trace layer in the fourth component is electrically connected to the circuit substrate.
Further, the material of the inorganic protective layer is one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, and the material of the first and second organic flexible layers includes one or more of polyimide, polycarbonate, polyethylene terephthalate, polyphenylene ether sulfone, thermoplastic polyurethane and polydimethylsiloxane.
Further, the size of the first component is smaller than that of the second component, the size of the second component is smaller than that of the third component, and the size of the third component is smaller than that of the fourth component.
Further, in the step (6), first, second, third, and fourth cavities are formed on the upper surfaces of the first, second, third, and fourth components, respectively, and the first, second, third, and fourth capacitance elements are embedded into the corresponding first, second, third, and fourth cavities, respectively.
Further, in the step (7), the second die is electrically connected to the circuit substrate through a wire bonding process or a flip chip process, and the organic package includes an epoxy resin.
Furthermore, the bottom surfaces of the two end portions of the first component are provided with protrusions, the two side surfaces of the organic packaging body are provided with recesses, and the protrusions are embedded into the recesses in the process of applying the first component to the side surfaces and the upper surface of the organic packaging body.
The invention also provides a semiconductor package formed by adopting the preparation method.
As shown in fig. 1 to 8, the present embodiment provides a method for manufacturing a semiconductor package, including the steps of:
as shown in fig. 1, in step (1), a temporary encapsulation carrier substrate 100 is provided, a temporary bonding layer 101 is disposed on the temporary encapsulation carrier substrate, an inorganic protective layer 102 is then deposited on the temporary bonding layer 101, and a first organic flexible layer 103 is then formed on the inorganic protective layer 102.
In a specific embodiment, the temporary package carrier substrate 100 may be a suitable rigid substrate of semiconductor, stainless steel, ceramic, etc.
In a specific embodiment, the temporary bonding layer 101 may be disposed on the temporary package carrier substrate 100 through a coating process, and the temporary bonding layer 101 loses its adhesiveness under light or heat, thereby facilitating its peeling.
In a specific embodiment, the material of the inorganic protection layer 102 is one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide, the inorganic protection layer 102 is formed by PECVD or ALD method, and the thickness of the inorganic protection layer 102 is 10-50 nm, and the inorganic protection layer 102 is disposed to prevent the first organic flexible layer 103 from being damaged in the subsequent process of peeling off the temporary package carrier substrate 100.
In a specific embodiment, the material of the first organic flexible layer 103 includes one or more of polyimide, polycarbonate, polyethylene terephthalate, polyethersulfone, thermoplastic polyurethane, and polydimethylsiloxane. More specifically, the first organic flexible layer 103 is formed by a suitable process such as coating, molding, injection molding, slit coating, spin coating, or the like.
As shown in fig. 2, in step (2), a metal nanowire suspension liquid and a black phosphorus nanosheet solution are spin-coated on the first organic flexible layer 103 to form a flexible conductive circuit layer 201.
In a specific embodiment, the presence of black phosphorus nanoplates in the flexible conductive trace layer 201 can increase the line-to-line bond tightness of the metal nanowire layer.
In a specific embodiment, the flexible conductive circuit layer 201 is formed by alternately spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution for 5-20 times, and the presence of the black phosphorus nanosheet can increase the joint tightness between wires in the metal nanowire layer, wherein the metal nanowire is a gold nanowire, a silver nanowire or a copper nanowire.
In more specific embodiments, the concentrations of the spin-coated metal nanowire suspension liquid and the spin-coated black phosphorus nanoplate solution are 10-30mg/ml and 30-50mg/ml, respectively, more specifically, the spin-coated metal nanowire suspension liquid may specifically be 10, 13, 16, 20, 23, 26, or 28mg/ml and the like, and the spin-coated black phosphorus nanoplate solution may specifically be 32, 35, 38, 40, 42, 45, 48, or 50mg/ml and the like, as appropriate. Further, according to the concentration of the spin-coated metal nanowire suspension liquid and the spin-coated black phosphorus nanosheet solution, the number of alternation times is selected to be 5, 8, 10, 12, 15 or 20, and then the flexible conductive circuit layer 201 with a proper thickness is obtained.
As shown in fig. 3, in step (3), a plurality of first dies 202 are then mounted on the flexible conductive circuit layer 201, the plurality of first dies 202 are arranged in a matrix, and a ratio of a distance between adjacent first dies 202 to a side length of the first dies 202 is 5-20.
In a specific embodiment, a plurality of the first dies 202 are electrically connected to the flexible conductive circuit layer 201 through a flip-chip process, so that the thickness of a subsequently formed second organic flexible layer can be reduced.
In a specific embodiment, the ratio of the spacing between adjacent first dies 202 to the side length of the first dies 202 is preferably 10 to 15.
As shown in fig. 4, in step (4), a second organic flexible layer 301 is then formed on the first organic flexible layer 103, the second organic flexible layer 301 covers the plurality of first dies 202, and the first and second organic flexible layers in the region between the adjacent first dies 202 can be bent.
In a specific embodiment, the material of the second organic flexible layer 301 includes one or more of polyimide, polycarbonate, polyethylene terephthalate, polyethersulfone, thermoplastic polyurethane, and polydimethylsiloxane. More specifically, the second organic flexible layer 301 is formed by a suitable process such as coating, molding, injection molding, slit coating, spin coating, or the like.
In step (5), a dicing process is then performed to form a first component 401, a second component 402, a third component 403, and a fourth component 404, while fig. 5 shows only the first component 401.
In a specific embodiment, the size of the first component 401 is smaller than the size of the second component 402, the size of the second component 402 is smaller than the size of the third component 403, and the size of the third component 403 is smaller than the size of the fourth component 404.
In step (6), a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element are respectively formed on the upper surfaces of the first component 401, the second component 401, the third component 401 and the fourth component 404, the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element respectively include a flexible lower electrode, an insulating medium layer and a flexible upper electrode which are stacked, and the specific forming process of the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element is as follows: and forming a flexible lower electrode on the upper surface of each component, further forming an insulating medium layer on the flexible lower electrode, and then forming a flexible upper electrode on the insulating medium layer, wherein the flexible upper electrode and the flexible lower electrode are both formed by spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution.
As shown in fig. 6, fig. 6 shows that only the first capacitive element 501 is formed on the upper surface of the first component 401.
In a specific embodiment, first, second, third, and fourth cavities are formed on the upper surfaces of the first, second, third, and fourth components 401 and 404, respectively, so as to embed the first, second, third, and fourth capacitive elements into the corresponding first, second, third, and fourth cavities, respectively.
In a specific embodiment, the specific preparation process of the flexible lower electrode and the flexible upper electrode is as follows: the method is formed by alternately spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution for 5-20 times, wherein the concentrations of the spin-coated metal nanowire suspension liquid and the spin-coated black phosphorus nanosheet solution are 10-30mg/ml and 30-50mg/ml respectively, more specifically, the spin-coated metal nanowire suspension liquid can be 10, 13, 16, 20, 23, 26 or 28mg/ml and the like, and the spin-coated black phosphorus nanosheet solution can be 32, 35, 38, 40, 42, 45, 48 or 50mg/ml and the like. The number of alternation is further selected to be 5, 8, 10, 12, 15 or 20 times according to the concentration of the spin-coated metal nanowire suspension liquid and the spin-coated black phosphorus nanosheet solution.
In a specific embodiment, the flexible lower electrode and the flexible upper electrode of each capacitive element can be electrically connected to the flexible conductive trace layer 201 of each component by disposing the conductive members in the first and second organic flexible layers of each component.
As shown in fig. 7, in step (7), a first package 600 is provided, where the first package 600 includes a circuit substrate 601, a second die 602 disposed on the circuit substrate 601, and an organic package 603, and the organic package 603 completely wraps the second die 602 and covers a portion of the circuit substrate 601.
Wherein, in the step (7), the second die 602 is electrically connected to the circuit substrate 601 through a wire bonding process or a flip chip process, and the organic package 603 includes an epoxy resin.
As shown in fig. 8, in the step (8), a first component 401 is then applied to the side and upper surfaces of the organic package 603, and the flexible conductive trace layer 201 in the first component 401 is electrically connected to the circuit substrate 601.
In a more preferred embodiment, the bottom surfaces of the two end portions of the first component 401 are provided with protrusions (not shown), and the two side surfaces of the organic package 603 are provided with recesses (not shown), so that the protrusions are embedded in the recesses during the process of applying the first component 401 to the side surfaces and the upper surface of the organic package 603, thereby providing the bonding stability of the first component 401.
As shown in fig. 8, in the step (9), a second component 402 is then applied on the first component 401, and the flexible conductive circuit layer 201 in the second component 402 is electrically connected to the circuit substrate; in the step (10), a third component 403 is then applied on the second component 402, and the flexible conductive circuit layer 201 in the third component 403 is electrically connected with the circuit substrate; a fourth component 404 is then applied over the third component 403 and the flexible electrically conductive line layer in the fourth component 404 is electrically connected to the circuit substrate.
As shown in fig. 8, the present invention also provides a semiconductor package formed by the above-mentioned manufacturing method.
Compared with the prior art, the semiconductor package and the preparation method thereof have the following beneficial effects:
the first organic flexible layer is protected from being damaged in the subsequent process of stripping the first organic flexible layer by depositing an inorganic protective layer before forming the first organic flexible layer. And the ratio of the distance between the first tube cores to the side length of the first tube cores is set to be 5-20, so that the first organic flexible layer and the second organic flexible layer in the area between the adjacent first tube cores can be bent, the bending flexibility of the packaging structure is increased, the packaging structure with any size can be cut, and the subsequent bending and stacking of the packaging structures are facilitated.
The flexible conductive circuit layer is formed by spin-coating the metal nanowire suspension liquid and the black phosphorus nanosheet solution, the existence of the black phosphorus nanosheet in the flexible conductive circuit layer can increase the joint tightness between the central line and the line of the metal nanowire layer, namely the black phosphorus nanosheet can tightly weld the joint of the metal nanowire and the metal nanowire together, so that the conductivity of the flexible conductive circuit layer can be improved, the flexible lower electrode and the flexible upper electrode of each capacitor element are formed by utilizing the spin-coating metal nanowire suspension liquid and the black phosphorus nanosheet solution, so that the flexible conductive circuit layer has excellent bending performance, and the prepared packaging structure cannot break the conductive circuit layer and the electrodes in the subsequent folding/bending process.
In the subsequent packaging process, the size of the first assembly is smaller than that of the second assembly, the size of the second assembly is smaller than that of the third assembly, the size of the third assembly is smaller than that of the fourth assembly, and the first assembly, the second assembly, the third assembly and the fourth assembly are sequentially stacked on the first packaging body, so that the integration level of semiconductor packaging is effectively improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method for manufacturing a semiconductor package, comprising: the preparation method of the semiconductor package comprises the following steps:
(1) providing a temporary packaging carrier substrate, arranging a temporary bonding layer on the temporary packaging carrier substrate, then depositing an inorganic protective layer on the temporary bonding layer, and then forming a first organic flexible layer on the inorganic protective layer;
(2) spin-coating a metal nanowire suspension liquid and a black phosphorus nanosheet solution on the first organic flexible layer to form a flexible conductive circuit layer;
(3) then, mounting a plurality of first tube cores on the flexible conducting circuit layer, wherein the first tube cores are arranged in a matrix manner, and the ratio of the distance between the adjacent first tube cores to the side length of the first tube cores is 5-20;
(4) then forming a second organic flexible layer on the first organic flexible layer, wherein the second organic flexible layer wraps the plurality of first tube cores, and the first organic flexible layer and the second organic flexible layer in the area between the adjacent first tube cores can be bent;
(5) then, cutting to form a first component, a second component, a third component and a fourth component;
(6) then respectively forming a first capacitor element, a second capacitor element, a third capacitor element and a fourth capacitor element on the upper surfaces of the first assembly, the second assembly, the third assembly and the fourth assembly, wherein the first capacitor element, the second capacitor element, the third capacitor element and the fourth capacitor element respectively comprise a flexible lower electrode, an insulating medium layer and a flexible upper electrode which are arranged in a stacked mode;
(7) providing a first package comprising a circuit substrate, a second die disposed on the circuit substrate, and an organic package completely encapsulating the second die and covering a portion of the circuit substrate;
(8) then, a first component is attached to the side face and the upper surface of the organic packaging body, and the flexible conducting circuit layer in the first component is electrically connected with the circuit substrate;
(9) then, a second component is attached to the first component, and the flexible conducting circuit layer in the second component is electrically connected with the circuit substrate;
(10) then a third component is pasted on the second component, and the flexible conducting circuit layer in the third component is electrically connected with the circuit substrate;
(11) a fourth component is then applied over the third component, and the flexible conductive trace layer in the fourth component is electrically connected to the circuit substrate.
2. The method for manufacturing a semiconductor package according to claim 1, wherein: the material of the inorganic protective layer is one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide, and the material of the first organic flexible layer and the second organic flexible layer comprises one or more of polyimide, polycarbonate, polyethylene terephthalate, polyphenylene ether sulfone, thermoplastic polyurethane and polydimethylsiloxane.
3. The method for manufacturing a semiconductor package according to claim 1, wherein: the size of the first component is smaller than that of the second component, the size of the second component is smaller than that of the third component, and the size of the third component is smaller than that of the fourth component.
4. The method for manufacturing a semiconductor package according to claim 1, wherein: in the step (6), first, second, third, and fourth cavities are formed on the upper surfaces of the first, second, third, and fourth components, respectively, and the first, second, third, and fourth capacitive elements are embedded in the corresponding first, second, third, and fourth cavities, respectively.
5. The method for manufacturing a semiconductor package according to claim 1, wherein: in the step (7), the second die is electrically connected to the circuit substrate through a wire bonding process or a flip-chip process, and the organic package includes an epoxy resin.
6. The method for manufacturing a semiconductor package according to claim 1, wherein: the bottom surfaces of the two end parts of the first assembly are provided with protrusions, the two side surfaces of the organic packaging body are provided with recesses, and the protrusions are embedded into the recesses in the process of attaching the first assembly to the side surfaces and the upper surface of the organic packaging body.
7. A semiconductor package formed by the manufacturing method according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210078198.XA CN114121684B (en) | 2022-01-24 | 2022-01-24 | Semiconductor package and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210078198.XA CN114121684B (en) | 2022-01-24 | 2022-01-24 | Semiconductor package and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114121684A true CN114121684A (en) | 2022-03-01 |
| CN114121684B CN114121684B (en) | 2022-04-12 |
Family
ID=80361060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210078198.XA Active CN114121684B (en) | 2022-01-24 | 2022-01-24 | Semiconductor package and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114121684B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120247819A1 (en) * | 2011-03-31 | 2012-10-04 | Tdk Corporation | Electronic component-embeded board and method for manufacturing the same |
| CN109712961A (en) * | 2017-10-25 | 2019-05-03 | 上海新微技术研发中心有限公司 | Three-dimensional integrated circuit and method of manufacturing the same |
| CN110660774A (en) * | 2018-06-29 | 2020-01-07 | 力成科技股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN110690055A (en) * | 2019-09-05 | 2020-01-14 | 上海电力大学 | Flexible electrode material based on black phosphorus/molybdenum trioxide and preparation and application thereof |
| KR20200062964A (en) * | 2018-11-27 | 2020-06-04 | 주식회사 에스모머티리얼즈 | Epoxy resin composition for photosemiconductor element molding and method for preparation of the same |
| US20200365567A1 (en) * | 2018-02-01 | 2020-11-19 | Lg Electronics Inc. | Display device using semiconductor light-emitting element and manufacturing method therefor |
| CN112366138A (en) * | 2020-11-11 | 2021-02-12 | 济南南知信息科技有限公司 | Storage chip packaging structure and preparation method thereof |
-
2022
- 2022-01-24 CN CN202210078198.XA patent/CN114121684B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120247819A1 (en) * | 2011-03-31 | 2012-10-04 | Tdk Corporation | Electronic component-embeded board and method for manufacturing the same |
| CN109712961A (en) * | 2017-10-25 | 2019-05-03 | 上海新微技术研发中心有限公司 | Three-dimensional integrated circuit and method of manufacturing the same |
| US20200365567A1 (en) * | 2018-02-01 | 2020-11-19 | Lg Electronics Inc. | Display device using semiconductor light-emitting element and manufacturing method therefor |
| CN110660774A (en) * | 2018-06-29 | 2020-01-07 | 力成科技股份有限公司 | Semiconductor package and method of manufacturing the same |
| KR20200062964A (en) * | 2018-11-27 | 2020-06-04 | 주식회사 에스모머티리얼즈 | Epoxy resin composition for photosemiconductor element molding and method for preparation of the same |
| CN110690055A (en) * | 2019-09-05 | 2020-01-14 | 上海电力大学 | Flexible electrode material based on black phosphorus/molybdenum trioxide and preparation and application thereof |
| CN112366138A (en) * | 2020-11-11 | 2021-02-12 | 济南南知信息科技有限公司 | Storage chip packaging structure and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114121684B (en) | 2022-04-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100401020B1 (en) | Stacking structure of semiconductor chip and semiconductor package using it | |
| TWI429050B (en) | Stack die packages | |
| TWI469309B (en) | Integrated circuit package system | |
| US6472749B1 (en) | Semiconductor device having a shortened wiring length to reduce the size of a chip | |
| US8129226B2 (en) | Power lead-on-chip ball grid array package | |
| US20100203677A1 (en) | Method for fabricating semiconductor packages with discrete components | |
| US6916682B2 (en) | Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing | |
| CN109755202B (en) | Electronic package and manufacturing method thereof | |
| CN100573858C (en) | Chip packing-body | |
| CN111933591B (en) | Fan-out type electromagnetic shielding packaging structure and packaging method | |
| US9812420B2 (en) | Die packaging with fully or partially fused dielectric leads | |
| CN114899155A (en) | Multi-type multi-quantity chip three-dimensional stacking integrated packaging structure and manufacturing method thereof | |
| CN112054005B (en) | Electronic package and manufacturing method thereof | |
| CN114121684B (en) | Semiconductor package and preparation method thereof | |
| CN207852897U (en) | Fan-out-type antenna packages structure | |
| CN107622981B (en) | Electronic package and manufacturing method thereof | |
| CN210692485U (en) | Antenna packaging structure | |
| CN210489610U (en) | Fan-shaped multi-chip packaging structure | |
| US8410598B2 (en) | Semiconductor package and method of manufacturing the same | |
| CN105489542A (en) | Chip packaging method and chip packaging structure | |
| CN112713098A (en) | Antenna packaging structure and packaging method | |
| TWI390701B (en) | Semiconductor package exempt with substrate and contact pins and its fabricating process | |
| CN210692484U (en) | Antenna packaging structure | |
| CN210692529U (en) | Antenna packaging structure | |
| CN111524467B (en) | Display device and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |