CN112366138A - Storage chip packaging structure and preparation method thereof - Google Patents

Storage chip packaging structure and preparation method thereof Download PDF

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CN112366138A
CN112366138A CN202011251334.8A CN202011251334A CN112366138A CN 112366138 A CN112366138 A CN 112366138A CN 202011251334 A CN202011251334 A CN 202011251334A CN 112366138 A CN112366138 A CN 112366138A
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memory chip
layer
graphene oxide
spin
aqueous solution
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CN112366138B (en
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秦玲
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Hunan Zhongke Storage Technology Co ltd
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Ji Nannan Knows Information Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a removable or sacrificial coating

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

The invention relates to a preparation method of a memory chip packaging structure, which comprises the following steps: arranging a first packaging layer, a first circuit layer, a first memory chip, a control chip and a second memory chip on a first carrier plate; then arranging a second packaging layer, a second circuit layer, a third storage chip, a cache chip and a fourth storage chip on the first packaging layer; then, arranging a third packaging layer, a third circuit layer, a fifth memory chip and a sixth memory chip on the second packaging layer; then, a fourth packaging layer, a fourth circuit layer, a seventh memory chip and an eighth memory chip are arranged on the third packaging layer; and then removing the first carrier plate, forming a plurality of first grooves exposing the back surface of each memory chip in each packaging layer, forming a plurality of second grooves exposing the first circuit layer in the first packaging layer, and forming heat dissipation columns and conductive columns in the first grooves and the second grooves respectively.

Description

Storage chip packaging structure and preparation method thereof
Technical Field
The invention relates to the field of semiconductor storage element packaging, in particular to a storage chip packaging structure and a preparation method thereof.
Background
With the continuous development of science and technology, the demand of people on consumer electronics is also higher and higher, a memory chip in the electronics is a key core component, in a traditional memory packaging component, due to the limitation of the self memory capacity of a single chip, a plurality of layers of chips need to be stacked in the memory packaging component to meet the storage requirement of higher capacity, and 8 layers, 16 layers and 32 layers are very common. Because the existing memory packaging component needs multiple layers of chips for stack packaging, and in the existing packaging process, the number of stacked layers is increased, the process risk is also obviously increased, and the problems of splintering, inclination or position deviation and the like are easy to occur. Therefore, how to improve the existing process technology can improve the integration of the package structure and ensure the yield of the memory package components.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art and to provide a memory chip package structure and a method for manufacturing the same.
In order to achieve the above object, the present invention provides a method for manufacturing a memory chip package structure, which comprises the following steps:
(1) providing a first carrier plate, arranging a first packaging layer on the first carrier plate, spin-coating PEDOT on the first packaging layer, wherein the first packaging layer is formed by PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution, and then arranging a first storage chip, a control chip and a second storage chip on the first packaging layer at intervals, so that the first storage chip, the control chip and the second storage chip are electrically connected to the first circuit layer;
(2) then, a second packaging layer is arranged on the first packaging layer, the second packaging layer covers the first and second memory chips and the control chip, then a plurality of first through holes are formed in the second packaging layer, the first through holes expose the first circuit layer, then conductive materials are deposited in the first through holes to form first conductive through holes, then PEDOT: PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the second packaging layer to form the second circuit layer, the second circuit layer is electrically connected with the first conductive through holes, and then a third memory chip, a cache chip and a fourth memory chip are arranged on the second packaging layer at intervals, wherein the cache chip is formed right above the control chip, the third memory chip is arranged above the first memory chip, and the third memory chip is arranged relative to the first memory chip and towards the first memory chip The middle of the board is offset by a distance, the fourth memory chip is arranged above the second memory chip, and the fourth memory chip is offset by a distance towards the middle of the first carrier board relative to the second memory chip;
(3) then, a third encapsulation layer is disposed on the second encapsulation layer, the third encapsulation layer covers the third and fourth memory chips and the cache chip, then a plurality of second through holes are formed in the third encapsulation layer, the plurality of second through holes expose the second circuit layer, then a conductive material is deposited in the second through holes to form second conductive through holes, then PEDOT PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the third encapsulation layer to form the third circuit layer, the third circuit layer is electrically connected with the second conductive through holes, then a fifth memory chip and a sixth memory chip are disposed on the third encapsulation layer at intervals, wherein the fifth memory chip is disposed above the third memory chip and the fifth memory chip is offset to the middle of the first carrier plate relative to the third memory chip, the sixth memory chip is arranged above the fourth memory chip and is offset to the middle of the first carrier plate by a distance relative to the fourth memory chip;
(4) then, a fourth packaging layer is arranged on the third packaging layer, the fourth packaging layer covers the fifth and sixth memory chips, then a plurality of third through holes are formed in the fourth packaging layer, the third through holes expose the third circuit layer, then conductive materials are deposited in the third through holes to form third conductive through holes, then PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the fourth packaging layer to form the fourth circuit layer, the fourth circuit layer is electrically connected with the third conductive through holes, then a seventh memory chip and an eighth memory chip are arranged on the fourth packaging layer at intervals, wherein the seventh memory chip is arranged above the fifth memory chip, and the seventh memory chip is offset to the middle of the first carrier plate by a distance relative to the fifth memory chip, the eighth memory chip is arranged above the sixth memory chip, the eighth memory chip is offset to the middle of the first carrier plate by a distance relative to the sixth memory chip, and then a fifth packaging layer is arranged on the fourth packaging layer;
(5) then, the first carrier is removed, a plurality of first grooves exposing the back surfaces of the first to eighth memory chips are formed in the second, third, fourth and fifth packaging layers, a plurality of second grooves exposing the first circuit layer are formed in the first packaging layer, a plurality of heat dissipation columns are formed in the first grooves, and a plurality of conductive columns are formed in the second grooves.
Preferably, in the step (1), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 20-30mg/ml, the average diameter of the silver nanowires is 10-30 nm, the average length of the silver nanowires is 5-10 microns, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 3-5mg/ml, and the diameter of the graphene oxide is 10-20 microns.
Preferably, in the step (2), the concentration of PEDOT: PSS in the spin-coated aqueous solution of PEDOT: PSS is 20-50mg/ml, the concentration of silver nanowires in the suspension of the spin-coated silver nanowires is 30-40mg/ml, the average diameter of the silver nanowires is 20-50 nm, the average length of the silver nanowires is 9-16 microns, the concentration of graphene oxide in the aqueous solution of the spin-coated graphene oxide is 2-4mg/ml, the diameter of the graphene oxide is 15-30 microns, the average diameter and the average length of the silver nanowires in the step (2) are both larger than the average diameter and the average length of the silver nanowires in the step (1), and the diameter of the graphene oxide in the step (2) is larger than the diameter of the graphene oxide in the step (1).
Preferably, in the step (3), the concentration of PEDOT: PSS in the spin-coated aqueous solution of PEDOT: PSS is 20-50mg/ml, the concentration of silver nanowires in the suspension of the spin-coated silver nanowires is 25-35mg/ml, the average diameter of the silver nanowires is 30-60 nm, the average length of the silver nanowires is 15-25 microns, the concentration of graphene oxide in the aqueous solution of the spin-coated graphene oxide is 1-3mg/ml, the diameter of the graphene oxide is 20-40 microns, the average diameter and the average length of the silver nanowires in the step (3) are both larger than the average diameter and the average length of the silver nanowires in the step (2), and the diameter of the graphene oxide in the step (3) is larger than the diameter of the graphene oxide in the step (2).
Preferably, in the step (4), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 15-25mg/ml, the average diameter of the silver nanowires is 10-30 nanometers, the average length of the silver nanowires is 5-10 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 4-5mg/ml, and the diameter of the graphene oxide is 10-20 micrometers.
Preferably, in the step (5), the first groove and the second groove are both formed by wet etching or dry etching, the material of the heat dissipation pillar and the conductive pillar is one or more of copper, aluminum, silver, titanium, nickel, gold and palladium, and the heat dissipation pillar and the conductive pillar are formed by one or more of electroplating, chemical plating, evaporation, magnetron sputtering, electron beam evaporation and chemical vapor deposition.
The invention also provides a memory chip packaging structure which is prepared by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the preparation process of the memory chip packaging structure, PEDOT, PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the packaging layer to form a circuit layer, although silver nanowires have high conductivity, pure silver nanowire grids have the defects of large surface roughness, poor adhesion, large resistance at nodes between the silver nanowires in mutual contact and the like, so that in the circuit layer, an organic conducting layer is formed by using PEDOT and PSS with excellent film forming performance, an organic conducting layer is further formed on the organic conducting layer, a graphene oxide layer is then formed on the silver nanowire grids, and the existence of the graphene oxide layer can effectively enable the silver nanowires in the silver nanowire grids in mutual contact to be more tightly jointed, so that the circuit layer with excellent conductivity and good stability is further formed, and meanwhile, conductive materials are deposited in the through holes to form conductive through holes so as to form the plane conductive through holes. By optimizing the packaging structure of the memory chip, the integration level and the functionality of the packaging structure are effectively improved.
Drawings
Fig. 1-5 are schematic structural diagrams of various manufacturing processes of a memory chip package structure according to an embodiment of the invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, various examples of the disclosure may use repeated reference characters and/or wording. The repeated symbols or words are for purposes of simplicity and clarity, and
and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 5, the present embodiment provides a memory chip package structure and a method for manufacturing the same.
In a specific embodiment, the method for manufacturing a memory chip package structure provided by the invention comprises the following steps: as shown in fig. 1, a step (1) is firstly performed, a first carrier 11 is provided, a first package layer 12 is disposed on the first carrier 11, a PEDOT: PSS aqueous solution, a silver nanowire suspension and a graphene oxide aqueous solution are spin-coated on the first package layer 12 to form the first circuit layer 13, and then a first memory chip 141, a control chip 142 and a second memory chip 143 are disposed on the first package layer 13 at intervals, such that the first memory chip 141, the control chip 142 and the second memory chip 143 are all electrically connected to the first circuit layer 13.
In the step (1), the concentration of PEDOT and PSS in the spin-coated PEDOT and PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 20-30mg/ml, the average diameter of the silver nanowires is 10-30 nanometers, the average length of the silver nanowires is 5-10 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 3-5mg/ml, and the diameter of the graphene oxide is 10-20 micrometers.
In a specific embodiment, a first carrier 11 is first provided, where the first carrier 11 may be one of a stainless steel carrier, a copper carrier, an aluminum carrier, a monocrystalline silicon carrier, and a polycrystalline silicon carrier, and then a resin material is disposed on the first carrier 11 to form a first encapsulation layer 12, where the first encapsulation layer 12 may be an epoxy encapsulation layer.
In a specific embodiment, the specific process of spin-coating PEDOT, PSS aqueous solution, silver nanowire suspension, and graphene oxide aqueous solution on the first encapsulation layer 12 to form the first circuit layer 13 is as follows: arranging a line pattern mask on the first packaging layer 12, spin-coating PEDOT, namely a PSS aqueous solution on the first packaging layer 12, wherein the concentration of the PST in the spin-coated PEDOT, namely the PSS aqueous solution is preferably 25mg/ml, 30mg/ml, 35mg/ml, 40mg/ml or 45mg/ml, the rotation speed of the spin-coating is 3000 and 4000 revolutions/minute, specifically 3200 revolutions/minute, 3400 revolutions/minute, 3600 revolutions/minute or 3800 revolutions/minute, and then carrying out heat treatment at 125-140 ℃ for 20-30 minutes to form a PEDOT, namely a PSS layer; and then spin-coating a silver nanowire suspension, wherein the concentration of the silver nanowire in the spin-coated silver nanowire suspension is 23mg/ml, 25mg/ml or 28mg/ml, the average diameter of the silver nanowire is 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, the average length of the silver nanowire is 5 microns, 6 microns, 7 microns, 8 microns, 9 microns or 10 microns, the spin-coating rotation speed is 3000 revolutions per minute or 5000 revolutions per minute, specifically 3500 revolutions per minute, 4000 revolutions per minute, 4500 revolutions per minute or 5000 revolutions per minute, so as to form a silver nanowire layer on the PEDOT/PSS layer, and then spin-coating a graphene oxide aqueous solution, wherein the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 3.5mg/ml, 4mg/ml, 4.5mg/ml or 5mg/ml, and the diameter of the graphene oxide is 12 microns, 14 microns, 16 microns or 18 microns, and the spin coating speed is 2000-3000 rpm, specifically 2200 rpm, 2400 rpm, 2600 rpm or 2800 rpm, to form a graphene oxide layer on the silver nanowire layer, and then repeating the formation of the PEDOT-PSS layer, the silver nanowire layer and the graphene oxide layer for multiple times to obtain the first wiring layer 13 with a suitable thickness, wherein the first wiring layer 13 has excellent stability and conductivity.
In a specific embodiment, a first memory chip 141, a control chip 142 and a second memory chip 143 are disposed at intervals on the first packaging layer 12, so that the conductive pads of the first memory chip 141, the control chip 142 and the second memory chip 143 are electrically connected to the first circuit layer 13 through a conductive adhesive.
As shown in fig. 2, step (2) is performed, then a second packaging layer 15 is disposed on the first packaging layer 12, the second packaging layer 15 covers the first and second memory chips and the control chip 141-, the third memory chip 181 is disposed above the first memory chip 141 and the third memory chip 181 is offset to the middle of the first carrier 11 by a distance with respect to the first memory chip 141, and the fourth memory chip 183 is disposed above the second memory chip 143 and the fourth memory chip 183 is offset to the middle of the first carrier 11 by a distance with respect to the second memory chip 143.
In the step (2), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 30-40mg/ml, the average diameter of the silver nanowires is 20-50 nm, the average length of the silver nanowires is 9-16 microns, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 2-4mg/ml, the diameter of the graphene oxide is 15-30 microns, the average diameter and the average length of the silver nanowires in the step (2) are both larger than the average diameter and the average length of the silver nanowires in the step (1), and the diameter of the graphene oxide in the step (2) is larger than the diameter of the graphene oxide in the step (1).
In a specific embodiment, a resin material is disposed on the first encapsulation layer 12 to form a second encapsulation layer 15, and the second encapsulation layer 15 may be an epoxy encapsulation layer.
In a specific embodiment, a plurality of first through holes 151 are then formed in the second encapsulation layer 15 through a laser drilling process, the plurality of first through holes 151 expose the first circuit layer 13, and a first conductive through hole 16 is then formed in the first through hole 151 through a copper electroplating process.
In a specific embodiment, the specific process of spin-coating the PEDOT, the PSS aqueous solution, the silver nanowire suspension, and the graphene oxide aqueous solution on the second encapsulation layer 15 to form the second circuit layer 17 includes: arranging a line pattern mask on the second packaging layer 15, spin-coating PEDOT, namely a PSS aqueous solution on the second packaging layer 15, wherein the concentration of the PST in the spin-coated PEDOT, namely the PSS aqueous solution is preferably 25mg/ml, 30mg/ml, 35mg/ml, 40mg/ml or 45mg/ml, the rotation speed of the spin-coating is 3000 and 4000 revolutions/minute, specifically 3200 revolutions/minute, 3400 revolutions/minute, 3600 revolutions/minute or 3800 revolutions/minute, and then carrying out heat treatment at 125-140 ℃ for 20-30 minutes to form a PEDOT, namely a PSS layer; then spin-coating silver nanowire suspension, wherein the concentration of the silver nanowires in the spin-coated silver nanowire suspension is 33mg/ml, 35mg/ml or 38mg/ml, the average diameter of the silver nanowires is 25 nm, 30 nm, 35 nm, 40 nm or 45 nm, the average length of the silver nanowires is 10 microns, 11 microns, 12 microns, 13 microns, 14 microns or 15 microns, and simultaneously ensuring that the average diameter and the average length of the silver nanowires in the step (2) are larger than those of the silver nanowires in the step (1), the spin-coating rotation speed is 3000 rpm and 5000 rpm, specifically 3500 rpm, 4000 rpm, 4500 rpm or 5000 rpm, so as to form a silver nanowire layer on the PEDOT: PSS layer, then spin-coating graphene oxide aqueous solution, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 2.5mg/ml, 3mg/ml, 3.5mg/ml or 4mg/ml, the diameter of the graphene oxide is 18 micrometers, 22 micrometers, 26 micrometers or 30 micrometers, and the diameter of the graphene oxide in the step (2) is larger than that of the graphene oxide in the step (1). The spin coating speed is 2000-3000 rpm, and specifically may be 2200 rpm, 2400 rpm, 2600 rpm or 2800 rpm, to form a graphene oxide layer on the silver nanowire layer, and then the steps of forming the PEDOT-PSS layer, the silver nanowire layer and the graphene oxide layer are repeated for a plurality of times to obtain the second wiring layer 17 with a suitable thickness, where the second wiring layer 17 has excellent stability and conductivity.
In a specific embodiment, a third memory chip 181, a cache chip 182 and a fourth memory chip 183 are then disposed on the second packaging layer 15 at intervals, such that the conductive pads of the third memory chip 181, the cache chip 182 and the fourth memory chip 183 are electrically connected to the second circuit layer 17 through a conductive adhesive.
As shown in fig. 3, step (3) is performed, a third packaging layer 19 is disposed on the second packaging layer 15, the third packaging layer 19 covers the third and fourth memory chips and the buffer chip 181- The third memory chip 181 is offset to the middle of the first carrier 11 by a distance, the sixth memory chip 222 is disposed above the fourth memory chip 183, and the sixth memory chip 222 is offset to the middle of the first carrier relative to the fourth memory chip 183 by a distance.
In the step (3), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 25-35mg/ml, the average diameter of the silver nanowires is 30-60 nanometers, the average length of the silver nanowires is 15-25 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 1-3mg/ml, the diameter of the graphene oxide is 20-40 micrometers, the average diameter and the average length of the silver nanowires in the step (3) are both larger than the average diameter and the average length of the silver nanowires in the step (2), and the diameter of the graphene oxide in the step (3) is larger than the diameter of the graphene oxide in the step (2).
In a specific embodiment, a resin material is disposed on the second encapsulation layer 15 to form a third encapsulation layer 19, and the third encapsulation layer 19 may be an epoxy encapsulation layer.
In a specific embodiment, a plurality of second through holes 191 are then formed in the third encapsulation layer 19 through a laser hole opening process, the second through holes 191 expose the second circuit layer 17, and then a second conductive through hole 20 is formed in the second through hole 191 through a copper electroplating process.
In a specific embodiment, the specific process of spin-coating the third encapsulation layer 19 with the PEDOT: PSS aqueous solution, the silver nanowire suspension, and the graphene oxide aqueous solution to form the third circuit layer 21 is as follows: arranging a circuit pattern mask on the third packaging layer 19, spin-coating PEDOT, namely a PSS aqueous solution on the third packaging layer 19, wherein the concentration of the PST in the spin-coated PEDOT, namely the PSS aqueous solution is preferably 25mg/ml, 30mg/ml, 35mg/ml, 40mg/ml or 45mg/ml, the rotation speed of the spin-coating is 3000 and 4000 revolutions/minute, specifically 3200 revolutions/minute, 3400 revolutions/minute, 3600 revolutions/minute or 3800 revolutions/minute, and then carrying out heat treatment at 125-140 ℃ for 20-30 minutes to form a PEDOT, namely a PSS layer; and then spin-coating a silver nanowire suspension, wherein the concentration of the silver nanowire in the spin-coated silver nanowire suspension is 27mg/ml, 30mg/ml or 32mg/ml, the average diameter of the silver nanowire is 35 nm, 40 nm, 45 nm, 50 nm or 45 nm, the average length of the silver nanowire is 15 microns, 17 microns, 19 microns, 21 microns, 23 microns or 25 microns, the average diameter and the average length of the silver nanowire in the step (3) are both greater than those of the silver nanowire in the step (2), the spin-coating speed is 3000-5000 r/min, specifically 3500 r/min, 4000 r/min, 4500 r/min or 5000 r/min, so as to form a silver nanowire layer on the PEDOT: PSS layer, and then spin-coating an aqueous graphene oxide solution, and the concentration of the graphene oxide in the spin-coated aqueous graphene oxide solution is 1.5mg/ml, 30mg/ml or 32mg/ml, 2mg/ml, 2.5mg/ml or 3mg/ml, the diameter of the graphene oxide is 24 micrometers, 28 micrometers, 32 micrometers or 36 micrometers, and the diameter of the graphene oxide in the step (3) is larger than that of the graphene oxide in the step (2). The spin coating speed is 2000-3000 rpm, specifically 2200 rpm, 2400 rpm, 2600 rpm or 2800 rpm, to form a graphene oxide layer on the silver nanowire layer, and then the steps of forming the PEDOT-PSS layer, the silver nanowire layer and the graphene oxide layer are repeated for a plurality of times to obtain a third wiring layer 21 with a suitable thickness, wherein the third wiring layer 21 has excellent stability and conductivity.
In a specific embodiment, the fifth memory chip 221 and the sixth memory chip 222 are then disposed on the third packaging layer 19 at intervals, so that the conductive pads of the fifth memory chip 221 and the sixth memory chip 222 are electrically connected to the third wiring layer 21 through a conductive adhesive.
As shown in FIG. 4, step (4) is performed, a fourth packaging layer 23 is disposed on the third packaging layer 19, the fourth packaging layer 23 covers the fifth and sixth memory chips 221 and 222, a plurality of third through holes 231 are formed in the fourth packaging layer 23, the third through holes 231 expose the third wiring layer 21, a conductive material is deposited in the third through holes 231 to form third conductive through holes 24, PEDOT, a PSS aqueous solution, a silver nanowire suspension and a graphene oxide aqueous solution are spin-coated on the fourth packaging layer 23 to form the fourth wiring layer 25, the fourth wiring layer 25 is electrically connected with the third conductive through holes 24, and a seventh memory chip 261 and an eighth memory chip 262 are disposed on the fourth packaging layer 23 at intervals, wherein the seventh memory chip is disposed above the fifth memory chip 261 and the seventh memory chip 261 is disposed towards the fifth memory chip 221 relative to the fifth memory chip 221 The middle of the first carrier 11 is offset by a distance, the eighth memory chip 262 is disposed above the sixth memory chip 222 and the eighth memory chip 262 is offset by a distance toward the middle of the first carrier 11 with respect to the sixth memory chip 222, and then a fifth encapsulating layer 27 is disposed on the fourth encapsulating layer 23.
In the step (4), the concentration of PEDOT and PSS in the spin-coated PEDOT and PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 15-25mg/ml, the average diameter of the silver nanowires is 10-30 nanometers, the average length of the silver nanowires is 5-10 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 4-5mg/ml, and the diameter of the graphene oxide is 10-20 micrometers.
In a specific embodiment, a resin material is disposed on the third encapsulation layer 19 to form a fourth encapsulation layer 23, a fifth encapsulation layer 27 is disposed on the fourth encapsulation layer 23, and the fourth encapsulation layer 23 and the fifth encapsulation layer 27 may be epoxy encapsulation layers.
In a specific embodiment, a plurality of third vias 231 are then formed in the fourth encapsulation layer 23 by a laser drilling process, a plurality of the third vias 231 expose the third circuit layer 21, and a third conductive via 24 is then formed in the third vias 231 by a copper electroplating process.
In a specific embodiment, the specific process of spin-coating the fourth encapsulation layer 23 with the PEDOT, the PSS aqueous solution, the silver nanowire suspension, and the graphene oxide aqueous solution to form the fourth wiring layer 25 is as follows: arranging a line pattern mask on the fourth packaging layer 23, spin-coating PEDOT, namely a PSS aqueous solution on the fourth packaging layer 23, wherein the concentration of the PST in the spin-coated PEDOT, namely the PSS aqueous solution is preferably 25mg/ml, 30mg/ml, 35mg/ml, 40mg/ml or 45mg/ml, the rotation speed of the spin-coating is 3000 and 4000 revolutions/minute, specifically 3200 revolutions/minute, 3400 revolutions/minute, 3600 revolutions/minute or 3800 revolutions/minute, and then carrying out heat treatment at 125-140 ℃ for 20-30 minutes to form a PEDOT, namely a PSS layer; and then spin-coating a silver nanowire suspension, wherein the concentration of the silver nanowire in the spin-coated silver nanowire suspension is 17mg/ml, 20mg/ml or 22mg/ml, the average diameter of the silver nanowire is 15 nm, 20 nm, 25 nm or 35 nm, the average length of the silver nanowire is 6 microns, 7 microns, 8 microns, 9 microns or 10 microns, the spin-coating rotation speed is 3000-5000 r/min, specifically 3500 r/min, 4000 r/min, 4500 r/min or 5000 r/min, so as to form a silver nanowire layer on the PEDOT/PSS layer, then spin-coating a graphene oxide aqueous solution, the concentration of the graphene oxide in the spin-coated graphene oxide aqueous solution is 4.2mg/ml, 4.4mg/ml, 4.6mg/ml or 4.8mg/ml, and the diameter of the graphene oxide is 12 microns, 14 microns, 16 microns or 18 microns, and the spin coating speed is 2000-3000 rpm, specifically 2200 rpm, 2400 rpm, 2600 rpm or 2800 rpm, to form a graphene oxide layer on the silver nanowire layer, and then repeating the formation of the PEDOT-PSS layer, the silver nanowire layer and the graphene oxide layer for multiple times to obtain a fourth wiring layer 25 with a suitable thickness, wherein the fourth wiring layer 25 has excellent stability and conductivity.
In a specific embodiment, a seventh memory chip 261 and an eighth memory chip 262 are then disposed on the fourth packaging layer 23 at intervals, such that the conductive pads of the seventh memory chip 261 and the eighth memory chip 262 are electrically connected to the fourth wiring layer 25 through a conductive adhesive.
As shown in fig. 5, step (5) is performed, the first carrier 11 is removed, first grooves 281 are formed in the second, third, fourth, and fifth package layers to expose the back surfaces of the first to eighth memory chips, second grooves 282 are formed in the first package layer to expose the first circuit layer, heat dissipation posts 291 are formed in the first grooves, and conductive posts 292 are formed in the second grooves.
In the step (5), the first groove 281 and the second groove 282 are both formed by wet etching or dry etching, the material of the heat dissipation pillar 291 and the conductive pillar 292 is one or more of copper, aluminum, silver, titanium, nickel, gold, and palladium, and the heat dissipation pillar 292 and the conductive pillar 292 are formed by one or more of electroplating, chemical plating, evaporation, magnetron sputtering, electron beam evaporation, and chemical vapor deposition.
As shown in fig. 5, the present invention further provides a memory chip package structure, which is prepared by the above method.
Compared with the prior art, the invention has the following advantages: in the preparation process of the memory chip packaging structure, PEDOT, PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the packaging layer to form a circuit layer, although silver nanowires have high conductivity, pure silver nanowire grids have the defects of large surface roughness, poor adhesion, large resistance at nodes between the silver nanowires in mutual contact and the like, so that in the circuit layer, an organic conducting layer is formed by using PEDOT and PSS with excellent film forming performance, an organic conducting layer is further formed on the organic conducting layer, a graphene oxide layer is then formed on the silver nanowire grids, and the existence of the graphene oxide layer can effectively enable the silver nanowires in the silver nanowire grids in mutual contact to be more tightly jointed, so that the circuit layer with excellent conductivity and good stability is further formed, and meanwhile, conductive materials are deposited in the through holes to form conductive through holes so as to form the plane conductive through holes. By optimizing the packaging structure of the memory chip, the integration level and the functionality of the packaging structure are effectively improved.
In another embodiment, the method for manufacturing a memory chip package structure provided by the invention includes the following steps:
(1) providing a first carrier plate, arranging a first packaging layer on the first carrier plate, spin-coating PEDOT on the first packaging layer, wherein the first packaging layer is formed by PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution, and then arranging a first storage chip, a control chip and a second storage chip on the first packaging layer at intervals, so that the first storage chip, the control chip and the second storage chip are electrically connected to the first circuit layer;
(2) then, a second packaging layer is arranged on the first packaging layer, the second packaging layer covers the first and second memory chips and the control chip, then a plurality of first through holes are formed in the second packaging layer, the first through holes expose the first circuit layer, then conductive materials are deposited in the first through holes to form first conductive through holes, then PEDOT: PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the second packaging layer to form the second circuit layer, the second circuit layer is electrically connected with the first conductive through holes, and then a third memory chip, a cache chip and a fourth memory chip are arranged on the second packaging layer at intervals, wherein the cache chip is formed right above the control chip, the third memory chip is arranged above the first memory chip, and the third memory chip is arranged relative to the first memory chip and towards the first memory chip The middle of the board is offset by a distance, the fourth memory chip is arranged above the second memory chip, and the fourth memory chip is offset by a distance towards the middle of the first carrier board relative to the second memory chip;
(3) then, a third encapsulation layer is disposed on the second encapsulation layer, the third encapsulation layer covers the third and fourth memory chips and the cache chip, then a plurality of second through holes are formed in the third encapsulation layer, the plurality of second through holes expose the second circuit layer, then a conductive material is deposited in the second through holes to form second conductive through holes, then PEDOT PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the third encapsulation layer to form the third circuit layer, the third circuit layer is electrically connected with the second conductive through holes, then a fifth memory chip and a sixth memory chip are disposed on the third encapsulation layer at intervals, wherein the fifth memory chip is disposed above the third memory chip and the fifth memory chip is offset to the middle of the first carrier plate relative to the third memory chip, the sixth memory chip is arranged above the fourth memory chip and is offset to the middle of the first carrier plate by a distance relative to the fourth memory chip;
(4) then, a fourth packaging layer is arranged on the third packaging layer, the fourth packaging layer covers the fifth and sixth memory chips, then a plurality of third through holes are formed in the fourth packaging layer, the third through holes expose the third circuit layer, then conductive materials are deposited in the third through holes to form third conductive through holes, then PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the fourth packaging layer to form the fourth circuit layer, the fourth circuit layer is electrically connected with the third conductive through holes, then a seventh memory chip and an eighth memory chip are arranged on the fourth packaging layer at intervals, wherein the seventh memory chip is arranged above the fifth memory chip, and the seventh memory chip is offset to the middle of the first carrier plate by a distance relative to the fifth memory chip, the eighth memory chip is arranged above the sixth memory chip, the eighth memory chip is offset to the middle of the first carrier plate by a distance relative to the sixth memory chip, and then a fifth packaging layer is arranged on the fourth packaging layer;
(5) then, the first carrier is removed, a plurality of first grooves exposing the back surfaces of the first to eighth memory chips are formed in the second, third, fourth and fifth packaging layers, a plurality of second grooves exposing the first circuit layer are formed in the first packaging layer, a plurality of heat dissipation columns are formed in the first grooves, and a plurality of conductive columns are formed in the second grooves.
In some other embodiments, in the step (1), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20 to 50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 20 to 30mg/ml, the average diameter of the silver nanowires is 10 to 30 nm, the average length of the silver nanowires is 5 to 10 microns, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 3 to 5mg/ml, and the diameter of the graphene oxide is 10 to 20 microns.
In some other embodiments, in the step (2), the spin-coated PEDOT: PEDOT in PSS solution: the concentration of the PSS is 20-50mg/ml, the concentration of the silver nanowires in the silver nanowire suspension liquid in the spin coating is 30-40mg/ml, the average diameter of the silver nanowires is 20-50 nanometers, the average length of the silver nanowires is 9-16 micrometers, the concentration of graphene oxide in a spin-coated graphene oxide aqueous solution is 2-4mg/ml, the diameter of the graphene oxide is 15-30 micrometers, and the average diameter and the average length of the silver nanowires in the step (2) are both larger than those of the silver nanowires in the step (1), and the diameter of the graphene oxide in the step (2) is larger than that of the graphene oxide in the step (1).
In some other embodiments, in the step (3), the spin-coated PEDOT: PEDOT in PSS solution: the concentration of the PSS is 20-50mg/ml, the concentration of the silver nanowires in the silver nanowire suspension liquid of the spin coating is 25-35mg/ml, the average diameter of the silver nanowires is 30-60 nanometers, the average length of the silver nanowires is 15-25 microns, the concentration of graphene oxide in a spin-coated graphene oxide aqueous solution is 1-3mg/ml, the diameter of the graphene oxide is 20-40 microns, and the average diameter and the average length of the silver nanowires in the step (3) are both larger than those of the silver nanowires in the step (2), and the diameter of the graphene oxide in the step (3) is larger than that of the graphene oxide in the step (2).
In some other embodiments, in the step (4), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20 to 50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 15 to 25mg/ml, the average diameter of the silver nanowires is 10 to 30 nm, the average length of the silver nanowires is 5 to 10 microns, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 4 to 5mg/ml, and the diameter of the graphene oxide is 10 to 20 microns.
In some other embodiments, in step (5), the first groove and the second groove are formed by wet etching or dry etching, the material of the heat dissipation pillar and the conductive pillar is one or more of copper, aluminum, silver, titanium, nickel, gold, and palladium, and the heat dissipation pillar and the conductive pillar are formed by one or more of electroplating, chemical plating, evaporation, magnetron sputtering, electron beam evaporation, and chemical vapor deposition.
In some other embodiments, the invention further provides a memory chip packaging structure prepared by the method.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (7)

1. A preparation method of a memory chip packaging structure is characterized by comprising the following steps: the method comprises the following steps:
(1) providing a first carrier plate, arranging a first packaging layer on the first carrier plate, spin-coating PEDOT on the first packaging layer, wherein the first packaging layer is formed by PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution, and then arranging a first storage chip, a control chip and a second storage chip on the first packaging layer at intervals, so that the first storage chip, the control chip and the second storage chip are electrically connected to the first circuit layer;
(2) then, a second packaging layer is arranged on the first packaging layer, the second packaging layer covers the first and second memory chips and the control chip, then a plurality of first through holes are formed in the second packaging layer, the first through holes expose the first circuit layer, then conductive materials are deposited in the first through holes to form first conductive through holes, then PEDOT: PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the second packaging layer to form the second circuit layer, the second circuit layer is electrically connected with the first conductive through holes, and then a third memory chip, a cache chip and a fourth memory chip are arranged on the second packaging layer at intervals, wherein the cache chip is formed right above the control chip, the third memory chip is arranged above the first memory chip, and the third memory chip is arranged relative to the first memory chip and towards the first memory chip The middle of the board is offset by a distance, the fourth memory chip is arranged above the second memory chip, and the fourth memory chip is offset by a distance towards the middle of the first carrier board relative to the second memory chip;
(3) then, a third encapsulation layer is disposed on the second encapsulation layer, the third encapsulation layer covers the third and fourth memory chips and the cache chip, then a plurality of second through holes are formed in the third encapsulation layer, the plurality of second through holes expose the second circuit layer, then a conductive material is deposited in the second through holes to form second conductive through holes, then PEDOT PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the third encapsulation layer to form the third circuit layer, the third circuit layer is electrically connected with the second conductive through holes, then a fifth memory chip and a sixth memory chip are disposed on the third encapsulation layer at intervals, wherein the fifth memory chip is disposed above the third memory chip and the fifth memory chip is offset to the middle of the first carrier plate relative to the third memory chip, the sixth memory chip is arranged above the fourth memory chip and is offset to the middle of the first carrier plate by a distance relative to the fourth memory chip;
(4) then, a fourth packaging layer is arranged on the third packaging layer, the fourth packaging layer covers the fifth and sixth memory chips, then a plurality of third through holes are formed in the fourth packaging layer, the third through holes expose the third circuit layer, then conductive materials are deposited in the third through holes to form third conductive through holes, then PSS aqueous solution, silver nanowire suspension and graphene oxide aqueous solution are spin-coated on the fourth packaging layer to form the fourth circuit layer, the fourth circuit layer is electrically connected with the third conductive through holes, then a seventh memory chip and an eighth memory chip are arranged on the fourth packaging layer at intervals, wherein the seventh memory chip is arranged above the fifth memory chip, and the seventh memory chip is offset to the middle of the first carrier plate by a distance relative to the fifth memory chip, the eighth memory chip is arranged above the sixth memory chip, the eighth memory chip is offset to the middle of the first carrier plate by a distance relative to the sixth memory chip, and then a fifth packaging layer is arranged on the fourth packaging layer;
(5) then, the first carrier is removed, a plurality of first grooves exposing the back surfaces of the first to eighth memory chips are formed in the second, third, fourth and fifth packaging layers, a plurality of second grooves exposing the first circuit layer are formed in the first packaging layer, a plurality of heat dissipation columns are formed in the first grooves, and a plurality of conductive columns are formed in the second grooves.
2. The method for manufacturing a memory chip package structure according to claim 1, wherein: in the step (1), the concentration of PEDOT and PSS in the spin-coated PEDOT and PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 20-30mg/ml, the average diameter of the silver nanowires is 10-30 nanometers, the average length of the silver nanowires is 5-10 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 3-5mg/ml, and the diameter of the graphene oxide is 10-20 micrometers.
3. The method for manufacturing a memory chip package structure according to claim 1, wherein: in the step (2), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 30-40mg/ml, the average diameter of the silver nanowires is 20-50 nm, the average length of the silver nanowires is 9-16 microns, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 2-4mg/ml, the diameter of the graphene oxide is 15-30 microns, the average diameter and the average length of the silver nanowires in the step (2) are both larger than the average diameter and the average length of the silver nanowires in the step (1), and the diameter of the graphene oxide in the step (2) is larger than the diameter of the graphene oxide in the step (1).
4. The method for manufacturing a memory chip package structure according to claim 1, wherein: in the step (3), the concentration of PEDOT: PSS in the spin-coated PEDOT: PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 25-35mg/ml, the average diameter of the silver nanowires is 30-60 nanometers, the average length of the silver nanowires is 15-25 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 1-3mg/ml, the diameter of the graphene oxide is 20-40 micrometers, the average diameter and the average length of the silver nanowires in the step (3) are both larger than the average diameter and the average length of the silver nanowires in the step (2), and the diameter of the graphene oxide in the step (3) is larger than the diameter of the graphene oxide in the step (2).
5. The method for manufacturing a memory chip package structure according to claim 1, wherein: in the step (4), the concentration of PEDOT and PSS in the spin-coated PEDOT and PSS aqueous solution is 20-50mg/ml, the concentration of silver nanowires in the spin-coated silver nanowire suspension is 15-25mg/ml, the average diameter of the silver nanowires is 10-30 nanometers, the average length of the silver nanowires is 5-10 micrometers, the concentration of graphene oxide in the spin-coated graphene oxide aqueous solution is 4-5mg/ml, and the diameter of the graphene oxide is 10-20 micrometers.
6. The method for manufacturing a memory chip package structure according to claim 1, wherein: in the step (5), the first groove and the second groove are formed by wet etching or dry etching, the heat dissipation column and the conductive column are made of one or more materials selected from copper, aluminum, silver, titanium, nickel, gold and palladium, and the heat dissipation column and the conductive column are formed by one or more processes selected from electroplating, chemical plating, evaporation, magnetron sputtering, electron beam evaporation and chemical vapor deposition.
7. A memory chip package structure prepared by the method of any one of claims 1 to 6.
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