CN113675099B - Heat dissipation type stacked package body and manufacturing method thereof - Google Patents
Heat dissipation type stacked package body and manufacturing method thereof Download PDFInfo
- Publication number
- CN113675099B CN113675099B CN202111242161.8A CN202111242161A CN113675099B CN 113675099 B CN113675099 B CN 113675099B CN 202111242161 A CN202111242161 A CN 202111242161A CN 113675099 B CN113675099 B CN 113675099B
- Authority
- CN
- China
- Prior art keywords
- nanoparticles
- metal nanoparticles
- blind holes
- layer
- small
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 238000004806 packaging method and process Methods 0.000 claims abstract description 24
- 239000002082 metal nanoparticle Substances 0.000 claims description 195
- 239000000725 suspension Substances 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 45
- 239000002245 particle Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 28
- 239000002105 nanoparticle Substances 0.000 claims description 28
- 238000004528 spin coating Methods 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 239000010949 copper Substances 0.000 claims description 20
- 238000001035 drying Methods 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 17
- 239000010931 gold Substances 0.000 claims description 17
- FOIXSVOLVBLSDH-UHFFFAOYSA-N Silver ion Chemical compound [Ag+] FOIXSVOLVBLSDH-UHFFFAOYSA-N 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 239000011135 tin Substances 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 238000010329 laser etching Methods 0.000 claims description 4
- 229910052725 zinc Inorganic materials 0.000 claims description 4
- 239000011701 zinc Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 description 11
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000011049 filling Methods 0.000 description 3
- 238000012858 packaging process Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000007771 core particle Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003698 laser cutting Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000010345 tape casting Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention relates to a heat dissipation type stacked packaging body and a manufacturing method thereof. And through setting up the aperture of first blind hole is less than the aperture of second blind hole, and the degree of depth of first blind hole is less than the degree of depth of annular groove, adjacent distance between the first blind hole is greater than the diameter of first blind hole, adjacent distance between the second blind hole is greater than the diameter of second blind hole, can ensure in the preparation process, do not damage the functional area of semiconductor tube core.
Description
Technical Field
The invention relates to the field of semiconductor packaging, in particular to a heat dissipation type stacked packaging body and a manufacturing method thereof.
Background
The packaging process of a semiconductor chip is generally: the laser cutting process is firstly carried out on a semiconductor wafer to form a plurality of discrete semiconductor chips, then the cut semiconductor chips are attached to a corresponding circuit substrate or a lead frame by using a conductive adhesive material or a non-conductive adhesive material, when the semiconductor chips are flipped to the circuit substrate or the lead frame by using the conductive adhesive material, a low filling material is generally required to be arranged to improve the electrical connection stability of the semiconductor chips, and when the semiconductor chips are bonded to the circuit substrate or the lead frame by using the non-conductive adhesive material, bonding pads of the semiconductor chips are generally required to be connected to corresponding pins of the substrate or the lead frame by using gold wires, silver wires or copper wires. And then packaging the semiconductor chip by using a resin material to form a packaging structure of the semiconductor chip.
In the prior art, in order to improve the integration of the semiconductor chip package structure, a plurality of semiconductor chips are stacked and then packaged accordingly. In the conventional stacked package, the heat dissipation performance is not good, and the stacked package structure is easily overheated and fails.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned deficiencies in the prior art and to provide a heat dissipation type stacked package and a method for manufacturing the same.
In order to achieve the purpose, the invention adopts the technical scheme that:
a manufacturing method of a heat dissipation type stacked package body comprises the following steps:
step (1): providing a first carrier, disposing a semiconductor die on the carrier, and disposing a patterned mask on the first carrier.
Step (2): and then, etching the semiconductor die by using the patterned mask to form an annular groove at the peripheral edge of the upper surface of the semiconductor die, and forming a plurality of first blind holes and a plurality of second blind holes in the middle area of the upper surface of the semiconductor die, wherein the first blind holes are arranged into a first annular part, the second blind holes are arranged into a second annular part, the first annular part surrounds the second annular part, the aperture of the first blind holes is smaller than that of the second blind holes, the depth of the first blind holes is equal to that of the second blind holes, and the depth of the first blind holes is smaller than that of the annular groove.
And (3): and then spin-coating a suspension of first large-size metal nanoparticles on the semiconductor die, then performing drying treatment, then spin-coating a suspension of first small-size metal nanoparticles, and then performing drying treatment to form a first metal nanoparticle layer, wherein the first metal nanoparticle layer covers the bottom of the annular groove, the first blind hole and the second blind hole.
And (4): and then spin-coating a suspension of second large-sized metal nanoparticles on the semiconductor die, followed by a drying process, followed by spin-coating a suspension of first small-sized metal nanoparticles, followed by a drying process, to form a second metal nanoparticle layer, wherein the second large-sized metal nanoparticles have a smaller diameter than the first large-sized metal nanoparticles, and the second metal nanoparticle layer covers the first metal nanoparticle layer.
And (5): and then spin-coating a suspension of third large-size metal nanoparticles on the semiconductor die, then performing a drying process, then spin-coating a suspension of first small-size metal nanoparticles, and then performing a drying process to form a third metal nanoparticle layer, wherein the third large-size metal nanoparticles have a smaller diameter than the second large-size metal nanoparticles, and the third metal nanoparticle layer covers the second metal nanoparticle layer and covers the upper surface of the semiconductor die.
And (6): a layer of metallic bonding material is then deposited on the semiconductor die, the layer of metallic bonding material covering the third layer of metallic nanoparticles to form a first assembly.
And (7): and (3) bonding the two first components formed in the step (6) together to enable the two metal bonding material layers to be bonded and connected, and removing one first carrier plate.
And (8): then forming a first packaging layer, then forming a heat conduction layer on the first packaging layer, wherein the heat conduction layer is in contact with the first metal nanoparticle layer, the second metal nanoparticle layer, the third metal nanoparticle layer and the metal bonding material layer, and then forming a second packaging layer, and the second packaging layer wraps the heat conduction layer.
In a more preferred embodiment, in the step (1), a specific process for forming the patterned mask is: the patterned mask is formed by coating a photoresist material on the carrier, the photoresist material covering the semiconductor die, and then exposing and developing the photoresist material.
In a more preferable technical scheme, in the step (2), the annular groove, the first blind holes and the second blind holes are formed simultaneously through wet etching treatment or laser etching treatment, a distance between adjacent first blind holes is larger than a diameter of the first blind holes, a distance between adjacent second blind holes is larger than a diameter of the second blind holes, and a ratio of a depth of the first blind holes to a depth of the annular groove is 0.7-0.9.
In a more preferable technical solution, in the step (3), the first large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles, and copper nanoparticles, the particle size of the first large-sized metal nanoparticles is 300-500 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
In a more preferable technical solution, in the step (4), the second large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles, and copper nanoparticles, the particle size of the second large-sized metal nanoparticles is 200-350 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
In a more preferable technical solution, in the step (5), the third large-sized metal nanoparticle and the first small-sized metal nanoparticle are specifically one of silver nanoparticles, gold nanoparticles, and copper nanoparticles, the particle size of the third large-sized metal nanoparticle is 100-250 nm, and the particle size of the first small-sized metal nanoparticle is 10-30 nm.
In a more preferred embodiment, in the step (6), the metal bonding material is one or an alloy of two or more of copper, aluminum, silver, gold, tin, indium, lead, and zinc.
In a more preferred technical solution, in the step (8), the heat conductive layer is of an annular structure, and the heat conductive layer surrounds the first component.
The invention also provides a heat dissipation type stacked package body which is formed by adopting the manufacturing method.
Compared with the prior art, the heat dissipation type stacked package body and the manufacturing method thereof have the following beneficial effects:
in the manufacturing process of the heat dissipation type stacked package body, an annular groove is formed at the peripheral edge of the upper surface of the semiconductor tube core, a plurality of first blind holes and a plurality of second blind holes are formed in the middle area of the upper surface of the semiconductor tube core, and metal nanoparticles are filled in the annular groove, the first blind holes and the second blind holes, so that a plurality of heat dissipation paths are provided for the semiconductor tube core, and the semiconductor tube core is convenient to dissipate heat quickly. And through setting up the aperture of first blind hole is less than the aperture of second blind hole, and the degree of depth of first blind hole is less than the degree of depth of annular groove, adjacent distance between the first blind hole is greater than the diameter of first blind hole, adjacent distance between the second blind hole is greater than the diameter of second blind hole, can ensure in the preparation process, do not damage the functional area of semiconductor tube core.
In the process of filling the annular groove and the first and second blind holes, suspensions of first, second and third large-size metal nanoparticles are respectively spin-coated, the diameter of the second large-size metal nanoparticles is smaller than that of the first large-size metal nanoparticles, the diameter of the third large-size metal nanoparticles is smaller than that of the second large-size metal nanoparticles, and the suspensions of the first small-size metal nanoparticles are spin-coated to modify after the spin-coating of the suspensions of the large-size metal nanoparticles is completed.
And in the subsequent stacking bonding and packaging processes, the heat conduction layer of the annular structure is arranged to contact the first metal nanoparticle layer, the second metal nanoparticle layer, the third metal nanoparticle layer and the metal bonding material layer, so that the heat of the stacking packaging structure can be rapidly dissipated.
Drawings
Fig. 1-7 are schematic structural diagrams illustrating steps in a process of fabricating a heat dissipation stacked package according to the present invention.
Detailed Description
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a manufacturing method of a heat dissipation type stacked packaging body, which comprises the following steps:
step (1): providing a first carrier, disposing a semiconductor die on the carrier, and disposing a patterned mask on the first carrier.
Step (2): and then, etching the semiconductor die by using the patterned mask to form an annular groove at the peripheral edge of the upper surface of the semiconductor die, and forming a plurality of first blind holes and a plurality of second blind holes in the middle area of the upper surface of the semiconductor die, wherein the first blind holes are arranged into a first annular part, the second blind holes are arranged into a second annular part, the first annular part surrounds the second annular part, the aperture of the first blind holes is smaller than that of the second blind holes, the depth of the first blind holes is equal to that of the second blind holes, and the depth of the first blind holes is smaller than that of the annular groove.
And (3): and then spin-coating a suspension of first large-size metal nanoparticles on the semiconductor die, then performing drying treatment, then spin-coating a suspension of first small-size metal nanoparticles, and then performing drying treatment to form a first metal nanoparticle layer, wherein the first metal nanoparticle layer covers the bottom of the annular groove, the first blind hole and the second blind hole.
And (4): and then spin-coating a suspension of second large-sized metal nanoparticles on the semiconductor die, followed by a drying process, followed by spin-coating a suspension of first small-sized metal nanoparticles, followed by a drying process, to form a second metal nanoparticle layer, wherein the second large-sized metal nanoparticles have a smaller diameter than the first large-sized metal nanoparticles, and the second metal nanoparticle layer covers the first metal nanoparticle layer.
And (5): and then spin-coating a suspension of third large-size metal nanoparticles on the semiconductor die, then performing a drying process, then spin-coating a suspension of first small-size metal nanoparticles, and then performing a drying process to form a third metal nanoparticle layer, wherein the third large-size metal nanoparticles have a smaller diameter than the second large-size metal nanoparticles, and the third metal nanoparticle layer covers the second metal nanoparticle layer and covers the upper surface of the semiconductor die.
And (6): a layer of metallic bonding material is then deposited on the semiconductor die, the layer of metallic bonding material covering the third layer of metallic nanoparticles to form a first assembly.
And (7): and (3) bonding the two first components formed in the step (6) together to enable the two metal bonding material layers to be bonded and connected, and removing one first carrier plate.
And (8): then forming a first packaging layer, then forming a heat conduction layer on the first packaging layer, wherein the heat conduction layer is in contact with the first metal nanoparticle layer, the second metal nanoparticle layer, the third metal nanoparticle layer and the metal bonding material layer, and then forming a second packaging layer, and the second packaging layer wraps the heat conduction layer.
In the step (1), a specific process for forming the patterned mask is as follows: the patterned mask is formed by coating a photoresist material on the carrier, the photoresist material covering the semiconductor die, and then exposing and developing the photoresist material.
In the step (2), the annular groove, the first blind holes and the second blind holes are formed simultaneously through wet etching treatment or laser etching treatment, the distance between the adjacent first blind holes is larger than the diameter of the first blind holes, the distance between the adjacent second blind holes is larger than the diameter of the second blind holes, and the ratio of the depth of the first blind holes to the depth of the annular groove is 0.7-0.9.
In the step (3), the first large-size metal nanoparticles and the first small-size metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the first large-size metal nanoparticles is 300-500 nanometers, and the particle size of the first small-size metal nanoparticles is 10-30 nanometers.
In the step (4), the second large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the second large-sized metal nanoparticles is 200-350 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
In the step (5), the third large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the third large-sized metal nanoparticles is 100-250 nm, and the particle size of the first small-sized metal nanoparticles is 10-30 nm.
In the step (6), the metal bonding material is one or an alloy of two or more of copper, aluminum, silver, gold, tin, indium, lead and zinc.
Wherein, in the step (8), the heat conductive layer is of an annular structure, and the heat conductive layer surrounds the first component.
The invention also provides a heat dissipation type stacked package body which is formed by adopting the manufacturing method.
As shown in fig. 1 to 7, the present embodiment provides a method for manufacturing a heat dissipation type stacked package, including the following steps:
as shown in fig. 1, in step (1), a first carrier 100 is provided, a semiconductor die 101 is disposed on the carrier 100, and then a patterned mask 102 is disposed on the first carrier 100.
In a specific embodiment, in the step (1), a specific process for forming the patterned mask 102 is: the patterned mask 102 is formed by coating a photoresist material on the carrier 100, the photoresist material covering the semiconductor die 101, and then exposing and developing the photoresist material.
In a more specific embodiment, the first carrier 100 may be a semiconductor substrate, for example, a monocrystalline silicon substrate or a polycrystalline silicon substrate, the first carrier 100 may also be a ceramic substrate, a metal substrate or a plastic substrate, and in another embodiment, the first carrier 100 may be a rigid substrate, that is, any material that can play a supporting role may be used as the first carrier.
As shown in fig. 1, in step (2), the semiconductor die 101 is then etched by using the patterned mask 102 to form an annular trench 103 at the peripheral edge of the upper surface of the semiconductor die 101, and a plurality of first blind holes 104 and a plurality of second blind holes 105 are formed in the middle area of the upper surface of the semiconductor die 101, wherein the plurality of first blind holes 104 are arranged in a first annular portion, the plurality of second blind holes 105 are arranged in a second annular portion, the first annular portion surrounds the second annular portion, the diameter of the first blind holes 104 is smaller than that of the second blind holes 105, the depth of the first blind holes 104 is equal to that of the second blind holes 105, and the depth of the first blind holes 104 is smaller than that of the annular trench 103.
In a specific embodiment, in the step (2), the annular trench 103, the first blind holes 104, and the second blind holes 105 are formed simultaneously through wet etching processing or laser etching processing, a distance between adjacent first blind holes 104 is greater than a diameter of the first blind holes 104, a distance between adjacent second blind holes 105 is greater than a diameter of the second blind holes 105, and a ratio of a depth of the first blind holes 104 to a depth of the annular trench 103 is 0.7-0.9.
In a more specific embodiment, the annular trench 103, the first blind via 104 and the second blind via 105 are formed simultaneously by using a wet etching process, a ratio of a hole diameter of the first blind via 104 to a hole diameter of the second blind via 105 is 0.7 to 0.8, and more specifically may be 0.85, a ratio of a distance between adjacent first blind vias 104 to a diameter of the first blind via 104 is 1.2 to 1.4, and more specifically may be 1.25, a ratio of a distance between adjacent second blind vias 105 to a diameter of the second blind via 105 is 1.2 to 1.4, and more specifically may be 1.25, and a ratio of a depth of the first blind via 104 to a depth of the annular trench 103 is 0.7 to 0.9, and more specifically may be 0.8.
As shown in fig. 2, in step (3), a suspension of first large-sized metal nanoparticles is then spin-coated on the semiconductor die 101, followed by a baking process, followed by spin-coating a suspension of first small-sized metal nanoparticles, followed by a baking process, to form a first metal nanoparticle layer 106, wherein the first metal nanoparticle layer 106 covers the annular trench 103, the first blind via 104, and the bottom of the second blind via 105.
In a specific embodiment, in the step (3), the first large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the first large-sized metal nanoparticles is 300-500 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
In a more specific embodiment, by dispersing metal nanoparticles of different sizes in a suitable solvent such as ethanol, acetone, etc., to prepare suspensions of first large-sized metal nanoparticles and suspensions of first small-sized metal nanoparticles at different concentrations, more preferably, at a concentration of the first large-sized metal nanoparticles of 5 to 30 mg/ml, more preferably, 10 to 20 mg/ml, in the suspension of the first large-sized metal nanoparticles, at a concentration of the first small-sized metal nanoparticles of 2 to 8 mg/ml, more preferably, 4 to 6mg/ml, by optimizing the concentration of the metal nanoparticles of each suspension, the first small-sized metal nanoparticles are facilitated to be inserted into the gaps between the first large-sized metal nanoparticles, thereby increasing the heat conduction path.
In a more specific embodiment, the rotation speed of the spin coating of the suspension of the first large-sized metal nanoparticles and the suspension of the first small-sized metal nanoparticles is 2000-.
In a more specific embodiment, the first large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically silver nanoparticles, the particle diameter of the first large-sized metal nanoparticles is 350-450 nm, and the particle diameter of the first small-sized metal nanoparticles is 20-30 nm.
As shown in fig. 3, in step (4), a suspension of second large-sized metal nanoparticles having a smaller diameter than the first large-sized metal nanoparticles is then spin-coated on the semiconductor die, followed by a baking process, followed by a suspension of first small-sized metal nanoparticles, followed by a baking process, to form a second metal nanoparticle layer 107 covering the first metal nanoparticle layer.
In a specific embodiment, in the step (4), the second large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the second large-sized metal nanoparticles is 200-350 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
In a more specific embodiment, by dispersing metal nanoparticles of different sizes in a suitable solvent such as ethanol, acetone, etc., to prepare suspensions of second large-sized metal nanoparticles and suspensions of first small-sized metal nanoparticles at different concentrations, more preferably, at a concentration of the second large-sized metal nanoparticles of 20 to 50 mg/ml, more preferably, 30 to 40 mg/ml, in the suspensions of the second large-sized metal nanoparticles, at a concentration of the first small-sized metal nanoparticles of 2 to 8 mg/ml, more preferably, 4 to 6mg/ml, by optimizing the concentration of the metal nanoparticles of each suspension, the first small-sized metal nanoparticles are facilitated to be inserted into the gaps between the second large-sized metal nanoparticles, thereby increasing the heat conduction path.
In a more specific embodiment, the rotation speed of the spin coating of the suspension of the second large-sized metal nanoparticles and the suspension of the first small-sized metal nanoparticles is 2000-.
In a more specific embodiment, the second large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically silver nanoparticles, the second large-sized metal nanoparticles have a particle size of 250-300 nm, and the first small-sized metal nanoparticles have a particle size of 20-30 nm.
As shown in fig. 4, in step (5): a suspension of third large-sized metal nanoparticles having a smaller diameter than the second large-sized metal nanoparticles is then spin-coated on the semiconductor die, followed by a drying process, followed by a suspension of first small-sized metal nanoparticles, followed by a drying process, to form a third metal nanoparticle layer 108 covering the second metal nanoparticle layer and covering the upper surface of the semiconductor die.
In a specific embodiment, in the step (5), the third large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the third large-sized metal nanoparticles is 100-250 nm, and the particle size of the first small-sized metal nanoparticles is 10-30 nm.
In a more specific embodiment, by dispersing metal nanoparticles of different sizes in a suitable solvent such as ethanol, acetone, etc., to prepare suspensions of third large-sized metal nanoparticles and suspensions of first small-sized metal nanoparticles at different concentrations, more preferably, at a concentration of the second large-sized metal nanoparticles of 15 to 40 mg/ml, more preferably, 20 to 30 mg/ml, in the suspensions of the third large-sized metal nanoparticles, at a concentration of the first small-sized metal nanoparticles of 2 to 8 mg/ml, more preferably, 4 to 6mg/ml, by optimizing the concentration of the metal nanoparticles of each suspension, the first small-sized metal nanoparticles are facilitated to be inserted into the gaps between the third large-sized metal nanoparticles, thereby increasing the heat conduction path.
In a more specific embodiment, the rotation speed of the spin coating of the suspension of the third large-sized metal nanoparticles and the suspension of the first small-sized metal nanoparticles is 2000-.
In a more specific embodiment, the third large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically silver nanoparticles, the third large-sized metal nanoparticles have a particle size of 180-220 nm, and the first small-sized metal nanoparticles have a particle size of 20-30 nm.
As shown in fig. 5, in step (6): a layer of metallic bonding material 109 is then deposited on the semiconductor die 101, the layer of metallic bonding material 109 covering the third layer of metallic nanoparticles 108 to form a first component 110.
In a specific embodiment, in the step (6), the metal bonding material is one or an alloy of two or more of copper, aluminum, silver, gold, tin, indium, lead, and zinc.
In a specific embodiment, the metal bonding material layer 109 is deposited by a suitable process such as coating, doctor blading, electroplating, electroless plating, evaporation, chemical vapor deposition, and the like, and more specifically, the metal bonding material layer may be a suitable material such as metallic copper, tin-containing solder, copper-containing solder, and the like.
As shown in fig. 6, in step (7): and (3) bonding the two first assemblies 110 formed in the step (6) together to bond the two metal bonding material layers 109, and removing one of the first carrier boards 100.
In a specific embodiment, two metal bonding material layers 109 are bonded and connected by a suitable process such as laser irradiation or heating.
As shown in fig. 7, in step (8): then, a first packaging layer 111 is formed, then, a heat conduction layer 112 is formed on the first packaging layer 111, the heat conduction layer 112 contacts the first metal nanoparticle layer 106, the second metal nanoparticle layer 107, the third metal nanoparticle layer 108 and the metal bonding material layer 109, then, a second packaging layer 113 is formed, and the second packaging layer 113 wraps the heat conduction layer 112.
In a specific embodiment, in the step (8), the heat conductive layer 112 is in a ring structure, and the heat conductive layer 112 surrounds the first component 110.
In a specific embodiment, the first encapsulation layer 111 and the second encapsulation layer 113 may be epoxy resin.
In a specific embodiment, the heat conductive layer 112 may be made of a suitable metal material such as copper, aluminum, or silver, and is formed by a suitable process such as evaporation, electroplating, magnetron sputtering, or the like.
As shown in fig. 7, the present invention further provides a heat dissipation stacked package formed by the above-mentioned manufacturing method.
Compared with the prior art, the heat dissipation type stacked package body and the manufacturing method thereof have the following beneficial effects:
in the manufacturing process of the heat dissipation type stacked package body, an annular groove is formed at the peripheral edge of the upper surface of the semiconductor tube core, a plurality of first blind holes and a plurality of second blind holes are formed in the middle area of the upper surface of the semiconductor tube core, and metal nanoparticles are filled in the annular groove, the first blind holes and the second blind holes, so that a plurality of heat dissipation paths are provided for the semiconductor tube core, and the semiconductor tube core is convenient to dissipate heat quickly. And through setting up the aperture of first blind hole is less than the aperture of second blind hole, and the degree of depth of first blind hole is less than the degree of depth of annular groove, adjacent distance between the first blind hole is greater than the diameter of first blind hole, adjacent distance between the second blind hole is greater than the diameter of second blind hole, can ensure in the preparation process, do not damage the functional area of semiconductor tube core.
In the process of filling the annular groove and the first and second blind holes, suspensions of first, second and third large-size metal nanoparticles are respectively spin-coated, the diameter of the second large-size metal nanoparticles is smaller than that of the first large-size metal nanoparticles, the diameter of the third large-size metal nanoparticles is smaller than that of the second large-size metal nanoparticles, and the suspensions of the first small-size metal nanoparticles are spin-coated to modify after the spin-coating of the suspensions of the large-size metal nanoparticles is completed.
And in the subsequent stacking bonding and packaging processes, the heat conduction layer of the annular structure is arranged to contact the first metal nanoparticle layer, the second metal nanoparticle layer, the third metal nanoparticle layer and the metal bonding material layer, so that the heat of the stacking packaging structure can be rapidly dissipated.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for manufacturing a heat dissipation type stacked package body is characterized in that: the method comprises the following steps:
step (1): providing a first carrier plate, arranging a semiconductor tube core on the carrier plate, and then arranging a patterned mask on the first carrier plate;
step (2): then, etching the semiconductor die by using the patterned mask to form an annular groove at the peripheral edge of the upper surface of the semiconductor die, and forming a plurality of first blind holes and a plurality of second blind holes in the middle area of the upper surface of the semiconductor die, wherein the plurality of first blind holes are arranged into a first annular part, the plurality of second blind holes are arranged into a second annular part, the first annular part surrounds the second annular part, the aperture of the first blind holes is smaller than that of the second blind holes, the depth of the first blind holes is equal to that of the second blind holes, and the depth of the first blind holes is smaller than that of the annular groove;
and (3): spin-coating a suspension of first large-size metal nanoparticles on the semiconductor die, then performing drying treatment, spin-coating a suspension of first small-size metal nanoparticles, and then performing drying treatment to form a first metal nanoparticle layer, wherein the first metal nanoparticle layer covers the annular groove, the first blind hole and the bottom of the second blind hole;
and (4): spin-coating a suspension of second large-size metal nanoparticles on the semiconductor die, then performing drying treatment, spin-coating a suspension of first small-size metal nanoparticles, and then performing drying treatment to form a second metal nanoparticle layer, wherein the second large-size metal nanoparticles have a smaller diameter than the first large-size metal nanoparticles, and the second metal nanoparticle layer covers the first metal nanoparticle layer;
and (5): then spin-coating a suspension of third large-size metal nanoparticles on the semiconductor die, then performing drying treatment, then spin-coating a suspension of first small-size metal nanoparticles, and then performing drying treatment to form a third metal nanoparticle layer, wherein the third large-size metal nanoparticles have a smaller diameter than the second large-size metal nanoparticles, and the third metal nanoparticle layer covers the second metal nanoparticle layer and covers the upper surface of the semiconductor die;
and (6): subsequently depositing a layer of metallic bonding material on the semiconductor die, the layer of metallic bonding material covering the third layer of metallic nanoparticles to form a first assembly;
and (7): bonding the two first components formed in the step (6) together to enable the two metal bonding material layers to be bonded and connected, and removing one first carrier plate;
and (8): then forming a first packaging layer, then forming a heat conduction layer on the first packaging layer, wherein the heat conduction layer is in contact with the first metal nanoparticle layer, the second metal nanoparticle layer, the third metal nanoparticle layer and the metal bonding material layer, and then forming a second packaging layer, and the second packaging layer wraps the heat conduction layer.
2. The method of claim 1, wherein: in the step (1), a specific process for forming the patterned mask is as follows: the patterned mask is formed by coating a photoresist material on the carrier, the photoresist material covering the semiconductor die, and then exposing and developing the photoresist material.
3. The method of claim 1, wherein: in the step (2), the annular groove, the first blind holes and the second blind holes are formed simultaneously through wet etching treatment or laser etching treatment, the distance between the adjacent first blind holes is larger than the diameter of the first blind holes, the distance between the adjacent second blind holes is larger than the diameter of the second blind holes, and the ratio of the depth of the first blind holes to the depth of the annular groove is 0.7-0.9.
4. The method of claim 1, wherein: in the step (3), the first large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the first large-sized metal nanoparticles is 300-500 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
5. The method of claim 1, wherein: in the step (4), the second large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the second large-sized metal nanoparticles is 200-350 nanometers, and the particle size of the first small-sized metal nanoparticles is 10-30 nanometers.
6. The method of claim 1, wherein: in the step (5), the third large-sized metal nanoparticles and the first small-sized metal nanoparticles are specifically one of silver nanoparticles, gold nanoparticles and copper nanoparticles, the particle size of the third large-sized metal nanoparticles is 100-250 nm, and the particle size of the first small-sized metal nanoparticles is 10-30 nm.
7. The method of claim 1, wherein: in the step (6), the metal bonding material is one or an alloy of two or more of copper, aluminum, silver, gold, tin, indium, lead and zinc.
8. The method of claim 1, wherein: in the step (8), the heat conductive layer is of an annular structure, and the heat conductive layer surrounds the first component.
9. A heat dissipation stacked package formed by the method of any one of claims 1 to 8.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111242161.8A CN113675099B (en) | 2021-10-25 | 2021-10-25 | Heat dissipation type stacked package body and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202111242161.8A CN113675099B (en) | 2021-10-25 | 2021-10-25 | Heat dissipation type stacked package body and manufacturing method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113675099A CN113675099A (en) | 2021-11-19 |
CN113675099B true CN113675099B (en) | 2021-12-17 |
Family
ID=78550990
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202111242161.8A Active CN113675099B (en) | 2021-10-25 | 2021-10-25 | Heat dissipation type stacked package body and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN113675099B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN115148609B (en) * | 2022-09-05 | 2022-11-08 | 山东中清智能科技股份有限公司 | Heat dissipation type power module and preparation method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112420641A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Power element packaging structure and preparation method thereof |
CN112420640A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Stack packaging structure and preparation method thereof |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7554193B2 (en) * | 2005-08-16 | 2009-06-30 | Renesas Technology Corp. | Semiconductor device |
KR100865125B1 (en) * | 2007-06-12 | 2008-10-24 | 삼성전기주식회사 | Semiconductor and method for manufacturing thereof |
-
2021
- 2021-10-25 CN CN202111242161.8A patent/CN113675099B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112420641A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Power element packaging structure and preparation method thereof |
CN112420640A (en) * | 2020-11-26 | 2021-02-26 | 苏州矽锡谷半导体科技有限公司 | Stack packaging structure and preparation method thereof |
Also Published As
Publication number | Publication date |
---|---|
CN113675099A (en) | 2021-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7902676B2 (en) | Stacked semiconductor device and fabricating method thereof | |
US8859912B2 (en) | Coreless package substrate and fabrication method thereof | |
US9070616B2 (en) | Method of fabricating packaging substrate | |
TWI475935B (en) | Coreless package substrate and fabrication method thereof | |
TWI496254B (en) | Package structure of embedded semiconductor component and manufacturing method thereof | |
TW202107659A (en) | Semiconductor devices and methods of manufacturing semiconductor devices | |
US8367473B2 (en) | Substrate having single patterned metal layer exposing patterned dielectric layer, chip package structure including the substrate, and manufacturing methods thereof | |
TWI463925B (en) | Package substrate and fabrication method thereof | |
TW201110253A (en) | Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure | |
JP2012119648A (en) | Semiconductor device and method for forming pad layout of flip chip semiconductor die | |
US11450620B2 (en) | Innovative fan-out panel level package (FOPLP) warpage control | |
TW202203331A (en) | Packaged substrate and manufacturing method thereof | |
TWI541957B (en) | Semiconductor package and package substrate | |
US12057324B2 (en) | Semiconductor package having a semiconductor element and a wiring structure | |
CN113675099B (en) | Heat dissipation type stacked package body and manufacturing method thereof | |
US7541217B1 (en) | Stacked chip structure and fabrication method thereof | |
KR102210802B1 (en) | Semiconductor device and method for manufacturing the same | |
TWI694577B (en) | Semiconductor structure and manufacturing method thereof | |
JP2002076167A (en) | Semiconductor chip, stacked semiconductor package and their manufacturing method | |
TW202046456A (en) | Electronic package and manufacturing method thereof | |
US9576820B2 (en) | Semiconductor structure and method of manufacturing the same | |
CN111524817A (en) | Semiconductor chip stack package and forming method thereof | |
US11373956B2 (en) | Semiconductor device package and method of manufacturing the same | |
TWI842404B (en) | Method of electronic package and carrier structure thereof | |
CN216671634U (en) | Multi-chip packaging piece |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |