CN112992888A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
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- CN112992888A CN112992888A CN202110407586.3A CN202110407586A CN112992888A CN 112992888 A CN112992888 A CN 112992888A CN 202110407586 A CN202110407586 A CN 202110407586A CN 112992888 A CN112992888 A CN 112992888A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
Abstract
The embodiment of the invention provides a chip packaging structure and a preparation method of the chip packaging structure, and relates to the technical field of chip packaging. Through setting up first leading electrical pillar to realize the electricity between a plurality of structure chips and the medium basic unit through first wiring layer and be connected, avoided the routing, increased the quantity of piling up of chip simultaneously, guaranteed the stability of structure.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a preparation method of the chip packaging structure.
Background
With the rapid development of the semiconductor industry, electronic products are miniaturized more and more thinly to meet the requirements of users, and meanwhile, the product performance and the memory requirement are higher and higher, so that a semiconductor packaging structure adopts a multi-chip stacking (Stack-Die) technology or a chip fow (flow over wire) stacking technology to Stack two or more chips in a single packaging structure, thereby realizing the reduction of the packaging volume of the product and the improvement of the product performance. Such stacked products (memory card/storage card) usually have 2 types of chips, memory storage chips and chips, and are packaged in the same substrate unit by stacking, for example: the NAND product requires a large enough product capacity and a large number of stacked layers, and the memory card performance is limited by the number of memory chips and the size of the stacked structure.
In the prior art, the wire bonding mode is usually adopted to realize the electrical connection and control between chips and between the chips and a substrate, however, as the number of stacked layers of the chips increases, the longer the wire bonding of the top chip is, the more difficult the control is, the unstable wire bonding, such as bridging or wire breaking, is easily caused, and as mutual interference between the wire bonding needs to be avoided, the wire bonding structure of the top layer needs to be expanded to the outside, so that the packaging size of the product is increased, and the wire bonding also causes the increase of process steps and the increase of cost.
Disclosure of Invention
The present invention provides a chip package structure and a method for manufacturing the chip package structure, which can increase the number of stacked chips, avoid the problem of bridging or wire breaking caused by wire bonding, and ensure the stability of the chip package structure.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a chip package structure, including:
a dielectric base layer;
the chip plastic package module is arranged on the medium base layer and comprises a control chip, a plastic package body and a plurality of first structure chips, the first structure chips are stacked to form a first stacked structure attached to the medium base layer, the control chip is arranged on one side of the first stacked structure and is electrically connected with the medium base layer, and the plastic package body wraps the control chip and the first stacked structure and is attached to the medium base layer;
the plastic package is internally provided with a first conductive column, the first conductive column is located between the first laminated structure and the control chip, a first wiring layer is arranged on the upper side or the lower side of each first structure chip, and the first wiring layer is connected with the first conductive column.
In an alternative embodiment, each of the first structural chips is provided with a first conductive bump on an upper side or a lower side thereof, and the first wiring layer is connected to the first conductive bump.
In an optional implementation mode, the chip plastic package module further includes a plurality of second structure chips, and is a plurality of the second structure chips are stacked and form a second stacked structure attached to the medium base layer, the control chip is disposed between the first stacked structure and the second stacked structure, the second stacked structure is wrapped in the plastic package body, and a second conductive pillar is further disposed in the plastic package body, the second conductive pillar is located between the second stacked structure and the control chip, each of the upper side or the lower side of the second structure chip is provided with a second wiring layer, and the second wiring layer is connected to the second conductive pillar.
In an alternative embodiment, each of the second structural chips is provided with a second conductive bump on an upper side or a lower side thereof, and the second wiring layer is connected to the second conductive bump.
In an alternative embodiment, a control conductive bump is disposed on the lower side of the control chip, and the control conductive bump is connected to the adjacent first wiring layer and the second wiring layer.
In an optional embodiment, a third conductive pillar is further disposed on the lower side of the control chip, the third conductive pillar extends to the dielectric base layer, and the control chip is electrically connected to the dielectric base layer through the third conductive pillar.
In an optional embodiment, a first connection pad, a second connection pad and a third connection pad are disposed on the dielectric base layer, the first conductive pillar is connected to the first connection pad, the second conductive pillar is connected to the second connection pad, and the third conductive pillar is connected to the third connection pad.
In an optional embodiment, a heat dissipation adhesive layer is further disposed on the upper side of the control chip, and the heat dissipation adhesive layer penetrates through the upper surface of the plastic package body.
In an optional embodiment, the upper surface of the plastic package body is further provided with a heat dissipation sheet, and the heat dissipation sheet is connected with the heat dissipation glue layer.
In a second aspect, the present invention provides a method for preparing a chip package structure, for preparing the chip package structure according to the foregoing embodiments, including:
preparing a chip plastic package module by using a carrier;
forming a medium base layer on the bottom side of the chip plastic package module;
the chip plastic package module comprises a control chip, a plurality of first structure chips and a plastic package body, wherein the first structure chips are stacked to form a first stacked structure attached to the medium base layer, the control chip is arranged on one side of the first stacked structure and is electrically connected with the medium base layer, and the plastic package body wraps the control chip and the first stacked structure and is attached to the medium base layer; still be provided with first conductive pillar in the plastic packaging body, first conductive pillar is located first laminated structure with between the control chip, every the upside or the downside of first structure chip are provided with first wiring layer, first wiring layer with first conductive pillar is connected.
The beneficial effects of the embodiment of the invention include, for example:
in the chip package structure provided by the embodiment of the invention, a plurality of first structure chips are stacked to form a first stacked structure, a control chip is arranged on one side of the first stacked structure, the control chip is electrically connected with a medium base layer, and a plastic package body is coated outside the control chip and the first stacked structure and is attached to the medium base layer, wherein a first conductive pillar is further arranged in the plastic package body and is positioned between the first stacked structure and the control chip, a first wiring layer is arranged on the upper side or the lower side of each first structure chip, and the first wiring layer is connected with the first conductive pillar. Through setting up first leading electrical pillar to realize the electricity between a plurality of structure chips and the medium basic unit through first wiring layer and be connected, avoided the routing, increased the quantity of piling up of chip simultaneously, guaranteed the stability of structure.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a chip package structure according to an embodiment of the invention;
fig. 2 is another schematic structural diagram of a chip package structure according to an embodiment of the invention;
fig. 3 to 9 are flow charts of a manufacturing process of the chip package structure according to the embodiment of the invention.
Icon: 100-chip package structure; 110-a media substrate; 111-a first splice tray; 113-a second connecting disc; 115-third land; 130-chip plastic package module; 131-a control chip; 1311-controlling the conductive bumps; 133-a plastic package body; 135 a-a first structural chip; 135 b-a second structural chip; 1351 — a first conductive bump; 1353-second conductive bump; 137 a-a first wiring layer; 137 b-a second wiring layer; 139 a-first conductive post; 139 b-second conductive post; 139c — a third conductive pillar; 150-a heat dissipation glue layer; 170-a heat sink; 200-carrier.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. indicate an orientation or a positional relationship based on that shown in the drawings or that the product of the present invention is used as it is, this is only for convenience of description and simplification of the description, and it does not indicate or imply that the device or the element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present invention.
Furthermore, the appearances of the terms "first," "second," and the like, if any, are used solely to distinguish one from another and are not to be construed as indicating or implying relative importance.
As disclosed in the background art, the stacked structure of the chips in the prior art usually requires wire bonding for electrical connection to achieve power supply and control. However, as the number of stacked chips increases, the wire bonding method has more and more disadvantages. Firstly, since the wire bonding needs to be connected with the substrate, the longer the wire bonding length of the top chip is along with the increase of the stacking height of the chip, the wire bonding is difficult to control, and further the wire bonding is unstable, and the risk such as bridging or wire breaking is easy to occur. Secondly, need avoid the line body to interfere each other during the routing, so along with the increase of routing height, the scope of the routing dish on the base plate corresponds the expansion, leads to the routing scope also to need outside expansion, and encapsulation size increases when the encapsulation, has increased product size, is unfavorable for the miniaturization of product. Meanwhile, the wire bonding also causes the increase of the process steps and the cost.
In addition, in the conventional chip stacking structure, due to the increase of the stacking height, the control chip is stacked on the lower layer of the chip, and the control chip can generate a large amount of heat, and the thicknesses of the stacking structure and the plastic package body are thick, so that the heat dissipation efficiency is low, and the performance of the product is affected.
In order to solve the above problems, the present invention provides a chip package structure and a method for manufacturing the chip package structure, and it should be noted that features in the embodiments of the present invention may be combined with each other without conflict.
First embodiment
Referring to fig. 1 to 9, the present embodiment provides a chip package structure 100, which can increase the number of stacked chips, and simultaneously avoid the problem of bridging or wire breaking caused by wire bonding, thereby ensuring the stability of the package structure. And the heat dissipation effect is good, and the performance of the product can be improved.
Referring to fig. 1, the chip package structure 100 provided in this embodiment includes a medium base layer 110 and a chip plastic package module 130, where the chip plastic package module 130 is attached to the medium base layer 110, and specifically, the chip plastic package module 130 may be formed on a carrier 200, and the medium base layer 110 is directly formed on a bottom side of the chip plastic package module 130 after the carrier 200 is removed, so that the chip plastic package module 130 is disposed on the medium base layer 110. Of course, the dielectric substrate 110 can be prepared in advance and directly attached to the bottom of the die module 130.
In this embodiment, the chip plastic package module 130 includes a control chip 131, a plastic package body 133, and a plurality of first structure chips 135a, where the plurality of first structure chips 135a are stacked and form a first stacked structure attached to the medium base layer 110, the control chip 131 is disposed on one side of the first stacked structure and electrically connected to the medium base layer 110, and the plastic package body 133 is wrapped outside the control chip 131 and the first stacked structure and attached to the medium base layer 110; the plastic package body 133 is further provided with first conductive pillars 139a, the first conductive pillars 139a are located between the first stacked structure and the control chip 131, the upper side or the lower side of each first structure chip 135a is provided with a first wiring layer 137a, and the first wiring layer 137a is connected to the first conductive pillars 139 a.
In this embodiment, the control chip 131 is disposed in the middle of the plastic package body 133 and electrically connected to the dielectric substrate 110, and the control chip 131 is connected to one of the first wiring layers 137a, so that the control chip 131 can be electrically connected to the first conductive pillars 139a, and the plurality of first structural chips 135a and the control chip 131 are electrically connected to each other, thereby ensuring power supply and control functions.
In the present embodiment, the first wiring layer 137a is located on the bottom of the first structural chip 135a, and is connected to the bottom of the first conductive pillar 139a, so as to electrically connect the first structural chip 135a of the bottom layer and the dielectric base layer 110. Of course, in other preferred embodiments, the first structural chip 135a at the bottom layer can also be directly connected to the dielectric substrate 110 in a flip-chip manner, and the electrical connection manner is not particularly limited herein.
In the present embodiment, the upper side or the lower side of each first structure chip 135a is provided with a first conductive bump 1351, and the first wiring layer 137a is connected to the first conductive bump 1351. Preferably, the first conductive bumps 1351 of the first structural chip 135a at the bottom are located at the bottom side thereof, the first conductive bumps 1351 on the rest of the first structural chips 135a are located at the top side thereof, the first conductive pillars 139a are arranged in a vertical direction, and the plurality of first wiring layers 137a extend horizontally and are simultaneously connected with the corresponding first conductive bumps 1351 and the first conductive pillars 139a, so as to realize the electrical connection between the plurality of first structural chips 135a and the first conductive pillars 139 a.
Further, the chip plastic package module 130 may further include a plurality of second structure chips 135b, the plurality of second structure chips 135b are stacked and form a second stacked structure attached to the dielectric base layer 110, the control chip 131 is disposed between the first stacked structure and the second stacked structure, the second stacked structure is wrapped in the plastic package body 133, a second conductive pillar 139b is further disposed in the plastic package body 133, the second conductive pillar 139b is located between the second stacked structure and the control chip 131, a second wiring layer 137b is disposed on an upper side or a lower side of each second structure chip 135b, and the second wiring layer 137b is connected to the second conductive pillar 139 b.
It should be noted that in this embodiment, the plurality of first structural chips 135a and the plurality of second structural chips 135b are both memory chips and have the same specification, the plurality of first structural chips 135a and the plurality of second structural chips 135b are respectively disposed on two sides of the control chip 131 and are arranged in a one-to-one correspondence, and the first conductive pillars 139a and the second conductive pillars 139b are also respectively disposed on two sides of the control chip 131 and are respectively connected to the plurality of first wiring layers 137a and the plurality of second wiring layers 137b to achieve electrical connection.
In an embodiment, the upper side or the lower side of each second structural chip 135b is provided with a second conductive bump 1353, and the second wiring layer 137b is connected with the second conductive bump 1353. Preferably, the second conductive bump 1353 on the bottom second structural chip 135b is located at the bottom side thereof and is electrically connected to the second conductive pillar 139b through the second wiring layer 137b at the bottom side, and of course, the second structural chip 135b located at the bottom here may also be electrically connected to the dielectric base layer 110 directly through the second conductive bump 1353, that is, an electrical connection structure is formed by soldering a pad on the dielectric base layer 110 and the second conductive bump 1353. The upper side of the other second structural chip 135b is provided with a second conductive bump 1353, and is electrically connected to the second conductive pillar 139b through the second wiring layer 137b on the upper side.
It should be noted that, in the present embodiment, the first wiring layer 137a is located on the upper side or the lower side of the first structural chip 135a, and the second wiring layer 137b is located on the upper side or the lower side of the second structural chip 135b, which is only an example, in other preferred embodiments, the first wiring layer 137a may be disposed on the upper sides of a plurality of first structural chips 135a, the first wiring layer 137a may be disposed on the lower sides of the rest of first structural chips 135a, the second wiring layer 137b may be disposed on the upper sides of a plurality of second structural chips 135b, and the second wiring layer 137b may be disposed on the lower sides of the rest of second structural chips 135b, and the positional relationship between the upper side and the lower side of the wiring layer and the structural chips is not specifically limited herein.
In the present embodiment, the lower side of the control chip 131 is provided with a control conductive bump 1311, and the control conductive bump 1311 is connected to the adjacent first and second wiring layers 137a and 137 b. Specifically, the first wiring layer 137a and the second wiring layer 137b on two adjacent sides of the control chip 131 extend to the control conductive bump 1311, so as to achieve electrical connection between the control chip 131 and the first conductive pillar 139a and the second conductive pillar 139b, in other preferred embodiments, the control conductive bump 1311 may also be disposed on the upper side of the control chip 131, and is electrically connected through the first wiring layer 137a and the second wiring layer 137b adjacent to the upper side.
Further, the lower side of the control chip 131 is further provided with a third conductive pillar 139c, the third conductive pillar 139c extends to the dielectric base layer 110, and the control chip 131 is electrically connected to the dielectric base layer 110 through the third conductive pillar 139 c. Specifically, there are two third conductive pillars 139c, one of the third conductive pillars 139c is electrically connected to the first conductive pillar 139a through the first wiring layer 137a, and the other third conductive pillar 139c is electrically connected to the second conductive pillar 139b through the second wiring layer 137 b.
In the present embodiment, the dielectric substrate 110 is provided with a first connection pad 111, a second connection pad 113, and a third connection pad 115, the first conductive pillar 139a is connected to the first connection pad 111, the second conductive pillar 139b is connected to the second connection pad 113, and the third conductive pillar 139c is connected to the third connection pad 115. Specifically, the number of the first lands 111 is the same as the number of the first conductive pillars 139a and the positions thereof are opposite to each other, the number of the second lands 113 is the same as the number of the second conductive pillars 139b and the positions thereof are opposite to each other, and the number of the third lands 115 is the same as the number of the third conductive pillars 139c and the positions thereof are opposite to each other.
In other preferred embodiments of the present invention, the control chip 131 may also be directly disposed on the dielectric base layer 110, that is, the control chip 131 corresponds to the first structural chip 135a and the second structural chip 135b of the bottom layer, and is electrically connected to the first conductive pillar 139a and the second conductive pillar 139b through the wiring structure on the bottom side, so as to save the arrangement of the third conductive pillar 139c and simplify the process flow. The number of corresponding layers of the control chip 131 and the first and second structural chips 135a and 135b is not particularly limited.
It should be noted that the control chip 131 may be a flip chip and is directly soldered on the dielectric base layer 110 through the control conductive bump 1311 to achieve electrical connection, or may be a flip chip and is electrically connected through a bottom conductive adhesive layer, or a front chip and is electrically connected to the first conductive pillar 139a and the second conductive pillar 139b through a conductive adhesive layer, and the arrangement manner of the control chip 131 is not specifically limited herein.
In this embodiment, a first adhesive film layer is disposed between two adjacent first structure chips 135a, and a second adhesive film layer is disposed between two adjacent second structure chips 135b, so that the first structure chips 135a are stacked by the first adhesive film layer, and the second adhesive film layer is used for absorbing the second structure chips 135 b.
In this embodiment, a heat dissipation adhesive layer 150 is further disposed on the upper side of the control chip 131, and the heat dissipation adhesive layer 150 penetrates through the upper surface of the plastic package body 133. Specifically, by forming a groove on the upper side of the plastic package body 133, a glue groove is formed, and the depth of the glue groove is determined by the control chip 131, i.e., the glue groove extends to the surface of the control chip 131. Then, the glue groove is filled with heat dissipation glue to form the heat dissipation glue layer 150, so that heat generated by the control chip 131 can be transferred outwards through the heat dissipation glue layer 150, and heat dissipation is achieved.
In this embodiment, the heat dissipation adhesive layer 150 may be made of a high thermal conductive material, such as silver paste, copper paste, etc., and can conduct heat generated by the control chip 131 to the outside to dissipate heat.
In this embodiment, the upper surface of the plastic package body 133 is further provided with a heat sink 170, and the heat sink 170 is connected to the heat dissipation adhesive layer 150. The heat sink 170 and the heat dissipation adhesive layer 150 form a T-shaped heat dissipation structure, the heat dissipation structure is composed of the heat sink 170 and the heat dissipation adhesive layer 150 in the adhesive groove, and the heat dissipation adhesive layer 150 plays a role of conducting heat, and conducts heat generated by the control chip 131 to the heat sink 170 and to the outside. Meanwhile, the heat sink 170 can also conduct heat from the surface of the plastic package body 133 to the outside, thereby achieving heat dissipation. The heat sink 170 may be made of ceramic sheet, metal sheet, or other materials capable of dissipating heat.
In this embodiment, the shape of the heat sink 170 is adapted to the shape of the plastic package body 133, and the heat sink is attached to the surface of the plastic package body 133, wherein the bottom side of the heat sink 170 is further coated with a heat sink adhesive, and the heat sink adhesive is adhered to the surface of the plastic package body 133 and the heat sink adhesive layer 150 into a whole, by the arrangement of the heat sink 170, the substrate warpage problem can be solved, that is, the heat sink 170 acts on the surface of the plastic package body 133, the plastic package body 133 is prevented from warping due to warping of the lower medium base layer 110, and the integrity of the product structure is ensured. Moreover, the middle heat dissipation adhesive layer 150 can also effectively solve the problem that the plastic package body 133 deforms under the action of thermal expansion and cold contraction or moisture absorption expansion and directly acts on the control chip 131, at the moment, the heat dissipation adhesive layer 150 plays a role in buffering, the young modulus of the chip is 131000MPa, and the young modulus of the heat dissipation adhesive layer 150 is lower than 3400MPa, so that the heat dissipation adhesive layer 150 is softer and more easily deformed compared with the plastic package body 133, and plays a role in buffering.
In the present embodiment, the heat sink 170 has a planar plate shape, and the surface of the heat dissipation adhesive layer 150 is flush with the upper surface of the plastic package body 133.
In another preferred embodiment of the present invention, referring to fig. 2, the heat sink 170 may also be recessed, that is, the heat dissipation adhesive layer 150 does not fill the groove on the plastic package body 133, and the heat sink 170 is recessed downward at the position of the heat dissipation adhesive layer 150 to form a recessed space, so that on one hand, the thickness of the heat dissipation adhesive layer 150 is reduced, so that heat can reach the heat sink 170 more quickly, and on the other hand, a recessed mark is left on the upper surface of the product, so as to facilitate identification of the front and back sides of the product.
In this embodiment, the heat dissipation adhesive layer 150 has a certain temperature resistance, and specifically, can ensure that it does not deform at any temperature between-65 ℃ and 280 ℃, and the young's modulus is lower than 3400MPa, so as to ensure the structural stability of the product.
In summary, in the chip package structure 100 provided in this embodiment, the plurality of first structure chips 135a are stacked to form a first stacked structure, the control chip 131 is disposed on one side of the first stacked structure, the control chip 131 is electrically connected to the dielectric base layer 110, the plastic package body 133 covers the control chip 131 and the first stacked structure and is attached to the dielectric base layer 110, wherein a first conductive pillar 139a is further disposed in the plastic package body 133, the first conductive pillar 139a is located between the first stacked structure and the control chip 131, a first wiring layer 137a is disposed on an upper side or a lower side of each first structure chip 135a, and the first wiring layer 137a is connected to the first conductive pillar 139 a. Through setting up first electrically conductive post 139a to realize the electric connection between a plurality of structure chips and the medium basic unit 110 through first wiring layer 137a, avoided the routing, increased the pile number of chip simultaneously, guaranteed the stability of structure. In addition, through setting up heat dissipation glue film 150 and fin 170 to form T font heat radiation structure with heat dissipation glue film 150 and fin 170, can effectively solve the warpage problem, heat dissipation glue film 150 can play the cushioning effect simultaneously, and then protects control chip 131, and the most important thing can realize the good heat dissipation of control chip 131 through T font heat radiation structure, and then realizes the heat dissipation of product.
Second embodiment
The present embodiment provides a method for manufacturing a chip package structure 100, for manufacturing the chip package structure 100 provided in the first embodiment, the method includes the following steps:
s1: the carrier 200 is used to prepare the chip molding module 130.
Specifically, the chip plastic package module 130 includes a control chip 131, a plurality of first structure chips 135a and a plastic package body 133, the plurality of first structure chips 135a are stacked and form a first stacked structure attached to the medium base layer 110, the control chip 131 is disposed on one side of the first stacked structure and electrically connected to the medium base layer 110, and the plastic package body 133 is wrapped outside the control chip 131 and the first stacked structure and attached to the medium base layer 110; the plastic package body 133 is further provided with first conductive pillars 139a, the first conductive pillars 139a are located between the first stacked structure and the control chip 131, a first wiring layer 137a is provided on the upper side or the lower side of each first structure chip 135a, and the first wiring layer 137a is connected to the first conductive pillars 139 a. The chip plastic package module 130 may be prepared in advance and then the chip plastic package module 130 is mounted on the medium base layer 110, or the medium base layer 110 is directly formed at the bottom of the chip plastic package module 130. Specifically, the chip plastic package module 130 may be prepared by using the carrier 200, the carrier 200 may be made of glass, silicon oxide, metal, or the like, and the warpage problem during the manufacturing process can be eliminated by preparing the chip plastic package module 130 through the carrier 200.
In this embodiment, step S1 specifically includes the following steps:
s11: the first structural chip 135a and the second structural chip 135b are mounted on the carrier 200.
Referring to fig. 3, specifically, a carrier 200 is provided, and a UV glue layer is coated on the surface of the carrier 200, because the carrier 200 has high strength, the carrier 200 can be used to eliminate the warpage problem during the manufacturing process, and the carrier 200 can be made of glass, silicon oxide, metal, or other materials. The first structural chip 135a and the second structural chip 135b are flip-chip mounted on the carrier 200, specifically, the first conductive bumps 1351 on the first structural chip 135a are attached downward on the UV glue layer of the carrier 200, the second conductive bumps 1353 on the second structural chip 135b are attached downward on the UV glue layer of the carrier 200, and the first conductive bumps 1351 and the second conductive bumps 1353 are spaced apart and a space for mounting the control chip 131 is reserved. Wherein, the material of the UV adhesive layer can be separated by irradiating UV light, thereby playing a role in separation. It may be made of one of, but not limited to, an adhesive paste, epoxy, and polyimide, and is used to apply a separation layer of the subsequently formed die assembly 130 by UV curing or thermal curing.
S12: the first structural chip 135a and the second structural chip 135b are attached again, and an intermediate molding layer is formed.
Referring to fig. 4, specifically, the first structural chip 135a in the second layer is continuously mounted on the first structural chip 135a mounted in step S11, and the second structural chip 135b in the second layer is continuously mounted on the second structural chip 135b, wherein the first conductive bump 1351 on the first structural chip 135a in the upper layer is disposed upward, the second conductive bump 1353 on the second structural chip 135b in the upper layer is disposed upward, the first structural chip 135a in the second layer is mounted on the back surface of the first structural chip through the first adhesive film layer, and the second structural chip 135b in the second layer is mounted on the back surface of the first structural chip through the second adhesive film layer. And then printing a liquid plastic package material, solidifying the plastic package material, carrying out the attached structural plastic package protection, and grinding the plastic package material by using a grinding process again to leak the first structural chip 135a and the second structural chip 135b on the second layer to form a middle plastic package layer so that the first conductive bump 1351 and the second conductive bump 1353 on the upper side are exposed. The molding compound may be epoxy resin or silicon oxide.
S13: a first wiring layer 137a and a second wiring layer 137b are formed on the intermediate plastic package layer, and after the grooves are filled, a first conductive pillar 139a, a second conductive pillar 139b and a third conductive pillar 139c are formed.
Referring to fig. 5, specifically, after exposing and developing the wiring pattern on the ground intermediate molding layer, a first wiring layer 137a and a second wiring layer 137b are formed, wherein the first wiring layer 137a is connected to the first conductive bump 1351 on the first structural chip 135a, and the second wiring layer 137b is connected to the second conductive bump 1353 on the second structural chip 135 b. Then, a laser hole opening mode is used for opening holes at the edges and the middle parts of the first wiring layer 137a and the second wiring layer 137b to the bottom of the middle plastic package layer until reaching the lower UV glue layer, then conductive glue is filled, and a first conductive pillar 139a, a second conductive pillar 139b and a third conductive pillar 139c are formed through baking and curing, wherein the number of the third conductive pillars 139c is two, and conductive glue materials can be conductive silver glue, conductive paste or conductive copper materials, and the like, so that the conductive characteristic requirements need to be met.
S14: and mounting the control chip 131, and mounting the first structural chip 135a and the second structural chip 135b again to form an intermediate plastic package layer.
Referring to fig. 6, specifically, the first structural chip 135a is mounted on the first structural chip 135a again, the second structural chip 135b is mounted on the second structural chip 135b again, the first conductive bump 1351 of the first structural chip 135a and the second conductive bump 1353 of the second structural chip 135b are mounted upward, the control chip 131 is mounted between the first structural chip 135a and the second structural chip 135b, and the control conductive bump 1311 of the control chip 131 is mounted downward and connected to the third conductive pillar 139 c. Then, a liquid plastic package material is printed, the mounted structure is protected by plastic package through curing the plastic package material, and the first structure chip 135a, the second structure chip 135b and the control chip 131 are exposed by using the mask process again.
S15: a first wiring layer 137a and a second wiring layer 137b are formed on the intermediate plastic package layer, and after the grooves are filled, first conductive pillars 139a and second conductive pillars 139b are formed.
Referring to fig. 7, referring to step S13 in particular, after exposing and developing the circuit pattern on the ground intermediate molding layer, a first wiring layer 137a and a second wiring layer 137b are formed, wherein the first wiring layer 137a is connected to the first conductive bump 1351 on the first structural chip 135a, and the second wiring layer 137b is connected to the second conductive bump 1353 on the second structural chip 135 b. Then, the edges of the first wiring layer 137a and the second wiring layer 137b are opened to the lower first conductive pillars 139a and the lower second conductive pillars 139b by using a laser opening method, and then the conductive paste is filled in the holes, and the first conductive pillars 139a and the second conductive pillars 139b of the second layer are formed by baking and curing.
Repeatedly mounting the first structure chip 135a and the second structure chip 135b, and repeatedly forming the first conductive pillar 139a and the second conductive pillar 139b until the last layer of the first structure chip 135a, the second structure chip 135b, the first conductive pillar 139a, and the second conductive pillar 139b is molded, and then the mounted structure is molded by using a printing liquid molding compound to form the molding body 133.
S16: the molding compound 133 is formed with a heat dissipation layer 150 and is attached with a heat sink 170.
Referring to fig. 8, specifically, after the plastic package body 133 is formed, the laser grooving process is used again to remove the plastic package body 133 above the control chip 131 to form a glue groove, wherein the control chip 131 is exposed out of the bottom wall of the glue groove, then the glue groove is filled with heat dissipation glue, meanwhile, the heat dissipation fin 170 is attached to the upper surface of the plastic package body 133, the heat dissipation glue at the bottom of the heat dissipation fin 170 is used to realize adhesion, and the structure of the heat dissipation fin 170 and the heat dissipation glue layer 150 is realized after curing to form a T-shaped heat dissipation structure, so that the heat dissipation effect on the control chip 131 is improved. By forming the T-shaped heat dissipation structure, a supporting effect and a heat dissipation effect can be achieved, wherein the heat dissipation fins 170 can be made of ceramic plates, metal plates and the like to achieve the heat dissipation effect and the supporting effect, the heat dissipation glue can be made of high-heat-conductivity silver glue, high-heat-conductivity copper paste and the like, and finally characters are printed on the heat dissipation fins 170 again.
S17: the carrier 200 is separated and the chip molding module 130 is formed.
Referring to fig. 9, specifically, the UV glue layer is removed by means of UV light irradiation, so that the plastic package body 133 is separated from the carrier 200, the first conductive bump 1351 on the first structural chip 135a at the bottom and the second conductive bump 1353 on the second structural chip 135b are exposed, the first wiring layer 137a connected to the first conductive bump 1351 is formed on the bottom side of the first structural chip 135a, the second wiring layer 137b connected to the second conductive bump 1353 is formed on the bottom side of the second structural chip 135b, and the first wiring layer 137a and the second wiring layer 137b extend to the bottoms of the first conductive pillar 139a and the second conductive pillar 139b, respectively, so as to achieve electrical connection.
After the chip mold package module 130 is formed, step S2 is performed, so as to obtain a final product.
S2: a dielectric substrate 110 is formed on the bottom side of the die encapsulation module 130.
With reference to fig. 1, after separating the carrier 200 and wiring the bottom side of the first structural chip 135a and the bottom side of the second structural chip 135b, the bottom side of the plastic package body 133 is filled with a dielectric layer, and the dielectric layer 110 is formed after curing, so that the bottom surface of the product is flat, wherein the dielectric layer may be epoxy resin, silicon oxide, or the like. After the dielectric base layer 110 is formed, the ball-planting process is used to plant balls on the bottom side of the dielectric base layer 110, and then the cutting process is used to cut the product into single pieces, thereby completing the preparation of the chip package structure 100.
In the method for manufacturing the chip package structure 100 according to the embodiment of the invention, the plurality of first structure chips 135a are stacked to form a first stacked structure, the control chip 131 is disposed on one side of the first stacked structure, the control chip 131 is electrically connected to the dielectric base layer 110, the plastic package body 133 covers the control chip 131 and the first stacked structure and is attached to the dielectric base layer 110, wherein the plastic package body 133 is further provided with a first conductive pillar 139a, the first conductive pillar 139a is located between the first stacked structure and the control chip 131, the upper side or the lower side of each first structure chip 135a is provided with a first wiring layer 137a, and the first wiring layer 137a is connected to the first conductive pillar 139 a. Through setting up first electrically conductive post 139a to realize the electric connection between a plurality of structure chips and the medium basic unit 110 through first wiring layer 137a, avoided the routing, increased the pile number of chip simultaneously, guaranteed the stability of structure. In addition, through setting up heat dissipation glue film 150 and fin 170 to form T font heat radiation structure with heat dissipation glue film 150 and fin 170, can effectively solve the warpage problem, heat dissipation glue film 150 can play the cushioning effect simultaneously, and then protects control chip 131, and the most important thing can realize the good heat dissipation of control chip 131 through T font heat radiation structure, and then realizes the heat dissipation of product.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. A chip package structure, comprising:
a dielectric base layer;
the chip plastic package module is arranged on the medium base layer and comprises a control chip, a plastic package body and a plurality of first structure chips, the first structure chips are stacked to form a first stacked structure attached to the medium base layer, the control chip is arranged on one side of the first stacked structure and is electrically connected with the medium base layer, and the plastic package body wraps the control chip and the first stacked structure and is attached to the medium base layer;
the plastic package is internally provided with a first conductive column, the first conductive column is located between the first laminated structure and the control chip, a first wiring layer is arranged on the upper side or the lower side of each first structure chip, and the first wiring layer is connected with the first conductive column.
2. The chip package structure according to claim 1, wherein a first conductive bump is disposed on an upper side or a lower side of each of the first structural chips, and the first wiring layer is connected to the first conductive bump.
3. The chip package structure according to claim 1, wherein the chip plastic package module further includes a plurality of second structure chips, the plurality of second structure chips are stacked and form a second stacked structure attached to the medium base layer, the control chip is disposed between the first stacked structure and the second stacked structure, the second stacked structure is encapsulated in the plastic package body, and a second conductive pillar is further disposed in the plastic package body, the second conductive pillar is located between the second stacked structure and the control chip, a second wiring layer is disposed on an upper side or a lower side of each of the second structure chips, and the second wiring layer is connected to the second conductive pillar.
4. The chip package structure according to claim 3, wherein a second conductive bump is disposed on an upper side or a lower side of each of the second structural chips, and the second wiring layer is connected to the second conductive bump.
5. The chip package structure according to claim 3, wherein a control conductive bump is disposed on an underside of the control chip, and the control conductive bump is connected to the adjacent first and second wiring layers.
6. The chip package structure according to claim 3 or 5, wherein a third conductive pillar is further disposed on the lower side of the control chip, the third conductive pillar extends to the dielectric base layer, and the control chip is electrically connected to the dielectric base layer through the third conductive pillar.
7. The chip package structure according to claim 6, wherein a first land, a second land and a third land are disposed on the dielectric base layer, the first conductive pillar is connected to the first land, the second conductive pillar is connected to the second land, and the third conductive pillar is connected to the third land.
8. The chip package structure according to claim 1, wherein a heat dissipation adhesive layer is further disposed on the upper side of the control chip, and the heat dissipation adhesive layer penetrates through to the upper surface of the plastic package body.
9. The chip package structure according to claim 8, wherein a heat sink is further disposed on the upper surface of the plastic package body, and the heat sink is connected to the heat dissipation adhesive layer.
10. A method for manufacturing a chip package structure according to claim 1, comprising:
preparing a chip plastic package module by using a carrier;
forming a medium base layer on the bottom side of the chip plastic package module;
the chip plastic package module comprises a control chip, a plurality of first structure chips and a plastic package body, wherein the first structure chips are stacked to form a first stacked structure attached to the medium base layer, the control chip is arranged on one side of the first stacked structure and is electrically connected with the medium base layer, and the plastic package body wraps the control chip and the first stacked structure and is attached to the medium base layer; still be provided with first conductive pillar in the plastic packaging body, first conductive pillar is located first laminated structure with between the control chip, every the upside or the downside of first structure chip are provided with first wiring layer, first wiring layer with first conductive pillar is connected.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449590A (en) * | 2016-11-08 | 2017-02-22 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor storage module and production method thereof |
| CN106653628A (en) * | 2016-11-08 | 2017-05-10 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor memory and manufacturing method thereof |
| CN108074912A (en) * | 2016-11-17 | 2018-05-25 | 爱思开海力士有限公司 | Semiconductor packages including connectors |
| CN112366138A (en) * | 2020-11-11 | 2021-02-12 | 济南南知信息科技有限公司 | Storage chip packaging structure and preparation method thereof |
-
2021
- 2021-04-15 CN CN202110407586.3A patent/CN112992888A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106449590A (en) * | 2016-11-08 | 2017-02-22 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor storage module and production method thereof |
| CN106653628A (en) * | 2016-11-08 | 2017-05-10 | 华进半导体封装先导技术研发中心有限公司 | Semiconductor memory and manufacturing method thereof |
| CN108074912A (en) * | 2016-11-17 | 2018-05-25 | 爱思开海力士有限公司 | Semiconductor packages including connectors |
| CN112366138A (en) * | 2020-11-11 | 2021-02-12 | 济南南知信息科技有限公司 | Storage chip packaging structure and preparation method thereof |
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