CN114121140B - Chip testing method, system, electronic device and storage medium - Google Patents
Chip testing method, system, electronic device and storage medium Download PDFInfo
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- CN114121140B CN114121140B CN202210104044.3A CN202210104044A CN114121140B CN 114121140 B CN114121140 B CN 114121140B CN 202210104044 A CN202210104044 A CN 202210104044A CN 114121140 B CN114121140 B CN 114121140B
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Abstract
The application provides a chip testing method, a chip testing system, electronic equipment and a storage medium, and relates to the technical field of integrated circuit testing. The method comprises the following steps: calibrating the initial converter to obtain a target converter, wherein the initial converter and the target converter are both analog-digital converters; calibrating voltage data in a voltage channel of the test chip based on the target converter to obtain calibrated voltage data; and calibrating the current data in the current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data. The converter after calibration can be adopted to carry out high-precision and high-efficiency calibration on the voltage data and the current data obtained by testing when the chip is tested, an independent calibration plate and a test instrument are not required to be manufactured to test and calibrate the chip, the operation time during calibration is reduced, a plurality of different channels can be tested and calibrated simultaneously, and the efficiency and the precision of testing and calibrating the chip are effectively improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit testing technologies, and in particular, to a chip testing method, a chip testing system, an electronic device, and a storage medium.
Background
Due to the improvement of the capacity, speed and other performances of various memory chips, the test performance of the memory chip test equipment for testing various memory chips is very important. The memory chip testing device is a system capable of automatically realizing the memory chip testing. The test is mainly divided into direct current parameter test, alternating current parameter measurement, function test and the like, and the direct current parameter is an important index for representing the performance of the chip.
The existing testing equipment basically adopts PMU (Precision Measurement Unit) to perform two main modes: and measuring the direct current parameters by applying current and measuring pressure and applying current. The method is characterized in that an independent calibration plate is generally required to be installed in a precision measurement unit and is tested through a test instrument, the independent calibration plate is required to be manufactured to calibrate the precision during testing, the operation is complex during calibration, multiple site tests are generally adopted due to more test items, more channels of a storage test system are used during testing, but at present, only one channel can be used for testing at each time, the testing flow is complex, the testing time is longer, and the chip testing efficiency is lower.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a chip testing method, a chip testing system, an electronic device, and a storage medium, so as to solve the problem of low chip testing efficiency in the prior art.
In a first aspect, the present application provides a chip testing method, including:
calibrating an initial converter to obtain a target converter, wherein the initial converter and the target converter are analog-digital converters;
calibrating voltage data in a voltage channel of the test chip based on the target converter to obtain calibrated voltage data;
calibrating current data in a current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data, wherein the current data comprises test current data and applied current data of the test chip, and the current channel comprises a first current channel and a second current channel; the calibrating the current data in the current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data includes: calibrating the test current data in the first current channel based on the target converter and calibration applied voltage data in the calibration voltage data to obtain calibration test current data; calibrating the applied current data in the second current channel based on the target converter to obtain calibrated applied current data, and taking the calibration test current data and the calibration applied current data as the calibration current data.
In the above implementation, the voltage data and the current data of the test chips in the plurality of channels are tested and calibrated by using the converter instead of the calibration board and the test meter. In order to improve the accuracy of the converter during calibration, the initial converter is calibrated to obtain a target converter with higher accuracy, so as to test and calibrate the voltage data in the voltage channel of the test chip through the target converter to obtain corresponding calibration voltage data, and the current data in the current channel of the test chip is tested and calibrated through the target converter and the calibrated voltage data, because the current data comprise the test current data and the applied current data, the two types of current data can be tested and calibrated from different current channels respectively, and two types of current modes of the test current and the applied current can be tested and calibrated respectively, so that the effectiveness and the precision of the calibrated current data obtained by calibration are improved, and the efficiency of testing and calibrating the current data in the chip test is improved. Through the mode of in-board calibration, need not to make solitary calibration board and test instrument and test and calibrate the chip, reduced the operating time and the complexity of operation flow when calibrating, can also test and calibrate a plurality of different passageways simultaneously, improved efficiency and the precision of testing and calibrating the chip effectively.
Optionally, the calibrating the initial converter to obtain the target converter includes:
obtaining calibration parameters according to the voltage parameters input into the initial converter, wherein the calibration parameters comprise calibration offset parameters and calibration slope parameters;
and calibrating the initial converter based on the calibration parameters to obtain the target converter.
In the implementation manner, in order to improve the accuracy of the initial converter, calibration parameters such as a calibration offset parameter and a calibration slope parameter can be calculated according to various voltage parameters input into the initial converter, and the calibration parameters are substituted into the initial converter for calibration calculation to obtain a calibrated target converter, so that the accuracy of the converter is improved, the error during calibration is reduced, and the accuracy of data calibration during chip testing is improved.
Optionally, the calibrating the test current data in the first current channel based on the target converter and calibration applied voltage data in the calibration voltage data to obtain calibration test current data includes:
setting a test current mode according to the first current channel corresponding to the obtained test current data so as to control switches of a plurality of channels and determine a first target channel corresponding to the target converter;
determining a corresponding first target resistance based on the test range;
setting a preset applied voltage value in the first target channel based on the applied voltage parameter corresponding to the calibration applied voltage data;
determining a protocol port current value in the target converter based on the preset applied voltage value and the first target resistance;
acquiring a target test current value corresponding to the protocol port current value in the target converter;
calculating based on the protocol port current value and the target test current value to obtain test current parameters, wherein the test current parameters comprise a test current slope parameter and a test current offset parameter;
and calculating according to the test current parameters and the test current data to obtain the calibration test current data.
In the implementation manner, the target converter can test the test current in the test chip, obtain corresponding test current data, select the corresponding first current channel, set the test current mode to control the switches of the multiple serial channels, and determine the corresponding first target channel when the target converter is calibrated. The method comprises the steps of applying pressure to a first target channel through an applied voltage parameter corresponding to calibration applied voltage data, setting a corresponding preset applied voltage value in a protocol port of a target converter, determining a protocol port current value in the target converter according to the preset applied voltage value and a determined first target resistor, and acquiring a target test current value of an acquisition port obtained by actual measurement in the target converter. The corresponding test current parameter is obtained by calculating the protocol port current value and the target test current value, the test current data is calibrated according to the test current slope parameter and the test current offset parameter in the test current parameter, the calibration test current data is obtained, the test current data can be calibrated quickly and accurately during current testing, and the calibration efficiency and precision are improved.
Optionally, the calibrating the applied current data in the second current channel based on the target converter to obtain calibrated applied current data includes:
setting an applied current mode according to the second current channel corresponding to the obtained applied current data so as to control switches of a plurality of channels and determine a second target channel corresponding to the target converter;
determining a corresponding second target resistance based on the test range;
setting a preset applied current value in the second target channel;
determining a target applied current value based on the port voltage value in the target converter and the second target resistance;
calculating based on the preset applied current value and the target applied current value to obtain applied current parameters, wherein the applied current parameters comprise an applied current slope parameter and an applied current offset parameter;
and calculating according to the applied current parameter and the applied current data to obtain the calibration applied current data.
In the implementation manner, the target converter can test the applied current in the test chip, acquire corresponding applied current data, select a corresponding second current channel, set an applied current mode to control switches of a plurality of serial channels, and determine a corresponding second target channel when the target converter is calibrated. And setting a corresponding port voltage value and a preset applied current value in the protocol port of the target converter by applying pressure and current to the second target channel, and determining the target applied current value in the protocol port of the target converter according to the port voltage value and the determined second target resistance. The corresponding applied current parameter is obtained by calculating the preset applied current value and the target applied current value, the applied current data is calibrated according to the applied current slope parameter and the applied current offset parameter in the applied current parameter to obtain calibrated applied current data, the applied current data can be calibrated quickly and accurately when current is applied, and the calibration efficiency and precision are improved.
Optionally, the voltage data includes applied voltage data and test voltage data of the test chip, and the voltage channels include a first voltage channel and a second voltage channel; the calibrating the voltage data in the voltage channel of the test chip based on the target converter to obtain the calibrated voltage data comprises the following steps:
calibrating the applied voltage data in the first voltage channel based on the target converter to obtain calibrated applied voltage data;
calibrating the test voltage data in the second voltage channel based on the target converter to obtain calibration test voltage data, and taking the calibration applied voltage data and the calibration test voltage data as the calibration voltage data.
In the above implementation, the voltage data includes test voltage data and applied voltage data, and the two kinds of voltage data can be respectively tested and calibrated from different voltage channels. The applied voltage data in the first voltage channel is calibrated through the target converter, the test voltage data in the second voltage channel is calibrated through the target converter, calibration voltage data consisting of the corresponding calibration applied voltage data and the calibration test voltage data are obtained respectively, two voltage modes of the applied voltage and the test voltage can be tested and calibrated respectively, the effectiveness and the precision of the calibration voltage data obtained through calibration are improved, and the efficiency of testing and calibrating the voltage data in chip testing is improved.
Optionally, the calibrating the applied voltage data in the first voltage channel based on the target converter to obtain calibrated applied voltage data includes:
setting an applied voltage mode according to the first voltage channel corresponding to the acquired applied voltage data so as to control switches of a plurality of channels and determine a third target channel corresponding to the target converter;
setting a preset applied voltage value in the third target channel, and acquiring a target applied voltage value in the target converter;
calculating based on the preset applied voltage value and the target applied voltage value to obtain applied voltage parameters, wherein the applied voltage parameters comprise an applied voltage slope parameter and an applied voltage offset parameter;
and calculating according to the applied voltage parameters and the applied voltage data to obtain the calibration applied voltage data.
In the implementation manner, the target converter can test the applied voltage in the test chip, acquire corresponding applied voltage data, select the corresponding first voltage channel, set the applied voltage mode to control the switches of the multiple serial channels, and determine the corresponding third target channel when the target converter is calibrated. And the third target channel is pressurized, and a corresponding preset applied voltage value is set, so that the target applied voltage value can be acquired in a protocol port of the target converter. The corresponding applied voltage parameter is obtained by calculating the preset applied voltage value and the target applied voltage value, the applied voltage data is calibrated according to the applied voltage slope parameter and the applied voltage offset parameter in the applied voltage parameter, the calibrated applied voltage data is obtained, the applied voltage data can be calibrated quickly and accurately when the voltage is applied, and the calibration efficiency and precision are improved.
Optionally, the calibrating the test voltage data in the second voltage channel based on the target converter to obtain calibrated test voltage data includes:
setting a test voltage mode according to the second voltage channel corresponding to the obtained test voltage data so as to control switches of a plurality of channels and determine a fourth target channel corresponding to the target converter;
setting the preset applied voltage value in the fourth target channel based on the applied voltage parameter, and acquiring a test voltage value in the target converter;
calculating based on the preset applied voltage value and the test voltage value to obtain a test voltage parameter, wherein the test voltage parameter comprises a test voltage slope parameter and a test voltage offset parameter;
and calculating according to the test voltage parameters and the test voltage data to obtain the calibration test voltage data.
In the implementation manner, the target converter can test the test voltage in the test chip, obtain corresponding test voltage data, select the corresponding second voltage channel, set the test voltage mode to control the switches of the multiple serial channels, and determine the corresponding fourth target channel when the target converter performs calibration. And applying pressure to the fourth target channel by calibrating the applied voltage parameters corresponding to the applied voltage data, setting the corresponding preset applied voltage value, and acquiring to obtain the test voltage value in the acquisition port in the target converter. The corresponding test voltage parameters are obtained by calculating the preset applied voltage value and the test voltage value, the test voltage data are calibrated according to the test voltage slope parameters and the test voltage offset parameters in the test voltage parameters, calibration test voltage data are obtained, the test voltage data can be calibrated quickly and accurately during voltage testing, and calibration efficiency and precision are improved.
In a second aspect, the present application further provides a chip testing system, where the system includes a plurality of calibration modules and a plurality of test boards, and each calibration module is disposed in a corresponding test board, so as to calibrate a plurality of channels of a test chip simultaneously through the calibration module;
the calibration module also comprises a converter calibration submodule, a voltage calibration submodule and a current calibration submodule;
the converter calibration submodule is used for calibrating an initial converter to obtain a target converter, and the initial converter and the target converter are analog-digital converters;
the voltage calibration submodule is used for calibrating voltage data in a voltage channel of the test chip based on the target converter to obtain calibration voltage data;
the current calibration submodule is used for calibrating current data in a current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data, wherein the current data comprise test current data and applied current data of the test chip, and the current channel comprises a first current channel and a second current channel; the current calibration submodule is further configured to: calibrating the test current data in the first current channel based on the target converter and calibration applied voltage data in the calibration voltage data to obtain calibration test current data; calibrating the applied current data in the second current channel based on the target converter to obtain calibrated applied current data, and taking the calibration test current data and the calibration applied current data as the calibration current data.
In the implementation mode, the initial converter is calibrated through the converter calibration submodule, and a target converter with higher precision can be obtained. And testing and calibrating the voltage data in the voltage channel of the test chip by the voltage calibration submodule based on the target converter, so as to obtain corresponding calibration voltage data. And testing and calibrating the current data in the current channel of the test chip by the current calibration submodule based on the target converter and the calibrated calibration voltage data. The converter is used for replacing a calibration board and a test instrument to test and calibrate voltage data and current data of a test chip in a plurality of channels, and through the mode of in-board calibration, the independent calibration board and the test instrument do not need to be manufactured to test and calibrate the chip, so that the operation time and the complexity of an operation flow during calibration are reduced, a plurality of different channels can be tested and calibrated simultaneously, and the efficiency and the precision of testing and calibrating the chip are effectively improved.
In a third aspect, the present application further provides an electronic device, where the electronic device includes a memory and a processor, where the memory stores program instructions, and the processor executes steps in any implementation manner of the chip testing method when reading and executing the program instructions.
In a fourth aspect, the present application further provides a computer-readable storage medium, where computer program instructions are stored, and when the computer program instructions are read and executed by a processor, the steps in any implementation manner of the chip testing method are executed.
In summary, the present application provides a chip testing method, system, electronic device and storage medium, which can set a calibration system in a testing board to simultaneously test and calibrate different channels of a testing chip, and does not need to manufacture a separate calibration board and a separate testing instrument to test and calibrate the chip, thereby effectively improving the efficiency and precision of testing and calibrating the chip.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a chip testing system according to an embodiment of the present disclosure;
fig. 2 is a schematic flowchart of a chip testing method according to an embodiment of the present disclosure;
fig. 3 is a detailed flowchart of a step S400 provided in an embodiment of the present application;
fig. 4 is a detailed flowchart of a step S600 according to an embodiment of the present disclosure;
fig. 5 is a detailed flowchart of step S610 according to an embodiment of the present disclosure;
fig. 6 is a detailed flowchart of step S620 according to an embodiment of the present disclosure;
fig. 7 is a detailed flowchart of a step S500 according to an embodiment of the present disclosure;
fig. 8 is a detailed flowchart of step S510 according to an embodiment of the present disclosure;
fig. 9 is a schematic detailed flowchart of step S520 according to an embodiment of the present disclosure.
Icon: 100-a calibration module; 110-converter calibration sub-module; 111-target converter; 112-an acquisition port; 113-protocol ports; 120-a voltage calibration submodule; 130-a current calibration submodule; 200-a test board; 300-testing the chip; 310-a precision measurement unit; 320-a test channel; 330-output measurement port; 340-a first multiplexer component; 341-a second multiplexer component; 350-precision resistance load; 360-a relay assembly; 370-precision resistor; 380-force interface; 390-detection interface.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of them. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present application without any creative effort belong to the protection scope of the embodiments of the present application.
In the existing chip testing method, when calibrating data of a chip, a calibration board and a test instrument are generally used to test and calibrate a precision unit of the chip, all channels in the precision unit used in testing the chip are individually selected by the calibration board to apply excitation and measure in a single channel, measurement is performed by a test instrument such as a desk multimeter, applied precision is calibrated by applying excitation and test instrument measurement result calculation, and measurement precision of the precision unit is calibrated by precision unit measurement result and test instrument result calculation.
However, when the above method is used for measurement and calibration, a separate calibration board needs to be manufactured and mounted, an instrument needs to be connected, a probe card needs to be detached when a wafer is tested on a chip, and due to the change of a test environment, the precision of a precision unit changes, so that a tester regularly performs self-inspection, and the mounting operation is repeated every self-inspection operation, which results in complicated calibration operation and long operation time. And only one channel of the test chip can be tested each time, so that the whole test time is longer, and the efficiency of testing the chips with more channels is lower.
Therefore, in order to solve the above-mentioned problems, an embodiment of the present application provides a chip testing system, please refer to fig. 1, and fig. 1 is a schematic structural diagram of the chip testing system provided in the embodiment of the present application, the chip testing system may include a plurality of calibration modules 100 and a plurality of testing boards 200 (only one of the calibration modules is shown in the figure, which is not shown), each calibration module 100 is disposed in a corresponding testing board 200, and the testing board 200 may be a digital channel board of multiple types and different models. The test board 200 is connected to a test chip 300 under test to simultaneously calibrate a plurality of channels of the test chip through the calibration module 100.
The calibration module 100 further includes a converter calibration sub-module 110, a voltage calibration sub-module 120, and a current calibration sub-module 130;
the converter calibration sub-module 110 is configured to calibrate the initial converter to obtain a target converter, where the initial converter and the target converter are analog-to-digital converters;
the voltage calibration submodule 120 is configured to calibrate voltage data in a voltage channel of the test chip based on the target converter to obtain calibrated voltage data;
the current calibration submodule 130 is configured to calibrate current data in a current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data, where the current data includes test current data and applied current data of the test chip 300, and the current channel includes a first current channel and a second current channel; a current calibration submodule 130 further configured to: calibrating the test current data in the first current channel based on the calibration applied voltage data in the target converter and the calibration voltage data to obtain calibration test current data; and calibrating the applied current data in the second current channel based on the target converter to obtain calibration applied current data, and taking the calibration test current data and the calibration applied current data as calibration current data.
Optionally, the transducer calibration sub-module 110 may further include a target transducer 111, the test board 200 may further include a Precision Measurement Unit 310, and the Precision Measurement Unit 310 may be a multiple PMU (Precision Measurement Unit). The precision measurement unit 310 is connected to a plurality of test channels 320 (only 4 are shown, and the other numbers are not shown) in the test chip 300 to test the test chip 300. A plurality of output measurement ports 330 (only 4 are shown in the figure, and the other numbers are not shown) may also be included in the test chip 300, and each test channel 320 is connected to the first multiplexer assembly 340 through the corresponding output measurement port 330. The test board 200 may further include a second multiplexer component 341 for collecting a plurality of chips, the second multiplexer component 341 is connected to the first multiplexer component 340 and the collection port 112 on the target converter 111, and the second multiplexer component 341 and the plurality of test channels 320 may be connected through the first multiplexer component 340; the plurality of test channels 320 and the second multiplexer module 341 may also be directly connected through the output measurement port 330, so as to connect the plurality of test channels 320 and the collection port 112 on the target converter 111 through the second multiplexer module 341, and the calibration module 100 and the plurality of test chips 300 can be connected, so as to respectively measure and calibrate the voltage data and the current data in the plurality of test chips 300 through the test board 200 and the calibration module 100. By connecting the calibration module 100 in the test board 200 with the test chip 300, different test channels 320 in the test chip 300 can be calibrated simultaneously without separately installing and mounting a calibration board and a test meter.
Optionally, a precision resistor load 350 may be further included in the test board 200, and the precision resistor load 350 includes a relay assembly 360 and a plurality of precision resistors 370 (only 4 are shown, and the other numbers are not shown). The number and size of the precision resistors 370 can be determined according to the measurement range of the precision measurement unit 310, and the relay assembly 360 can be controlled to switch to different precision resistors 370 when different measurement ranges are calibrated. The precision measurement unit 310 can be connected with the precision resistive load 350 through the force interface 380 and the detection interface 390, the protocol port 113 of the target converter 111 is also connected with the detection interface 390, and can be isolated from external output during testing, so as to perform testing without influencing normal operation, and when a plurality of test channels 320 in the test chip 300 are measured and calibrated, the precision measurement unit 310 can be connected through a serial switch shared in the test channels 320, so as to control whether the test channels 320 output or not, and reduce the control part of the relay assembly 360.
Based on the chip testing system, the testing chips can be tested simultaneously in multiple channels, and the chip testing method specifically refers to fig. 2, where fig. 2 is a schematic flow diagram of a chip testing method provided in an embodiment of the present application, and the method may include steps S400 to S600.
And step S400, calibrating the initial converter to obtain a target converter.
In order To improve the precision of the Converter, the initial Converter may be an Analog To Digital Converter (ADC) of any model, such as 18-bit ADC, 24-bit ADC, etc., and may convert an Analog signal during testing into a corresponding Digital signal, and the target Converter may be a corresponding Analog To Digital Converter with higher parameter precision after calibrating the initial Converter belonging To the Analog To Digital Converter.
Step S500, calibrating the voltage data in the voltage channel of the test chip based on the target converter to obtain calibration voltage data.
The calibrated target converter can simultaneously test and calibrate a plurality of test channels of the test chip. The voltage data obtained by testing in the voltage channel in the test chip can be calibrated to obtain calibrated voltage data.
Step S600, calibrating the current data in the current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data.
After the voltage data is calibrated, the current data in the current channel of the test chip can be calibrated through the target converter and the calibrated voltage data obtained through calibration, and calibrated calibration current data are obtained.
It should be noted that, since the calibration gain data such as calibration voltage data and calibration current data of various parameters and the offset register may be stored in the precision measurement unit, after the test channel of the test chip is tested and calibrated, the calibration gain data such as calibration voltage data and calibration current data may be stored in the memory chip on the test board, when the test is performed, the test board may directly read the calibration gain data stored in the memory chip, and according to the SPI instruction, the calibration gain data may be sent to the corresponding precision measurement unit according to different addresses and different data, and then sent to the corresponding calibration register, so that when the precision measurement unit operates, the calibration gain data may be automatically substituted into the calculation for calibration.
In the embodiment shown in fig. 2, by means of in-board calibration, it is not necessary to manufacture separate calibration boards and test instruments to test and calibrate the chip, so that the operation time and the complexity of the operation flow during calibration are reduced, a plurality of different channels can be tested and calibrated at the same time, and the efficiency and the accuracy of testing and calibrating the chip are effectively improved.
Optionally, referring to fig. 3, fig. 3 is a detailed flowchart of step S400 provided in the present embodiment, and step S400 may further include steps S410 to S420.
Step S410, obtaining a calibration parameter according to the voltage parameter input to the initial converter.
Wherein the calibration parameters include a calibration offset parameter and a calibration slope parameter. When the parameters of the initial converter are calibrated, the initial converter is a linear device, so that the input voltage data can be selected, keywords of the input voltage data are screened out to be used as the voltage parameters, and the corresponding calibration parameters are calculated according to the voltage parameters and the initial parameters in the initial converter.
It should be noted that the voltage parameters may include a ground voltage parameter and a set voltage parameter, and when the target converter selects the set voltage parameter, the set voltage parameter may be set according to a reference voltage during testing, for example, when the reference voltage is 3V, the ground voltage parameter and the set voltage parameter may be respectively denoted as GND _ REF and 3V _ REF, and the set voltage parameter may be set and adjusted according to a change of the reference voltage.
Alternatively, the calibration offset parameter can be calculated from the input ground voltage parameter in combination with the initial ground voltage parameter in the initial converter, and the calibration slope parameter can be calculated from the input set voltage parameter in combination with the initial set parameter in the initial converter.
Step S420, calibrating the initial converter based on the calibration parameter to obtain the target converter.
The calibration offset parameter and the calibration slope parameter obtained by calibration calculation are substituted into calculation software to carry out calibration calculation, so that the parameter of the initial converter can be calibrated, and the target converter with higher parameter precision is obtained.
In the embodiment shown in fig. 3, the accuracy of the converter can be improved, the error size during calibration can be reduced, and the accuracy of data calibration during chip testing can be improved.
Optionally, referring to fig. 4, fig. 4 is a detailed flowchart of step S600 provided in the present embodiment, and step S600 may further include steps S610-S620.
Step S610, calibrating the test current data in the first current channel based on the calibration applied voltage data in the calibration voltage data and the target converter to obtain calibration test current data.
The current data may include test current data and applied current data of the test chip, and the current channel may include a first current channel and a second current channel of a plurality of test channels of the test chip. When the test chip is subjected to current testing, the voltage data of the test chip can be calibrated, and when the test chip is subjected to current testing, the target converter is used for calibrating the test current data in the first current channel according to the calibration applied voltage data in the calibration voltage data to obtain calibration test current data.
Step S620, calibrating the applied current data in the second current channel based on the target converter, to obtain calibrated applied current data.
When the current is applied to the test chip, the applied current data in the second current channel is calibrated through the target converter to obtain calibration applied current data, and the calibration test current data and the calibration applied current data are taken as calibration current data.
Optionally, when the first current channel and the second current channel of the test chip are tested, the test and calibration sequence may be changed, the first current channel may be tested and calibrated first, then the second current channel may be tested and calibrated, or the second current channel may be tested and calibrated first, and then the first current channel may be tested and calibrated.
In the embodiment shown in fig. 4, two current modes of the test current and the applied current can be respectively tested and calibrated, so that the validity and the precision of the calibrated current data obtained by calibration are improved, and the efficiency of testing and calibrating the current data in the chip test is improved.
Optionally, referring to fig. 5, fig. 5 is a detailed flowchart of step S610 provided in the embodiment of the present application, and step S610 may further include steps S611 to S617.
Step S611, setting a test current mode according to the first current channel corresponding to the obtained test current data, so as to control switches of multiple channels, and determine a first target channel corresponding to the target converter.
The method comprises the steps of using a test channel in a plurality of test channels of a test chip to test and obtain test current data in the test chip as a first current channel, setting a test current mode under the condition of applying voltage, controlling switches of the plurality of test channels in the test chip through serial connection, controlling the switches of the first current channel to be closed, and controlling the switches of other test channels to be opened, and determining a first target channel for collection when a target converter is connected with a multiplexer of a precision measurement unit.
Step S612, determining a corresponding first target resistance based on the test range.
According to the test range of the precision measurement unit, the corresponding relay can be controlled to be conducted, so that the corresponding first target resistor r0 is selected, and the first target resistor r0 can be precision resistors of various types and sizes.
Step S613, setting a preset applied voltage value in the first target channel based on the applied voltage parameter corresponding to the calibration applied voltage data.
And substituting the applied voltage parameters corresponding to the calibration applied voltage data into the test current mode for calculation to obtain corresponding preset applied voltage values v0 and v1, and setting preset applied voltage values v0 and v1 on the protocol port of the target converter for pressurization in the first target channel.
Step S614, determining a protocol port current value in the target converter based on the preset applied voltage value and the first target resistance.
And determining protocol port current values i1 and i2, i1= v0/r0 and i2= v1/r0 in the protocol ports in the target converter according to preset applied voltage values v0 and v1 and the determined first target resistor r 0.
Step S615, acquiring a target test current value corresponding to the protocol port current value in the target converter.
The current in the collection port of the target converter is collected, and actual target test current values i3 and i4 are obtained.
Step S616, calculating based on the protocol port current value and the target test current value to obtain a test current parameter.
And calculating the test current parameters of the test current in the first target channel according to i1, i2, i3 and i4, wherein the calculated test current parameters may include a test current slope parameter and a test current offset parameter.
Step S617, calculating according to the test current parameter and the test current data to obtain the calibration test current data.
And substituting the test current slope parameter and the test current offset parameter obtained by calculation into the test current data obtained by testing for calibration so as to calibrate errors in the test current data and obtain calibration test current data with higher precision.
In the embodiment shown in fig. 5, the test current data can be quickly and accurately calibrated during the test current, and the calibration efficiency and precision are improved.
Optionally, referring to fig. 6, fig. 6 is a detailed flowchart of step S620 provided in this embodiment of the application, and step S620 may further include steps S621 to S626.
Step S621, setting an applied current mode according to the second current channel corresponding to the obtained applied current data, so as to control switches of multiple channels, and determine a second target channel corresponding to the target converter.
The method comprises the steps of setting a test voltage mode under the condition of applying current to control switches of a plurality of test channels in the test chip in series, controlling the switches of the second current channel to be closed, and opening switches of other test channels to determine a second target channel for collection when a target converter is connected with a multiplexer of a precision measurement unit.
In step S622, a corresponding second target resistance is determined based on the test range.
According to the test range of the precision measurement unit, the corresponding relay can be controlled to be conducted, so that the corresponding second target resistor r1 is selected, and the second target resistor r1 can be precision resistors of various types and sizes.
Step S623, setting a preset applied current value in the second target channel.
Wherein corresponding port voltage values v0 and v1 and preset applied current values i5 and i6 are set in the protocol ports of the target converter in the second target channel for voltage application and current application.
In step S624, a target applied current value is determined based on the port voltage value in the target converter and the second target resistance.
Wherein the actual target applied current values i7 and i8, i7= v0/r1, i8= v1/r1 in the protocol ports in the target converter are determined from the port voltage values v0 and v1 and the determined second target resistance r 1.
Step S625, calculating based on the preset applied current value and the target applied current value to obtain an applied current parameter.
Wherein, the applied current parameters of the applied current in the second target channel are calculated according to i5, i6, i7 and i8, and the calculated applied current parameters may include an applied current slope parameter and an applied current offset parameter.
Step S626, calculating according to the applied current parameter and the applied current data to obtain the calibration applied current data.
And substituting the calculated applied current slope parameter and the calculated applied current offset parameter into the applied current data obtained by testing for calibration so as to calibrate errors in the applied current data and obtain calibrated applied current data with higher precision.
In the embodiment shown in fig. 6, the applied current data can be quickly and accurately calibrated when the current is applied, and the calibration efficiency and accuracy are improved.
Optionally, referring to fig. 7, fig. 7 is a detailed flowchart of step S500 provided in the present embodiment, and step S500 may further include steps S510 to S520.
Step S510, calibrating the applied voltage data in the first voltage channel based on the target converter, to obtain the calibrated applied voltage data.
The voltage data may include applied voltage data and test voltage data of the test chip, and the voltage channel may include a first voltage channel and a second voltage channel of a plurality of test channels of the test chip. When the voltage is applied to the test chip, the applied voltage data in the first voltage channel can be calibrated through the target converter, and the calibrated applied voltage data with higher precision can be obtained.
Step S520, calibrating the test voltage data in the second voltage channel based on the target converter to obtain calibration test voltage data.
When the test chip is subjected to test voltage, the target converter is used for calibrating test voltage data in the second voltage channel to obtain calibration test voltage data, and the calibration applied voltage data and the calibration test voltage data are taken as the calibration voltage data.
Optionally, when testing and calibrating the first voltage channel and the second voltage channel of the test chip, the testing and calibrating sequence may be changed or performed simultaneously, the first voltage channel may be tested and calibrated first, the second voltage channel may be tested and calibrated second, the first voltage channel may be tested and calibrated first, and the first voltage channel may be tested and calibrated second, and the first voltage channel and the second voltage channel may be tested and calibrated simultaneously.
In the embodiment shown in fig. 7, two voltage modes of the applied voltage and the test voltage can be respectively tested and calibrated, so that the validity and the precision of the calibrated voltage data obtained by calibration are improved, and the efficiency of testing and calibrating the voltage data in the chip test is improved.
Optionally, referring to fig. 8, fig. 8 is a detailed flowchart illustrating step S510 according to an embodiment of the present disclosure, and step S510 may further include steps S511-S514.
Step S511, setting an applied voltage mode according to the first voltage channel corresponding to the acquired applied voltage data, so as to control switches of multiple channels, and determine a third target channel corresponding to the target converter.
The method comprises the steps of using a test channel when voltage is applied in a plurality of test channels of a test chip as a first voltage channel, testing and obtaining voltage application data in the test chip, setting a test voltage mode under the condition of voltage application, controlling switches of the plurality of test channels in the test chip through serial connection, controlling the switches of the first voltage channel to be closed, opening switches of other test channels, determining a third target channel for collection when a target converter is connected with a multiplexer of a precision measurement unit, and controlling a relay to select an open circuit according to the third target channel.
Step S512, a preset applied voltage value is set in the third target channel, and a target applied voltage value is acquired in the target converter.
And acquiring actual target applied voltage values v2 and v3 by pressing the third target channel, setting preset applied voltage values v0 and v1 in the protocol port of the target converter and collecting the actual voltage values of the protocol port in the target converter.
Step S513, calculating based on the preset applied voltage value and the target applied voltage value to obtain an applied voltage parameter.
Wherein, the applied voltage parameters of the applied voltage in the third target channel are calculated according to v0, v1, v2 and v3, and the calculated applied voltage parameters comprise an applied voltage slope parameter and an applied voltage offset parameter.
Step S514, calculating according to the applied voltage parameter and the applied voltage data to obtain the calibration applied voltage data.
And substituting the calculated slope parameter and offset parameter of the applied voltage into the applied voltage data obtained by testing for calibration so as to calibrate errors in the applied voltage data and obtain calibrated applied voltage data with higher precision.
In the embodiment shown in fig. 8, the applied voltage data can be quickly and accurately calibrated when the voltage is applied, and the calibration efficiency and precision are improved.
Optionally, referring to fig. 9, fig. 9 is a detailed flowchart of step S520 provided in the present embodiment, and step S520 may further include steps S521-S524.
Step S521, setting a test voltage mode according to the second voltage channel corresponding to the obtained test voltage data, so as to control switches of multiple channels, and determine a fourth target channel corresponding to the target converter.
The method comprises the steps of setting a test voltage mode under the condition of applying voltage, controlling switches of a plurality of test channels in the test chip through serial connection, controlling the switches of the second voltage channel to be closed, opening switches of other test channels, determining a fourth target channel for collection when a target converter is connected with a multiplexer of a precision measurement unit, and controlling a relay to select an open circuit according to the fourth target channel.
Step S522, setting the preset applied voltage value in the fourth target channel based on the applied voltage parameter, and acquiring a test voltage value in the target converter.
And by applying pressure to the fourth target channel, preset applied voltage values v0 and v1 are set in a protocol port of the target converter, and the actual voltage values of the acquisition ports in the target converter are acquired to obtain actual test voltage values v4 and v 5.
Step S523, calculating based on the preset applied voltage value and the test voltage value to obtain a test voltage parameter.
And calculating test voltage parameters of the test voltage in the fourth target channel according to v0, v1, v4 and v5, wherein the calculated test voltage parameters comprise a test voltage slope parameter and a test voltage offset parameter.
Step S524, calculating according to the test voltage parameter and the test voltage data to obtain the calibration test voltage data.
And substituting the test voltage slope parameter and the test voltage offset parameter obtained by calculation into the test voltage data obtained by testing for calibration so as to calibrate errors in the test voltage data and obtain calibration test voltage data with higher precision.
In the embodiment shown in fig. 9, the test voltage data can be quickly and accurately calibrated during the test voltage, and the calibration efficiency and precision are improved.
The embodiment of the present application further provides an electronic device, which includes a memory and a processor, where the memory stores program instructions, and the processor executes the steps in any one of the chip testing methods provided in this embodiment when reading and executing the program instructions.
It should be understood that the electronic device may be a server, a Personal Computer (PC), a tablet PC, a smart phone, a Personal Digital Assistant (PDA), or other electronic devices having a logical computing function.
The embodiment of the present application further provides a computer-readable storage medium, where computer program instructions are stored, and when the computer program instructions are read and executed by a processor, the steps in any one of the chip testing methods provided in the present embodiment are executed.
In summary, the embodiments of the present application provide a chip testing method, a chip testing system, an electronic device, and a storage medium, which can set a calibration system in a test board to simultaneously test and calibrate different channels of a test chip, and do not need to manufacture a separate calibration board and a separate test instrument to test and calibrate the chip, thereby effectively improving the efficiency and precision of testing and calibrating the chip.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above-described system embodiments are merely illustrative, for example, the block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of devices according to various embodiments of the present application. In this regard, each block in the block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams, and combinations of blocks in the block diagrams, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Therefore, the present embodiment further provides a readable storage medium, in which computer program instructions are stored, and when the computer program instructions are read and executed by a processor, the computer program instructions perform the steps of any of the block data storage methods. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Claims (10)
1. A method for testing a chip, the method comprising:
calibrating an initial converter to obtain a target converter, wherein the initial converter and the target converter are analog-digital converters;
calibrating voltage data in a voltage channel of the test chip based on the target converter to obtain calibrated voltage data;
calibrating current data in a current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data, wherein the current data comprises test current data and applied current data of the test chip, and the current channel comprises a first current channel and a second current channel; the calibrating the current data in the current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data includes: calibrating the test current data in the first current channel based on the target converter and calibration applied voltage data in the calibration voltage data to obtain calibration test current data; calibrating the applied current data in the second current channel based on the target converter to obtain calibrated applied current data, and taking the calibration test current data and the calibration applied current data as the calibration current data.
2. The method of claim 1, wherein calibrating the initial converter to obtain the target converter comprises:
obtaining calibration parameters according to the voltage parameters input into the initial converter, wherein the calibration parameters comprise calibration offset parameters and calibration slope parameters;
and calibrating the initial converter based on the calibration parameters to obtain the target converter.
3. The method of claim 1, wherein calibrating the test current data in the first current path based on the target converter and the calibrated applied voltage data in the calibrated voltage data to obtain calibrated test current data comprises:
setting a test current mode according to the first current channel corresponding to the obtained test current data so as to control switches of a plurality of channels and determine a first target channel corresponding to the target converter;
determining a corresponding first target resistance based on the test range;
setting a preset applied voltage value in the first target channel based on the applied voltage parameter corresponding to the calibration applied voltage data;
determining a protocol port current value in the target converter based on the preset applied voltage value and the first target resistance;
acquiring a target test current value corresponding to the protocol port current value in the target converter;
calculating based on the protocol port current value and the target test current value to obtain test current parameters, wherein the test current parameters comprise a test current slope parameter and a test current offset parameter;
and calculating according to the test current parameters and the test current data to obtain the calibration test current data.
4. The method of claim 1, wherein said calibrating said applied current data in said second current path based on said target converter to obtain calibrated applied current data comprises:
setting an applied current mode according to the second current channel corresponding to the obtained applied current data so as to control switches of a plurality of channels and determine a second target channel corresponding to the target converter;
determining a corresponding second target resistance based on the test range;
setting a preset applied current value in the second target channel;
determining a target applied current value based on the port voltage value in the target converter and the second target resistance;
calculating based on the preset applied current value and the target applied current value to obtain applied current parameters, wherein the applied current parameters comprise an applied current slope parameter and an applied current offset parameter;
and calculating according to the applied current parameter and the applied current data to obtain the calibration applied current data.
5. The method of claim 1, wherein the voltage data comprises applied voltage data and test voltage data for the test chip, the voltage channels comprising a first voltage channel and a second voltage channel; the calibrating the voltage data in the voltage channel of the test chip based on the target converter to obtain the calibrated voltage data comprises the following steps:
calibrating the applied voltage data in the first voltage channel based on the target converter to obtain calibrated applied voltage data;
calibrating the test voltage data in the second voltage channel based on the target converter to obtain calibration test voltage data, and taking the calibration applied voltage data and the calibration test voltage data as the calibration voltage data.
6. The method of claim 5, wherein the calibrating the applied voltage data in the first voltage channel based on the target converter to obtain calibrated applied voltage data comprises:
setting an applied voltage mode according to the first voltage channel corresponding to the acquired applied voltage data so as to control switches of a plurality of channels and determine a third target channel corresponding to the target converter;
setting a preset applied voltage value in the third target channel, and acquiring a target applied voltage value in the target converter;
calculating based on the preset applied voltage value and the target applied voltage value to obtain applied voltage parameters, wherein the applied voltage parameters comprise an applied voltage slope parameter and an applied voltage offset parameter;
and calculating according to the applied voltage parameters and the applied voltage data to obtain the calibration applied voltage data.
7. The method of claim 6, wherein the calibrating the test voltage data in the second voltage channel based on the target converter to obtain calibrated test voltage data comprises:
setting a test voltage mode according to the second voltage channel corresponding to the obtained test voltage data so as to control switches of a plurality of channels and determine a fourth target channel corresponding to the target converter;
setting the preset applied voltage value in the fourth target channel based on the applied voltage parameter, and acquiring a test voltage value in the target converter;
calculating based on the preset applied voltage value and the test voltage value to obtain a test voltage parameter, wherein the test voltage parameter comprises a test voltage slope parameter and a test voltage offset parameter;
and calculating according to the test voltage parameters and the test voltage data to obtain the calibration test voltage data.
8. A chip test system is characterized by comprising a plurality of calibration modules and a plurality of test boards, wherein each calibration module is arranged in the corresponding test board so as to calibrate a plurality of channels of a test chip simultaneously through the calibration modules;
the calibration module also comprises a converter calibration submodule, a voltage calibration submodule and a current calibration submodule;
the converter calibration submodule is used for calibrating an initial converter to obtain a target converter, and the initial converter and the target converter are analog-digital converters;
the voltage calibration submodule is used for calibrating voltage data in a voltage channel of the test chip based on the target converter to obtain calibration voltage data;
the current calibration submodule is used for calibrating current data in a current channel of the test chip based on the calibration voltage data and the target converter to obtain calibration current data, wherein the current data comprise test current data and applied current data of the test chip, and the current channel comprises a first current channel and a second current channel; the current calibration submodule is further configured to: calibrating the test current data in the first current channel based on the target converter and calibration applied voltage data in the calibration voltage data to obtain calibration test current data; calibrating the applied current data in the second current channel based on the target converter to obtain calibrated applied current data, and taking the calibration test current data and the calibration applied current data as the calibration current data.
9. An electronic device comprising a memory having stored therein program instructions and a processor that, when executed, performs the steps of the method of any of claims 1-7.
10. A computer-readable storage medium having computer program instructions stored thereon for execution by a processor to perform the steps of the method of any one of claims 1-7.
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| CN114400042B (en) * | 2022-03-22 | 2022-06-10 | 合肥悦芯半导体科技有限公司 | Memory test system |
| CN115993568B (en) * | 2023-03-24 | 2023-05-30 | 绅克半导体科技(苏州)有限公司 | Semiconductor tester and direct current calibration method for test channel of semiconductor tester |
| CN116185784B (en) * | 2023-04-25 | 2023-09-08 | 荣耀终端有限公司 | Calibration device, calibration system and acquisition system |
| CN117214663B (en) * | 2023-09-14 | 2024-03-29 | 南京天易合芯电子有限公司 | Application method of system-level chip test board |
| CN117250483A (en) * | 2023-11-17 | 2023-12-19 | 深圳市航顺芯片技术研发有限公司 | Chip test system and method |
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| JP4592796B2 (en) * | 2008-12-15 | 2010-12-08 | 三菱電機株式会社 | Electronic control unit with analog input signal |
| US20110316556A1 (en) * | 2010-06-29 | 2011-12-29 | Eric Paul Bergeron | Calibrating a channel of a test system |
| ES2787825T3 (en) * | 2012-10-12 | 2020-10-19 | Alstom Transp Tech | Automatic calibration of the energy meter central unit |
| US10809287B2 (en) * | 2013-08-16 | 2020-10-20 | Arcteq Relays Oy | Method and system and computer program for measuring alternating-current system quantities |
| TWI580194B (en) * | 2015-09-24 | 2017-04-21 | 瑞昱半導體股份有限公司 | Chip having self-calibration mechanism and calibration method thereof |
| US11144316B1 (en) * | 2018-04-17 | 2021-10-12 | Ali Tasdighi Far | Current-mode mixed-signal SRAM based compute-in-memory for low power machine learning |
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Address after: 230000 2 / F, east side of building D1, intelligent equipment science and Technology Park, 3963 Susong Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: Yuexin Technology Co.,Ltd. Address before: 230000 2 / F, east side of building D1, intelligent equipment science and Technology Park, 3963 Susong Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee before: Hefei Yuexin Semiconductor Technology Co.,Ltd. Address after: 230000 2 / F, east side of building D1, intelligent equipment science and Technology Park, 3963 Susong Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee after: Hefei Yuexin Semiconductor Technology Co.,Ltd. Address before: 230000 2 / F, east side of building D1, intelligent equipment science and Technology Park, 3963 Susong Road, Hefei Economic and Technological Development Zone, Anhui Province Patentee before: Hefei Yuexin Semiconductor Technology Co.,Ltd. |