JPH1174789A - A/d converter measuring device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an A/D converter measuring device capable of exactly measuring an integral nonlinearity error and/or a differential nonlinearity error of an A/D converter. SOLUTION: The A/D converter measuring device to measure the integral nonlinearity error and/or the differential nonlinearity error of the A/D converter is provided with a D/A converter 1 to supply inputted voltage to the A/D converter 15 as an object to be measured and to vary the inputted voltage and a CPU 5 to discriminate zero transition voltage and full transition voltage of the A/D converter 15 based on relation between the inputted voltage supplied from the D/A converter 1 and an output code of the A/D converter 15 and to calculate the integral nonlinearity error and/or the differential nonlinearity error by every output code of the A/D converter 15 from values of the zero transition voltage and the full transition voltage and the number of bits of the A/D converter 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter measuring device for measuring characteristics of an A / D converter.

[0002]

2. Description of the Related Art As shown in FIG. 4, a conventional A / D converter measuring apparatus includes reference D / A converters 21 and 22 and an operational amplifier 23, and an A / D converter as an object to be measured.
The configuration is such that the / D converter 25 is connected between the reference D / A converter 21 and the reference D / A converter 22.
In this A / D converter measuring device, input data from an LSI tester is converted into an analog voltage by a reference D / A converter 21, and the analog voltage is converted into digital data by an A / D converter 25, and the digital data is converted. The reference voltage is converted into an analog voltage by the reference D / A converter 22, and the analog voltage and the reference D / A
The difference from the analog voltage from the A converter 21 is amplified by the operational amplifier 23 constituting the differential amplifier, and is output as an integral nonlinearity error. In the measurement of the A / D converter 25, when the reference D / A converter 21 has, for example, 12 bits, the input data from the LSI tester is set to 0.
The output is sequentially changed from 00 (H) to FFF (H), and the difference between the output of the reference D / A converter 21 and the output of the reference D / A converter 22 at that time is monitored.

As another conventional A / D converter measuring device, as shown in FIG.
1, a digital comparator 32 and a reference A / D converter 33 are known, and an A / D converter 35 to be measured is connected between the reference D / A converter 31 and the digital comparator 32. . In this A / D converter measuring device, an LSI
The input data from the tester is converted into an analog voltage by the reference D / A converter 31, and the analog voltage is converted to an analog voltage.
The data is converted into digital data by the D converter 35, and is also converted into digital data by the reference A / D converter 33. The digital data is compared by the digital comparator 32, and an integral nonlinearity error is output. In the measurement of the A / D converter 35, when the reference D / A converter 31 has, for example, 12 bits, the input data from the LSI tester is sequentially changed from 000 (H) to FFF (H), and the A / D at that time is changed. The difference between the output of the converter 35 and the output of the reference A / D converter 33 is monitored.

However, in the conventional A / D converter measuring apparatus as described above, the A / D converter 2 to be measured is
Since only the difference between the input and output of the A / D converters 25 and 35 is compared as an analog voltage or digital data and the result is output, the zero transition voltage and the full transition voltage of the individual A / D converters 25 and 35 can be measured. Did not. For this reason, typical zero transition voltage and full transition voltage of the A / D converters 25 and 35 to be measured are determined in advance, and the reference D / A converters 21 and 22 are adjusted in accordance with the zero transition voltage and the full transition voltage. , 31 and standard A
The zero transition voltage and the full transition voltage of the / D converter 33 were adjusted. Therefore, the individual A / D converters 25 and 35, which are the actual measurement targets,
If the zero transition voltage and full transition voltage are different from the typical values, and the slope of the ideal straight line that represents the ideal input / output relationship is different from the typical value, measure the accurate integral nonlinearity error. Could not. Moreover, the reference D / A converters 21, 22, 31 and the reference A /
A non-linearity of the input / output characteristics of the D converter 33 or a characteristic change due to a change in the ambient temperature or the like appears as an error in the measurement result. As a result, the measured A /
In some cases, the D converters 25 and 35 are determined to be defective in spite of the fact that they are non-defective, resulting in a decrease in yield.

Further, not only the zero transition voltage and the full transition voltage but also the differential nonlinearity error cannot be measured.

The zero transition voltage is defined as A /
When the D converter is 8-bit, for example, the analog input voltage when the output code changes from 00 (H) to 01 (H), and the full transition voltage is A /
When the D converter has, for example, 8 bits, it is an analog input voltage when the output code changes from FE (H) to FF (H). (H) indicates that the preceding numerical value is a hexadecimal number. The integral nonlinearity error is
As shown in FIG. 6, it indicates how much the analog input voltage for the digital output code deviates from the ideal straight line. The differential nonlinearity error is, as shown in FIG. This represents how much the step width of the analog input voltage deviates from the ideal step width. The ideal step width is the minimum resolution, that is, 1 LSB, and is calculated by the following equation (1) or (2). In the following Expression 1 or 2, n is the number of bits of the A / D converter 15.

[0007]

(Equation 1)

[0008]

(Equation 2)

[0009]

DISCLOSURE OF THE INVENTION The present invention has been conceived in view of the above circumstances, and has an A / D converter capable of accurately measuring an integral non-linearity error and / or a differential non-linearity error of an A / D converter. It is an object to provide a D converter measuring device.

In order to solve the above problems, the present invention takes the following technical measures.

According to a first aspect of the present invention, there is provided an A / D converter measuring apparatus for measuring an integral nonlinearity error and / or a differential nonlinearity error of an A / D converter,
An input voltage supply unit for supplying an input voltage to an A / D converter to be measured and varying the input voltage, based on a relationship between the input voltage supplied from the input voltage supply unit and an output code of the A / D converter. Then, the zero transition voltage and the full transition voltage of the A / D converter are determined, and from these values and the number of bits of the A / D converter, for each output code of the A / D converter, the integral nonlinearity error and / or Alternatively, there is provided an A / D converter measuring device, comprising an error calculating means for calculating a differential nonlinearity error.

According to a preferred embodiment, the error calculating means calculates a slope of an ideal straight line representing an ideal input / output relationship of the A / D converter by using the zero transition voltage and the full transition voltage, and calculates the slope of the ideal straight line. An integral non-linearity error is calculated for each output code of the A / D converter based on the slope of the straight line.

According to another preferred embodiment, the error calculating means uses the number of bits of the A / D converter and the zero transition voltage and the full transition voltage to perform A / D conversion.
The minimum resolution of the / D converter is calculated, and the integral non-linearity error and / or the differential non-linearity error are calculated for each output code of the A / D converter based on the minimum resolution.

According to another preferred embodiment, the input voltage supply means has first D / A conversion means for converting digital input data into an analog voltage and supplying the analog voltage to the A / D converter. The calculation means is realized by a CPU which determines a zero transition voltage and a full transition voltage of the A / D converter based on a relationship between digital input data and an output code of the A / D converter.

According to another preferred embodiment, the A / D converter to be measured is implemented as an IC including only the A / D converter or other circuits, and outputs the output of the error calculating means realized by the CPU. A second D / A converter for converting the voltage into an analog voltage and outputting the analog voltage; and an IC socket in which an integrated A / D converter is mounted.
The / A conversion means, the CPU, the second D / A conversion means, and the IC socket are mounted on one board.

According to another preferred embodiment, the second D / A converter converts the zero transition voltage and the full transition voltage determined by the error calculator into analog voltages and outputs the analog voltages.

According to the present invention, the error calculating means determines, for each A / D converter, a zero transition voltage and a full transition voltage, and uses them to determine an integral nonlinearity error and / or a differential nonlinearity. , The integral nonlinearity error of the A / D converter and / or
Alternatively, the differential nonlinearity error can be accurately measured.

That is, the ideal straight line and the minimum resolution for each A / D converter can be obtained by using the zero transition voltage and the full transition voltage, so that regardless of the variation in the characteristics of each A / D converter. , Integral nonlinearity error and / or differential nonlinearity error can be accurately measured.

Therefore, it is possible to avoid a decrease in yield due to erroneously determining a non-defective product as a defective product, and when a strict standard value is required, it is possible to accurately determine whether or not the standard value is satisfied.

A part of the input voltage supply means and the error calculation means are operated, for example, by a predetermined program.
It can be realized by PU.

If the input voltage supply means is provided with first D / A conversion means for converting digital input data into an analog voltage and supplying it to the A / D converter, and the error calculation means is realized by a CPU, By monitoring the input data and the output code of the A / D converter by the CPU, the zero transition voltage and the full transition voltage can be easily determined.

A second D / A conversion means for converting the output of the error calculation means realized by the CPU into an analog voltage and outputting the analog voltage; and an IC socket on which an integrated A / D converter is mounted. And the first D / A converter, the CPU, the second D / A converter, and the IC socket are connected to one another.
When mounted on individual substrates, measurement can be easily performed using an LSI tester or the like simply by mounting an integrated A / D converter in an IC socket.

Further, if the second D / A conversion means converts the zero transition voltage and the full transition voltage determined by the error calculation means into an analog voltage and outputs the analog voltage, the zero transition voltage and the full transition voltage Can be known as an analog voltage value. .

[0024] Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

FIG. 1 is a circuit block diagram of an A / D converter measuring device according to the present invention. The A / D converter measuring device includes a D / A converter 1, a low-pass filter 2, an operational amplifier 3, and a data selector. 4, CPU5, R
AM6, latch circuit 7, D / A converter 8, low-pass filter 9, relays 10a and 10b, correction amplifier 11,
And resistor comprises a R ₁ ~R _4, A / D converter 15 as the measurement object, by attaching in FIG outside of the IC socket is connected between the operational amplifier 3 and data selector 4. These D / A converter 1, low-pass filter 2, operational amplifier 3, data selector 4, CPU
5, RAM 6, latch circuit 7, D / A converter 8, the low pass filter 9, the relay 10a, 10b, the correction amplifier 11, resistors R ₁ to R _4, and the IC socket is mounted on one printed circuit board ing. The resistor R ₁ is connected between the output terminal of the low-pass filter 2 and the non-inverting input terminal of the operational amplifier 3. The connection point between the resistor R ₁ and the non-inverting input terminal of the operational amplifier 3 is the resistor R _1. Grounded through _two . Resistor R ₃ is connected between the contact point of the contacts and relays 10b of the relay 10a, the connection point between the contacts of resistor R ₃ and the relay 10b is grounded via a resistor R _4. If the characteristics of the D / A converter 1 properties and the D / A converter 8 are the same, a resistor equal to the resistance value of R ₁ and the resistance value of the resistor R _3, the resistance value and the resistance resistor R ₂ equal the resistance of the vessel R _4.

The D / A converter 1 converts digital input data input from an unillustrated LSI tester into an analog voltage and outputs the analog voltage to the low-pass filter 2. Low-pass filter 2 removes a predetermined frequency or more unnecessary frequency component superimposed on the analog voltage from the D / A converter 1 is supplied to the non-inverting input of the operational amplifier 3 via a resistor R _1. The operational amplifier 3 acts as a buffer amplifier, impedance-converts the analog voltage from the D / A converter 1 and supplies the analog voltage to the input terminal of the A / D converter 15. The data selector 4 is controlled by the CPU 5 to control the digital output from the A / D converter 15 and the LS
The input data from the I tester is selectively supplied to the CPU 5. The CPU 5 controls the data selector 4, the latch circuit 7, and the relays 10a and 10b according to the instruction code from the LSI tester.
The selected data is subjected to arithmetic processing, and the arithmetic result is written to the RAM 6 or output to the latch circuit 7. The RAM 6 is used by the CPU 5 to write and read operation result data.

The latch circuit 7 includes, for example, a plurality of D flip-flop circuits, and latches data from the CPU 5. The D / A converter 8 converts the data latched by the latch circuit 7 into an analog voltage and outputs the analog voltage to the low-pass filter 9. The low-pass filter 9 removes unnecessary frequency components higher than a predetermined frequency superimposed on the analog voltage from the D / A converter 8, and removes the relays 10a, 1
0b is supplied to the input terminal of the correction amplifier 11. The relays 10a and 10b are controlled by the CPU 5 to directly connect the output terminal of the low-pass filter 9 to the input terminal of the correction amplifier 11, and to connect the output terminal of the low-pass filter 9 and the input terminal of the correction amplifier 11 with a resistor R. Switch to the state of connecting via ₃ . Although not shown, the relay 10
The connection states of a and 10b are switched by the CPU 5 controlling the energization of the coil. Correction amplifier 11
Amplifies the analog voltage from the D / A converter 8 and outputs it as an output value of the A / D converter measuring device.

Next, the operation of the A / D converter measuring device will be described. A / D converter 1 whose measurement target is 8 bits
In the case of 5, for example, a 12-bit D / A converter 1 is used. At the time of measurement, an instruction code is supplied to the CPU 5 from an LSI tester (not shown) and the D / A
Input data is supplied to converter 1. This gives C
The PU 5 negates the select signal supplied to the data selector 4 to input the output code of the A / D converter 15 to the CPU 5, and to relay 10a, 10b
To control the output end of the low-pass filter 9 and the correction amplifier 1
1 is directly connected to the input terminal. Then, the LSI tester
The input data supplied to the input terminal of the / A converter 1 is increased at a predetermined cycle. This input data is first 00
0 (H), 001 (H), 002 (H), 0
03 (H), etc.
The increase ends when the output code of the D converter 15 becomes FF (H). (H) indicates that the preceding digit string is 16
It represents a decimal number. When the input data to the D / A converter 1 is sequentially increased as described above, the D / A
The analog voltage which is both the output of the converter 1 and the input of the A / D converter 15 sequentially increases, and the output code of the A / D converter 15 changes from 00 (H) to 01 (H) at some point. As a result, the CPU 5 asserts the select signal supplied to the data selector 4 and causes the CPU 5 to input the input data from the LSI tester. Then, the CPU 5 stores the value of the input data in the RAM 6.

Similarly, every time the output code of the A / D converter 15 increases by one, the input data from the LSI tester at that time is stored in the RAM 6. As a result, the output code of the A / D converter 15 becomes 0 in the RAM 6.
From input data X ₁ (H) when it becomes ₁ (H), A /
255 pieces of input data up to input data X ₂₅₅ (H) when the output code of the D converter 15 becomes FF (H) are stored.

Then, the CPU 5 stores the data stored in the RAM 6
255 input data X₁(H) -X₂₅₅Based on (H)
In addition, each time the output code of the A / D converter 15 outputs
Calculate the linearity error and store the calculation result in the latch circuit 7.
Latch sequentially. Specifically, the CPU 5 sets the A / D
The output code of the inverter 15 changes from 00 (H) to 01 (H).
Analog input voltage data X when it changes to₁(H)
Zero transition voltage V₀And A / D converter 1
5 output code changed from FE (H) to FF (H)
Analog input data X₂₅₅(H) full transition
Voltage V_FAnd Then, the CPU 5
Transition voltage V₀And full transition voltage V_F
And A / D converter 15 using the number of bits
Calculates the value of 1 LSB which is the minimum resolution of converter 15
Then, it is stored in the RAM 6. And the CPU 5
Zero transition voltage V₀And full transition voltage
V _FA / D converter 1 based on and 1LSB value
For each output code of No. 5, an integral nonlinearity error is calculated. You
That is, the zero transition voltage V₀And full transient
Voltage V_FA / D converter based on and 1LSB value
Calculation of ideal input voltage data for each of 15 output codes
Can be multiplied by that value and the value of the actual input data.
The minute nonlinearity error is calculated. Calculate integral nonlinearity error
The CPU 5 that has supplied the latch signal to the latch circuit 7
Signal for a predetermined time to latch the integral nonlinearity error
The circuit 7 sequentially latches. The CPU 5 has an A / D
Integral nonlinearity error calculated for each output code of inverter 15
The maximum value and the minimum value of the difference are stored in the RAM 6.

The integral nonlinearity error latched by the latch circuit 7 is converted into an analog voltage by a D / A converter 8 and output via a low-pass filter 9, relays 10a and 10b, and a correction amplifier 11. That is, a voltage corresponding to the integral nonlinearity error is sequentially output from the output terminal of the correction amplifier 11 at a predetermined timing for each output code of the A / D converter 15. By observing this output with, for example, a digital storage oscilloscope, a waveform as shown in FIG. 2 is obtained. 2, the horizontal axis represents the output code of the A / D converter 15, and the vertical axis represents the integral nonlinearity error in LSB units.

On the other hand, in the measurement of the differential nonlinearity error, the CPU 5 calculates A / A based on the value of ₁ LSB stored in the RAM 6 and 255 pieces of input data X ₁ (H) to X ₂₅₅ (H). The differential non-linear error is calculated for each output code of the D converter 15, the latch signal supplied to the latch circuit 7 is asserted for a predetermined time, and the differential non-linear error is sequentially latched by the latch circuit 7. Also, the CPU 5
The maximum value and the minimum value of the differential nonlinearity error calculated for each output code of the / D converter 15 are stored in the RAM 6.

The differential nonlinearity error latched by the latch circuit 7 is converted into an analog voltage by the D / A converter 8 and output via the low-pass filter 9, the relays 10a and 10b, and the correction amplifier 11. That is, a voltage corresponding to the differential nonlinearity error is sequentially output at a predetermined timing from the output terminal of the correction amplifier 11 for each output code of the A / D converter 15. By observing this output with, for example, a digital storage oscilloscope, a waveform as shown in FIG. 3 is obtained. The horizontal axis in FIG. 3 represents the output code of the A / D converter 15, and the vertical axis represents the differential nonlinearity error in LSB units.

When the output of the integral nonlinear error and the differential nonlinear error for each output code of the A / D converter 15 is completed, the CPU 5 reads the maximum value and the minimum value of the integral nonlinear error from the RAM 6 and Are output from the output terminals of the correction amplifier 11 by the same operation as described above. Further, the CPU 5 reads the maximum value and the minimum value of the differential nonlinearity error from the RAM 6 and outputs the same from the output terminal of the correction amplifier 11 by the same operation as described above.

It should be noted that which of the integral nonlinearity error and the differential nonlinearity error is to be measured is determined by an instruction code to the CPU 5. The order of measurement may be from either measurement, and only one of the integral non-linearity error and the differential non-linearity error may be measured.
Each of the above errors is output from the output terminal of the correction amplifier 11 so that an error of 1 LSB becomes 1 V. However,
When measuring the zero transition voltage V ₀ and the full transition voltage V _F , they are output as voltage units as they are.

Also, the LSI tester sends a predetermined
By inputting the instruction code, the output of the correction amplifier 11
Zero transition voltage V from the power end₀And full tran
Voltage V_FCan also be output. This place
In this case, the CPU 5 controls the relays 10a and 10b to
Output terminal of the pass filter 9 and the input terminal of the correction amplifier 11
Is the resistor R_ThreeVia the RAM 6
Transition voltage V₀Read the data corresponding to
By asserting the latch signal of the latch circuit 7,
Low transition voltage V₀Latch data corresponding to
Latch on road 7. This zero transition voltage V₀
Is converted to analog data by the D / A converter 8.
To the low-pass filter 9, relay 10
a, resistor R _Three, And through the relay 10b,
Output from the output terminal of the amplifier 11. At this time, D / A
Same as inverter 1 and D / A converter 8
When using a D / A converter with characteristic
1 output voltage is zero transition voltage V₀Equals
As shown, the resistor R_ThreeResistance and resistor R₁And the resistance of
Are set equal, and the resistor R_FourResistance and resistor R_TwoNo
Set the resistance value equal.

After outputting the zero transition voltage V ₀ , C
PU5 reads the data corresponding to the full transition voltage V _F from the RAM 6, by asserting a latch signal of the latch circuit 7 to latch the data corresponding to the full transition voltage V _F to the latch circuit 7.
Data corresponding to the full transition voltage V _F is
The D / A converter 8 is converted to an analog voltage, the low pass filter 9, the relay 10a, the resistor R _3, and through the relay 10b, is output from the output terminal of the correction amplifier 11. At this time, D / A converter 1 and D / A
When using the D / A converter of the same characteristics with each other as a converter 8, so that the output voltage of the correction amplifier 11 is equal to the full transition voltage V _F, the resistance value of the resistor R ₃ and the resistance value of the resistor R ₁ equally set, the resistor R the resistance value of ₄ and the resistor is set equal to the resistance value of R _2.

When the mass-produced A / D converter 15 is continuously and rapidly measured, the integration non-linearity error and the differential non-linearity error are not output for each output code of the A / D converter 15 and the integration is performed. It is also possible to output only the maximum value and the minimum value of the nonlinearity error and the differential nonlinearity error. That is, when a predetermined instruction code is input to the CPU 5 from the LSI tester, the CPU 5 reads the maximum value and the minimum value of the integral nonlinearity error from the RAM 6 and outputs the same from the output terminal of the correction amplifier 11.
The maximum value and the minimum value of the differential nonlinearity error are read from 6 and output from the output terminal of the correction amplifier 11. At this time, the output terminal of the low-pass filter 9 and the input terminal of the correction amplifier 11 are directly connected by relays 10a and 10b.
Note that together with the maximum and minimum values of the integral nonlinearity error and the differential nonlinearity error, or instead of the maximum and minimum values of the integral nonlinearity error and the differential nonlinearity error,
The determination result of whether or not the maximum value and the minimum value of the predetermined integral nonlinearity error and the differential nonlinearity error are within a range of a predetermined standard value may be output.

As described above, each A / D converter 15
Since the integral non-linearity error and the differential non-linearity error are calculated by measuring the zero transition voltage V ₀ and the full transition voltage V _{F of} each A / D converter 1,
Regardless of variations in the characteristics of the D / A converters 1 and 8 due to variations in the characteristics of the D / A converters 1 and 8, the integral nonlinearity error and the differential nonlinearity error can always be measured relatively accurately. Further, it accurately outputs zero transition voltage V ₀ and the full transition voltage V _F as an analog voltage. Further, it is not necessary to adjust measurement circuits such as the D / A converters 1 and 8, and stable measurement can be performed. In addition, the output of the correction amplifier 11 is stored in a digital storage
By making a hard copy of the observed waveform while observing with an oscilloscope or the like, it is possible to save an integral nonlinearity error, a differential nonlinearity error, and the like as a paper file. Of course, the integral non-linearity error and differential non-linearity error stored in the RAM 6 can be stored as data using a hard disk device, a magneto-optical disk device, or the like.

In the above embodiment, the output code of the A / D converter 15 changes from the input data X ₁ (H) when the output code of the A / D converter 15 becomes 01 (H) to FF (H). Input data X when it becomes
After storing 255 pieces of input data up to ₂₅₅ (H) in the RAM 6, the integral nonlinearity error and the differential nonlinearity error are output for each output code of the A / D converter 15, but the input data X ₁ Input data X ₂₅₅ (H) from (H)
It may be configured to output the integral non-linearity error or the differential non-linearity error while acquiring up to. in this case,
At the beginning of the measurement, the zero transition voltage V ₀ and the full transition voltage V _F are measured, and 1
The value of LSB is calculated, and the input data X ₁ (H) is used to calculate the input data X ₂₅₅ (H) using the value of ₁ LSB.
The integral or differential nonlinearity error up to
The calculation is performed each time the input data X is obtained, and the correction data is sequentially output from the correction amplifier 11. Then, the maximum value and the minimum value of the calculated integral nonlinearity error and differential nonlinearity error are calculated by RA
After the output of the integral nonlinearity error or the differential nonlinearity error for each output code of the A / D converter 15 is completed, the maximum value of the integral nonlinearity error or the differential nonlinearity error is stored from the RAM 6. Read and output the value and the minimum value.

In the above-described embodiment, a 12-bit D / D converter is used to measure the 8-bit A / D converter 15.
Although the A converter 1 is used, it is a matter of course that the number of bits is not limited to these. Basically, D /
The number of bits of the A-converter 1 may be at least 4 bits larger than the number of bits of the A / D converter 15. D / A
The number of bits of converter 8 is not particularly limited either, and may be the same as or different from the number of bits of D / A converter 1. Further, as the D / A converter 1 and the D / A converter 8, a serial input D / A converter may be used.

In the above embodiment, the output of the D / A converter 1 always passes through the low-pass filter 2 and
Although the output of the A converter 8 is configured to always pass through the low-pass filter 9, a bypass path is provided in the low-pass filter 2 or the low-pass filter 9 so that the low-pass filter 2 or the low-pass filter 9 can be passed through as necessary. Is also good. Low-pass filter 2,
The order of 9 is arbitrary. A plurality of filters may be provided in parallel or in series, and an analog multiplexer or a relay may be provided so that one of the filters can be arbitrarily selected.

In the above embodiment, the resistor R ₁
To R ₄ and the provided, but these are not necessarily provided. When the resistors R _{1 to} R ₄ are provided, their resistance values may be appropriately set according to various design conditions. Further, instead of grounding the resistors R ₂ and R ₄ , a predetermined power supply voltage may be applied.

Although the data selector 4 is provided in the above embodiment, if the input port of the CPU 5 has room, the data selector 4 is not provided and the input data from the LSI tester and the A / D converter 15 are provided. May be configured to be input to the input port of the CPU 5. When the data selector 4 is provided, the data selector 4 may be configured by a general-purpose logic circuit,
You may comprise by a gate array.

In the above embodiment, the latch circuit 7 is provided as an independent circuit.
If the A converter 8 has a built-in latch circuit, it may be used. When the latch circuit 7 is provided as an independent circuit, the latch circuit 7 may be configured by a general-purpose logic circuit or a gate array.

In the above embodiment, the RAM 6 is provided as an independent circuit.
When the AM is built in, it may be used. CP
Although specific configurations of the U5 and the RAM 6 are not particularly limited, the instruction code from the LSI tester is determined according to the CPU 5.

In the above embodiment, the correction amplifier 11 is provided, but the correction amplifier 11 is not always required.

In the above embodiment, the instruction code and the input data are supplied by the LSI tester.
A general-purpose digital function instead of a tester
A generator or the like may be used. In addition, an instruction code is supplied to the CPU 5 from a ROM or the like,
The A converter 1 may be supplied with input data.

In the above embodiment, both the integral non-linearity error and the differential non-linearity error are output, but only one of them may be output.

In the above embodiment, the input data to the D / A converter 1 is increased by one. However, the number of the input data may be increased by any number, for example, 001.
(H), 003 (H), 005 (H), etc.
It may be increased every bit.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of an A / D converter measurement device according to the present invention.

FIG. 2 is an explanatory diagram of an observation waveform of an integral nonlinearity error by the A / D converter measurement device according to the present invention.

FIG. 3 is an explanatory diagram of an observed waveform of a differential nonlinearity error by the A / D converter measurement device according to the present invention.

FIG. 4 is a circuit block diagram of a conventional A / D converter measuring device.

FIG. 5 is a circuit block diagram of another conventional A / D converter measuring device.

FIG. 6 is an explanatory diagram of an integral nonlinearity error.

FIG. 7 is an explanatory diagram of a differential nonlinearity error.

[Description of Signs] 1 D / A converter 2 Low-pass filter 3 Operational amplifier 4 Data selector 5 CPU 6 RAM 7 Latch circuit 8 D / A converter 9 Low-pass filter 10a, 10b Relay 11 Correction amplifier 15 A / D converter

Claims (6)

[Claims] An A / D converter measuring device for measuring an integral nonlinearity error and / or a differential nonlinearity error of an A / D converter, wherein an input voltage is supplied to the A / D converter as a measurement target. An input voltage supply means for varying the input voltage; an input voltage supplied from the input voltage supply means;
A zero transition voltage and a full transition voltage of the A / D converter are determined based on a relationship with an output code of the A / D converter, and the A / D converter is determined based on these values and the number of bits of the A / D converter. An A / D converter measuring apparatus, comprising: an error calculating means for calculating an integral nonlinearity error and / or a differential nonlinearity error for each output code of a converter. 2. The error calculation means according to claim 1, wherein said error transition means uses said zero transition voltage and full transition voltage to generate said A transition.
The slope of an ideal straight line representing the ideal input / output relationship of the / D converter is calculated, and based on the slope of the ideal straight line, the A
2. The A / D converter measuring device according to claim 1, wherein an integral nonlinearity error is calculated for each output code of the / D converter. 3. The error calculating means calculates a minimum resolution of the A / D converter using the number of bits of the A / D converter and the zero transition voltage and the full transition voltage, and based on the minimum resolution. And calculating an integral nonlinearity error and / or a differential nonlinearity error for each output code of the A / D converter.
2. The A / D converter measuring device according to 1. 4. The input voltage supply means has first D / A conversion means for converting digital input data into an analog voltage and supplying the analog voltage to the A / D converter. Based on the relationship between digital input data and the output code of the A / D converter,
4. The A according to claim 1, wherein the A / D converter is realized by a CPU that determines a zero transition voltage and a full transition voltage.
/ D converter measurement device. 5. The A / D converter to be measured is an IC including only the A / D converter or another circuit, and converts an output of an error calculating means realized by the CPU into an analog voltage. A second D / A converter for outputting the data; and an IC socket to which the A / D converter is integrated. The first D / A converter, the CPU, and the second D are provided.
The A / D converter measurement device according to claim 4, wherein the / A conversion means and the IC socket are mounted on one board. 6. The A / A converter according to claim 5, wherein said second D / A converter converts the zero transition voltage and the full transition voltage determined by the error calculator into analog voltages and outputs the analog voltages. D converter measurement device.