CN114116583A

CN114116583A - Serial communication method of double chips and system with double chips

Info

Publication number: CN114116583A
Application number: CN202111363879.2A
Authority: CN
Inventors: 黄一检; 邹锡挺; 叶文斌; 马永超
Original assignee: Delixi Hangzhou Inverter Co ltd
Current assignee: Delixi Hangzhou Inverter Co ltd
Priority date: 2021-11-17
Filing date: 2021-11-17
Publication date: 2022-03-01
Anticipated expiration: 2041-11-17
Also published as: CN114116583B

Abstract

The application relates to a serial communication method of a dual chip and a system with the dual chip. Wherein, the method comprises the following steps: the method comprises the steps that a first chip obtains at least one group of subdata and a group number of the subdata, wherein the subdata is not successfully sent to a second chip in a current period in first data and second data; the first chip carries the first data, the subdata and the group number of the subdata in a frame of serial data frame and sends the frame of serial data frame to the second chip; and under the condition that the subdata which is not successfully sent to the second chip exists in the current period, sending the next serial data frame until all the subdata in the current period are sent. By the method and the device, high-speed communication of a large amount of data between the double chips is achieved.

Description

Serial communication method of double chips and system with double chips

Technical Field

The present application relates to the field of serial communication, and in particular, to a serial communication method for dual chips and a system having the dual chips.

Background

Along with the improvement of the electrical design of the frequency converter and the increase of user functions, more and more frequency converters adopt a double-chip scheme so as to be respectively responsible for the logic control and the driving control of the frequency converter through different chips.

The dual-chip solution inevitably involves the problem of communication between chips, and especially in the frequency converter, some data needs to be fed back from one chip to the other chip in real time, which puts high requirements on the speed of data interaction. In the related art, a data transmission method of a frequency converter dual control chip system is proposed, in which 8 bytes are transmitted per packet of data between a master CPU and a slave CPU, 6 bytes of which are fixed data contents, and thus, the scheme can only realize high-speed transmission of data contents of a fixed number of bytes. However, in a frequency converter scenario or the like, there may be hundreds of bytes of data that needs to complete interaction between the dual chips in a short time, and real-time communication of hundreds of bytes of data cannot be achieved by using the above scheme. An effective solution has not been proposed for how to achieve high-speed communication of a large amount of data between dual chips.

Disclosure of Invention

The application provides a serial communication method of double chips and a system with the double chips, which are used for solving the problem that high-speed communication of a large amount of data cannot be realized between the double chips.

In a first aspect, an embodiment of the present application provides a serial communication method for a dual chip, including:

step 1, a first chip acquires at least one group of subdata which is not successfully sent to a second chip in a current period and a group number of the subdata from first data and second data, wherein a memory area of the first chip comprises a first memory area and a second memory area, the first memory area is used for storing the first data, the second memory area is used for storing the second data, the second data comprises a plurality of groups of subdata, and each group of subdata has a group number;

step 2, the first chip carries the first data, the subdata and the group number of the subdata in a frame of serial data frame and sends the frame of serial data frame to the second chip;

and 3, skipping to the step 1 under the condition that the subdata which is not successfully sent to the second chip exists in the current period, otherwise, ending the sending of the serial data frame of the current period.

In some of these embodiments, after the step 2, the method further comprises:

and the first chip receives the response information of the second chip and judges whether the subdata is successfully sent to the second chip according to the response information.

In some embodiments, the response information of the second chip carries a group number of the last at least one group of sub data successfully received by the second chip.

In some embodiments, the first data and the second data each have a fixed variable name, and the memory addresses of the first data and the second data are not carried in a serial data frame sent by the first chip to the second chip.

In some of these embodiments, the method further comprises:

the first chip judges whether target subdata stored in the second memory area is changed or not, wherein the target subdata comprises one or more groups of subdata of which the group number meets a preset condition;

and under the condition that the target subdata is changed, the first chip interrupts a next serial data frame to be transmitted, and carries the first data, the target subdata and the group number of the target subdata in the next serial data frame to be transmitted to the second chip.

In some embodiments, in a case that there is a change in the target sub-data, the first chip interrupting a next serial data frame to be transmitted, and carrying a group number of the first data, the target sub-data, and the target sub-data in the next serial data frame to be transmitted to the second chip includes:

and under the condition that the target subdata is changed and the duration of the current period does not exceed the preset duration, the first chip interrupts the next serial data frame to be sent, and carries the first data, the target subdata and the group number of the target subdata in the next serial data frame to be sent to the second chip.

In some embodiments, when there is no change in the target sub-data or the duration of the current period exceeds a preset duration, the first chip continues to transmit a next serial data frame to be transmitted.

In some of these embodiments, each serial data frame has an equal frame length with a margin left, the margin being determined based on a longest break time of events that allow breaking communications between the first chip and the second chip.

In some of these embodiments, the serial communication employs an 115200 baud rate, each serial data frame includes 14 16-bit data, each serial data frame is 3.3ms to 4ms in length, and wherein the margin is 0.5ms to 1.2 ms.

In a second aspect, the present application provides a system with a dual chip, including two chips and a serial communication circuit connecting the two chips, where the non-volatile memories of the two chips store computer programs, and the computer programs are executed by the processors of the chips to perform the steps of the dual chip serial communication method according to the first aspect.

To sum up, in the serial communication method with dual chips and the system with dual chips provided in the embodiment of the present application, the first chip is used to obtain at least one group of sub data and a group number of the sub data, which are not successfully sent to the second chip in the current period, in the first data and the second data; the first chip carries the first data, the subdata and the group number of the subdata in a frame of serial data frame and sends the frame of serial data frame to the second chip; and under the condition that the subdata which is not successfully sent to the second chip exists in the current period, sending the next serial data frame until all the subdata in the current period are sent, so that high-speed communication of a large amount of data between the double chips is realized.

Drawings

Fig. 1 is a schematic structural diagram of a system with two chips provided in this embodiment.

Fig. 2 is a flowchart of a serial communication method for a dual chip according to an embodiment of the present disclosure.

Detailed Description

For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings.

For a clearer understanding of the objects, aspects and advantages of the present application, reference is made to the following description and accompanying drawings. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In some instances, well known methods, procedures, systems, components, and/or circuits have been described at a higher level without undue detail in order to avoid obscuring aspects of the application with unnecessary detail. It will be apparent to those of ordinary skill in the art that various changes can be made to the embodiments disclosed herein, and that the general principles defined herein may be applied to other embodiments and applications without departing from the principles and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the scope of the present application as claimed.

Unless defined otherwise, technical or scientific terms used herein shall have the same general meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the terms "a," "an," "the," and the like do not denote a limitation of quantity, but rather are used in the singular or the plural. The terms "comprises," "comprising," "has," "having," and any variations thereof, as referred to in this application, are intended to cover non-exclusive inclusions; for example, a process, method, and system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to the listed steps or modules, but may include other steps or modules (elements) not listed or inherent to such process, method, article, or apparatus.

Reference to "a plurality" in this application means two or more. In general, the character "/" indicates a relationship in which the objects associated before and after are an "or". The terms "first," "second," "third," and the like in this application are used for distinguishing between similar items and not necessarily for describing a particular sequential or chronological order.

The terms "system," "engine," "unit," "module," and/or "block" referred to herein is a method for distinguishing, by level, different components, elements, parts, components, assemblies, or functions of different levels. These terms may be replaced with other expressions capable of achieving the same purpose. In general, reference herein to a "module," "unit," or "block" refers to a collection of logic or software instructions embodied in hardware or firmware. The "modules," "units," or "blocks" described herein may be implemented as software and/or hardware, and in the case of implementation as software, they may be stored in any type of non-volatile computer-readable storage medium or storage device.

In some embodiments, software modules/units/blocks may be compiled and linked into an executable program. It will be appreciated that software modules may be invokable from other modules/units/blocks or from themselves, and/or may be invoked in response to detected events or interrupts. Software modules/units/blocks configured for execution on a computing device may be provided on a computer-readable storage medium, such as a compact disc, digital video disc, flash drive, magnetic disk, or any other tangible medium, or downloaded as digital (and may be initially stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored partially or wholly on a storage device of the executing computing device and applied in the operation of the computing device. The software instructions may be embedded in firmware, such as an EPROM. It will also be appreciated that the hardware modules/units/blocks may be included in connected logic components, such as gates and flip-flops, and/or may be included in programmable units, such as programmable gate arrays or processors. The modules/units/blocks or computing device functions described herein may be implemented as software modules/units/blocks, and may also be represented in hardware or firmware. Generally, the modules/units/blocks described herein may be combined with other modules/units/blocks or, although they are physically organized or stored, may be divided into sub-modules/sub-units/sub-blocks. The description may apply to the system, the engine, or a portion thereof.

It will be understood that when an element, engine, module or block is referred to as being "on," "connected to" or "coupled to" another element, engine, module or block, it can be directly on, connected or coupled to or in communication with the other element, engine, module or block, or intervening elements, engines, modules or blocks may be present, unless the context clearly dictates otherwise. In this application, the term "and/or" may include any one or more of the associated listed items or combinations thereof.

The present embodiment provides a system with two chips, and fig. 1 is a schematic structural diagram of the system with two chips provided in the present embodiment, and as shown in fig. 1, the system includes two chips (referred to as a first chip 10 and a second chip 20, respectively) and a serial communication circuit 30 connecting the two chips. The serial communication circuit is also called a serial communication circuit. Compared with a Serial Peripheral Interface (SPI) communication circuit, the Serial communication circuit has the advantages of simple implementation mode and strong anti-interference capability, and CAN adapt to complex electromagnetic environments near a chip.

Referring to fig. 1, the chip refers to a controller including a nonvolatile memory, a memory, and a Processor, and the controller includes but is not limited to a Micro Controller Unit (MCU), an ARM, a Digital Signal Processor (DSP), or a programmable logic device. The first chip 10 includes a first nonvolatile memory 11, a first processor 12, and a first memory 13, and the second chip 20 includes a second nonvolatile memory 21, a second processor 22, and a second memory 23.

Non-volatile memory may include, among other things, mass storage for data or instructions. By way of example, and not limitation, nonvolatile memory may include a Hard Disk Drive (Hard Disk Drive, abbreviated to HDD), a floppy Disk Drive, a Solid State Drive (SSD), flash memory, an optical Disk, a magneto-optical Disk, tape, or a Universal Serial Bus (USB) Drive, or a combination of two or more of these. Non-volatile memory may include removable or non-removable (or fixed) media, where appropriate. In a particular embodiment, the non-volatile Memory includes Read-Only Memory (ROM). The ROM may be mask-programmed ROM, Programmable ROM (PROM), Erasable PROM (EPROM), Electrically Erasable PROM (EEPROM), Electrically rewritable ROM (EAROM), or FLASH Memory (FLASH), or a combination of two or more of these, where appropriate. The non-volatile memory may be used to store or cache various data files for processing and/or communication purposes, as well as possibly program instructions for execution by the processor.

The Memory may be a Random Access Memory (RAM) or a Cache Memory (Cache).

The processor may be composed of one or more processors, and may include a Central Processing Unit (CPU), or A Specific Integrated Circuit (ASIC), or may be configured to implement one or more Integrated circuits of the embodiments of the present Application.

In the system provided in this embodiment, the nonvolatile memories of the first chip 10 and the second chip 20 store computer programs, and when the computer programs are executed by the processors of the chips, the computer programs execute the dual-chip serial communication method provided in this embodiment.

Taking the above-mentioned computer program stored in the nonvolatile memory of the first chip 10 as an example and not as a limitation, with continuing reference to fig. 1, the computer program 111 may include execution instructions and a database, wherein the database may store configuration information.

In this embodiment, the data to be transmitted is divided into two types, and the related information of the two types of data is written into the database. As an example, table 1 shows an example of configuration information. In the configuration information, data to be transmitted is divided into first data with high priority and second data with low priority, the first data and the second data both have fixed variable names, and the variable names of the data are stored in the configuration information. In addition, for the second data of low priority, it is divided into several groups, each group having a group number, and each group of data is referred to as one sub data of the second data in this embodiment.

Table 1 example of configuration information

When the system executes the above-mentioned serial communication method of the dual chip, the system will initialize according to the above-mentioned configuration information, including applying for the memory area for storing the above-mentioned variable in the memory. Once initialization is complete, the memory address corresponding to each variable is determined. In the initialization process, a first memory area and a second memory area are determined, wherein the first memory area is used for storing first data, and the second memory area is used for storing second data. And each time any update exists in the first data and the second data, the data content stored in the corresponding memory address is updated.

By setting a fixed variable name for each of the first data and the second data and configuring the variable names in the configuration information, the data is transmitted in the order of the variables when the data is transmitted. For the first data, the variable name corresponding to the first data may be determined according to the transmission order of the first data. For the second data, the data in each sub data is also transmitted according to the variable sequence, and when the group number is known, the variable name corresponding to the second data can be determined according to the group number and the transmission sequence of the second data. Therefore, when the first data and the second data are transmitted, the memory addresses of all variables do not need to be transmitted, so that transmission resources are saved, and the data transmission efficiency is improved.

Note that the same configuration information as that in the first chip 10 is also stored in the nonvolatile memory of the second chip 20, so that the second chip 20 can correctly analyze the variable name of each data when receiving the serial data frame transmitted by the first chip 10.

The execution instructions are executed by the processor 12 of the first chip 10 to execute the dual-chip serial communication method provided by the present embodiment. Fig. 2 is a flowchart of a serial communication method for dual chips according to an embodiment of the present application, where as shown in fig. 2, the flowchart includes the following steps:

step S201, the first chip obtains at least one group of subdata and a group number of the subdata, which are not successfully sent to the second chip in the current period, in the first data and the second data.

The memory area of the first chip comprises a first memory area and a second memory area, the first memory area is used for storing first data, the second memory area is used for storing second data, the second data comprises a plurality of groups of subdata, and each group of subdata has a group number.

Step S202, the first chip carries the first data, the sub-data, and the group number of the sub-data in a frame of serial data frame and sends them to the second chip.

Step S203, when there is any sub-data which is not successfully sent to the second chip in the current period, the process jumps to step S201, otherwise, the process jumps to step S204.

Step S204, the transmission of the serial data frame of the current cycle is ended.

Through the steps, a plurality of serial data frames are sent in each period, each serial data frame carries first data and part of second data (namely at least one group of subdata) and carries a group number of the subdata, so that all the first data can be sent to the second chip in each serial data frame, and the first data can be sent to the second chip at the highest priority; and a plurality of serial data frames are adopted to transmit the second data, so that a large amount of second data can be transmitted to the second chip at a lower priority relative to the first data, and high-speed communication of a large amount of data between the double chips is realized under the condition of ensuring high-priority data transmission.

In some of these embodiments, the first data and the second data are transmitted by the first chip to the second chip for a plurality of consecutive transmission periods. After step S204, after the transmission of the serial data frame of the current cycle is finished, the transmission of the serial data frame of the next transmission cycle may be entered. In this way, a continuous transmission of the first data and the second data is achieved.

The sending period in this embodiment refers to a time that all the second data can be completely sent once, and the duration of each sending period may be the same or different.

As for the first data, the first data is transmitted once in each serial data frame regardless of whether the first data stored in the first memory area is changed. It may not be necessary to detect whether the first data was successfully received or parsed by the second chip. Even if the second chip fails to successfully receive or successfully parse the first data in the previous serial data frame, the first data can be parsed in the serial data frame received thereafter as well.

In this embodiment, the second data is transmitted in packets. If a group of sub-data in the second data is not successfully received or analyzed by the second chip and the group of sub-data is not retransmitted, the group of sub-data can be sent again only by waiting for the next sending period, so that the second chip cannot receive the group of sub-data in time. To this end, in some embodiments, the second chip replies to the first chip with a response message after receiving each serial data frame, the response message indicating whether a serial data frame was successfully received. In this way, the first chip can determine whether a certain group of sub-data is successfully sent to the second chip according to the response information. If a group of subdata is unsuccessfully sent to the second chip, the first chip carries the subdata unsuccessfully sent to the second chip in the next (or next) serial data frame, retransmission of the subdata failed in transmission is realized, and the second chip can be ensured to receive all the second data in a sending period in time. When the second data is transmitted in a group, each group of sub-data may be transmitted in sequence according to the sequence of the group number, or each group of sub-data may be transmitted out of order, which is not limited in this embodiment.

In some embodiments, the response information of the second chip carries a group number of the last at least one group of sub data successfully received by the second chip. The first chip may determine whether the sub-data in the previous serial data frame is successfully sent to the second chip by comparing whether the group number carried in the response information is consistent with the group number of the sub-data carried in the previous serial data frame.

In some embodiments, the first chip transmits data to the second chip, the second chip also transmits data to the first chip, and the second chip also transmits data to the first chip in the same transmission manner as in steps S201 to S204. In this case, the first chip may also send a response message to the second chip to indicate whether the first chip receives a certain set of sub-data sent by the second chip.

In the present embodiment, a data format of serial data frames is provided, each serial data frame comprising 14 bytes, wherein N bytes are used to transmit first data, 1 byte is used to transmit protocol status data, 12-N bytes are used to transmit second data, and 1 byte is used to transmit a CRC check value.

Taking N =5 as an example, the data format of the serial data frame for transmitting the a-th group sub data may be represented as:

1: data for variable 1;

2: data for variable 2;

3: data for variable 3;

4: data for variable 4;

5: data for variable 5;

6: protocol status data;

7: data for variable a 1;

8: data for variable a 2;

9: data for variable a 3;

10: data for variable a 4;

11: data for variable a 5;

12: data for variable a 6;

13: data for variable a 7;

14: a CRC check value.

Wherein the protocol state data includes: protocol status, the group number of the sub-data transmitted in the current serial data frame, and the group number of the sub-data successfully received in the previous serial data frame. Protocol states include handshaking, normal communication, failure, etc.

Each group of sub-data in the second data may also have a transmission priority, and if the sub-data with the high priority is changed in the current period, the sub-data to be transmitted in the next serial data frame may be interrupted, and the changed sub-data with the high priority may be transmitted again in the next serial data frame. Therefore, the subdata with high priority in the second data can be guaranteed to be sent to the chip of the opposite end in real time once being changed. Therefore, in some embodiments, the first chip determines whether target sub-data stored in the second memory area has a change, where the target sub-data includes one or more groups of sub-data whose group number meets a preset condition; and under the condition that the target subdata is changed, the first chip interrupts a next serial data frame to be transmitted, and carries the first data, the target subdata and the group number of the target subdata in the next serial data frame to be transmitted to the second chip.

The preset condition is one or more preset group numbers. The group number of the first N groups of sub-data in the second data is generally selected as the preset condition.

In consideration of the extreme situation, if the first N groups of sub-data are frequently changed, the first N groups of sub-data may be repeatedly transmitted in the current period. To avoid this extreme case, on the one hand, the group number of the sub data of high priority may be set to be small, for example, 1 to 3 group numbers. On the other hand, whether to continue to transmit the first N groups of sub data may be determined in a timed manner. For example, when the target sub-data is changed and the duration of the current period does not exceed the preset duration, the first chip interrupts the next serial data frame to be transmitted, and carries the group number of the first data, the target sub-data and the target sub-data in the next serial data frame to be transmitted to the second chip. And when the target subdata is not changed or the duration of the current period exceeds the preset duration, the first chip continues to transmit the next serial data frame to be transmitted.

Taking 4ms for each serial data frame transmission as an example, if the second data is totally divided into 100 groups of sub data, 400ms is required for the second data to be completely transmitted. If it is limited that all the second data are sent within 800ms, the preset time length may be set to 400ms, that is, within the first 400ms of the current period, if one or more sub-data groups in the first N sub-data groups are changed, the changed one or more sub-data groups are sent again; after 400ms of the current period, the changed group or groups of sub-data are not sent again, but other groups of sub-data are sent normally until all the second data are sent, and the time required for sending all the second data is guaranteed not to exceed 800 ms.

Communication interruptions are typically lower in priority than some high priority system interruptions within the system, and therefore, a margin needs to be left in each serial data frame because high priority events within the chip interrupt the transmission of the serial data frame. In the present embodiment, the frame length of each serial data frame is equal and leaves a margin, which is determined based on the longest break time of an event that allows breaking communication between chips, which is determined based on a statistical manner in the chip and its application scenarios.

In the implementation, the serial communication adopts an 115200 baud rate, each serial data frame comprises 14 16-bit data, and the 14 16-bit data can be guaranteed to be transmitted within 2.8ms under the condition that time errors, start and stop bits and the like are considered. In the embodiment, the length of each serial data frame is set to be 3.3ms to 4ms, so that a margin of 0.5ms to 1.2ms can be ensured, and the 14 16-bit data can be completely transmitted to the chip at the opposite end even if communication is interrupted.

Although the above embodiment is described by taking 115200 baud rate and 14 16-bit data transmitted in each serial data frame as an example, it is obvious that the baud rate used in serial communication and the number or bit number of data transmitted in each serial data frame are not limited in this scheme, that is, the baud rate, and the number or bit number of data transmitted in a serial data frame may be selected according to actual needs.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A serial communication method of a dual chip, comprising:

2. The method of claim 1, wherein after the step 2, the method further comprises:

3. The method of claim 2, wherein the response information of the second chip carries a group number of the last at least one group of sub data successfully received by the second chip.

4. The method of claim 1, wherein the first data and the second data each have a fixed variable name, and wherein the memory addresses of the first data and the second data are not carried in a serial data frame sent by the first chip to the second chip.

5. The method of claim 1, further comprising:

6. The method of claim 5, wherein, in the case that the target sub-data is changed, the first chip interrupts a next serial data frame to be transmitted, and carries the first data, the target sub-data, and a group number of the target sub-data in the next serial data frame to be transmitted to the second chip, comprising:

7. The method of claim 6, wherein in case that there is no change in the target sub-data or the duration of the current period exceeds a preset duration, the first chip continues to transmit the next serial data frame to be transmitted.

8. The method of claim 1, wherein each serial data frame has an equal frame length with a margin left, the margin being determined based on a longest break time of events that allow breaking communications between the first chip and the second chip.

9. The method of claim 8, wherein serial communication employs an 115200 baud rate, each serial data frame comprises 14 16-bit data, each serial data frame is 3.3ms to 4ms in length, and wherein the margin is 0.5ms to 1.2 ms.

10. A system with a dual chip comprising two chips and a serial communication circuit connecting the two chips, characterized in that the non-volatile memories of the two chips store a computer program which, when executed by the processors of the chips, performs the steps of the dual chip serial communication method of any of the preceding claims 1 to 9.