CN114116554A - Radar data forwarding architecture and method based on FPGA - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000012545 processing Methods 0.000 claims abstract description 70
- 230000006835 compression Effects 0.000 claims abstract description 35
- 238000007906 compression Methods 0.000 claims abstract description 35
- 238000007781 pre-processing Methods 0.000 claims abstract description 33
- 238000013500 data storage Methods 0.000 claims abstract description 4
- 230000003993 interaction Effects 0.000 claims description 12
- 230000009191 jumping Effects 0.000 claims description 12
- 238000009826 distribution Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 7
- 238000004891 communication Methods 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000005441 aurora Substances 0.000 claims description 3
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- 230000006870 function Effects 0.000 description 18
- 239000002245 particle Substances 0.000 description 12
- 239000013307 optical fiber Substances 0.000 description 11
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- 238000013461 design Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000004904 shortening Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000010606 normalization Methods 0.000 description 1
- 230000010076 replication Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000002054 transplantation Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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-
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
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Abstract
The application belongs to the technical field of data processing, and particularly relates to a radar data forwarding architecture and a forwarding method based on an FPGA. The architecture comprises an FPGA preprocessing module, a plurality of protocol processing units, a DMA controller and a pulse compression unit are configured on the FPGA preprocessing module, and each protocol processing unit, each pulse compression unit and each DMA controller are provided with a parameter configuration register set for parameter configuration; the processor soft core is connected with each parameter configuration register set of the FPGA preprocessing module through an AXI high-speed bus, and comprises: and the data storage reconstruction unit and the data forwarding unit complete data forwarding reconstruction by configuring parameters of a DMA controller, a pulse compression unit and a protocol processing unit of the FPGA preprocessing module. The method and the device can adapt to the radar data in different formats within a very short time, and forward the data according to requirements, so that the development period is shortened.
Description
Technical Field
The application belongs to the technical field of data processing, and particularly relates to a radar data forwarding architecture and a forwarding method based on an FPGA.
Background
The Field Programmable Gate Array (FPGA) is applied more and more widely in the fields of electronics and communication due to high flexibility and rich logic and I/O resources. The traditional FPGA uses Verilog/VHDL language to perform function writing, the program writing is complex, the code readability is poor, and the transplantation is inconvenient. In a radar signal processing system, a data preprocessing function is generally realized in an FPGA (field programmable gate array), but the requirements of data formats returned by different models, data preprocessing and data forwarding are inconsistent, a large amount of manpower is required to be consumed for customized design according to a using method of the traditional FPGA, codes are inconvenient to transplant, the development and debugging time is long, and programs cannot be reused.
Along with the complexity and diversification of the radar system, the forwarding function in the preprocessing module is more and more diversified, and mature functional modules are used in different models, so that the compiling and debugging time of the FPGA is reduced, and the shortening of the design and development period is particularly important.
Disclosure of Invention
In order to solve at least one of the above technical problems, the present application provides an FPGA-based radar data forwarding architecture and a forwarding method.
The application provides a radar data forwarding framework based on FPGA in a first aspect for the data interaction of radar data between radar data acquisition equipment and a plurality of radar data processors, the forwarding framework includes:
the system comprises an FPGA preprocessing module, a plurality of protocol processing units, a DMA controller and a pulse compression unit, wherein the FPGA preprocessing module is provided with the protocol processing units, the DMA controller and the pulse compression unit, each protocol processing unit is used for receiving radar data sent by other equipment from an interface which is correspondingly configured on the FPGA, and performing data interaction with a memory which is configured on the FPGA preprocessing module and the pulse compression unit through the DMA controller, and each protocol processing unit, the pulse compression unit and the DMA controller are provided with a parameter configuration register group for performing parameter configuration on the protocol processing unit, the pulse compression unit and the DMA controller;
the processor soft core is connected with each parameter configuration register set of the FPGA preprocessing module through an AXI high-speed bus, and comprises:
the data storage reconstruction unit is used for configuring parameters of a DMA (direct memory access) controller and a pulse compression unit of the FPGA (field programmable gate array) preprocessing module so as to complete pulse pressure and distribution processing on received radar data and form a plurality of data packets;
and the data forwarding unit is used for configuring parameters of each protocol processing unit so as to complete the forwarding of different data packets to each radar data processor and realize the data receiving and distribution among the FPGA, each processor and the interface.
Preferably, the protocol processing unit includes an SRIO protocol processing unit and an ARUORA protocol processing unit, the SRIO protocol processing unit is configured to control data interaction between the FPGA and an external recorder optical fiber and between the FPGA and an external AD optical fiber, and the ARUORA protocol processing unit is configured to control data interaction between the FPGA and an external AD optical fiber.
Preferably, the parameter configuration register set of each of the protocol processing unit and the pulse compression unit communicates with the processor soft core through a first AXI bus switch.
Preferably, the DMA controller includes a plurality of DMA controllers, each of which communicates with the processor soft core through a second AXI bus switch.
Preferably, the processor soft core comprises a microblaze soft core.
Preferably, the processor soft core divides address spaces for each protocol processing unit, the DMA controller, and the pulse compression unit in a Memory Map manner, and configures each parameter configuration register set through an AXI bus.
Preferably, the FPGA preprocessing module further includes a DDR controller, the FPGA is connected to an external DDR3 memory through the DDR controller, and both the processor soft core and the DMA controller can access the DDR3 memory through the second AXI bus.
A second aspect of the present application provides a radar data forwarding method based on an FPGA, which mainly includes:
step S1, electrifying, the soft core starts to configure DMA controller and each protocol processing unit;
step S2, waiting for data interruption, triggering aurora interruption when detecting a frame header or a packet header, and jumping to step S3 when the soft core receives the interruption;
step S3, detecting whether the received data is a frame header, if so, jumping to step S5, otherwise, jumping to step S4;
step S4, detecting whether the received data is the last packet of the current frame, if so, switching the memory pointer to the frame header receiving buffer area to prepare for receiving the frame header data of the next frame, and sending the current recombined data packet out according to the requirement; if not, the memory pointer is switched to the data receiving buffer area to prepare for receiving the next packet of data, and the current recombined data packet is sent out as required, and the process skips to the step S2 after the end;
step S5, extracting waveform codes, distributing ID, packet data volume key information, and waiting for the completion of the last data transmission; detecting whether the waveform code is abnormal, if so, switching the memory pointer to a frame header receiving buffer area to prepare for re-receiving the frame header, discarding the currently received frame header data, and then jumping to the step S2; if there is no exception, the sub-module parameters are reconfigured, the memory pointer is switched to the data receiving buffer area to prepare for receiving the data packet, and the process goes to step S2.
The method and the device have the advantages that the forwarding of the radar data is realized through the FPGA, the protocol processing units, the DMA controller, the pulse compression unit and the like on the FPGA preprocessing module are configured and reconstructed through the processor soft core, so that the radar data in different formats can be adapted in a very short time, the forwarding processing is carried out according to requirements, the development period is shortened, and the better flexibility and reliability are realized.
The advantages of this reconfigurable technical approach are mainly reflected in:
1) the soft core application, data flow driving, particle module control and interrupt response mechanism are compiled through C codes. The method can realize function reconstruction on the premise of not changing logic codes, improve development efficiency, save development cost, and simultaneously has software flexibility and hardware programmability.
2) The sub-function module is convenient to transplant and can be repeatedly called in different FPGAs.
3) In the face of new algorithm and forwarding requirements, the overall architecture of the FPGA can be basically kept unchanged, functions can be realized by replacing algorithm sub-modules and modifying soft core codes, the development period of new design is shortened, and the production cost is saved.
4) The function of the sub-modules is improved, and the same problems are avoided in different places.
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Fig. 1 is a system hardware structure block diagram of a preferred embodiment of the radar data forwarding architecture based on FPGA in the present application.
Fig. 2 is an interaction diagram of the FPGA preprocessing module and other devices according to the embodiment shown in fig. 1 of the present application.
Fig. 3 is a flowchart illustrating radar data forwarding implemented by the processor soft core according to the embodiment shown in fig. 1.
The system comprises a 1-FPGA preprocessing module and a 2-processor soft core.
Detailed Description
In order to make the implementation objects, technical solutions and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the embodiments of the present application. In the drawings, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The described embodiments are some, but not all embodiments of the present application. The embodiments described below with reference to the drawings are exemplary and intended to be used for explaining the present application, and should not be construed as limiting the present application. All other embodiments obtained by a person of ordinary skill in the art without any inventive work based on the embodiments in the present application are within the scope of protection of the present application. Embodiments of the present application will be described in detail below with reference to the drawings.
The present application provides a radar data forwarding architecture based on FPGA, which is used for data interaction between radar data acquisition devices and a plurality of radar data processors, as shown in fig. 1, the forwarding architecture includes:
the system comprises an FPGA preprocessing module 1, a plurality of protocol processing units, a DMA controller and a pulse compression unit, wherein the FPGA preprocessing module 1 is configured with the protocol processing units, the DMA controller and the pulse compression unit, each protocol processing unit is used for receiving radar data sent by other equipment from an interface which is correspondingly configured on the FPGA, and performing data interaction with a memory which is configured on the FPGA preprocessing module and the pulse compression unit through the DMA controller, and each protocol processing unit, the pulse compression unit and the DMA controller are provided with a parameter configuration register group for performing parameter configuration on the protocol processing unit, the pulse compression unit and the DMA controller;
the processor soft core 2 is connected with each parameter configuration register set of the FPGA preprocessing module 1 through an AXI high-speed bus, and the processor soft core 2 comprises:
the data storage reconstruction unit is used for configuring parameters of a DMA (direct memory access) controller and a pulse compression unit of the FPGA (field programmable gate array) preprocessing module 1 so as to complete pulse pressure and distribution processing on received radar data and form a plurality of data packets;
and the data forwarding unit is used for configuring parameters of each protocol processing unit so as to complete the forwarding of different data packets to each radar data processor and realize the data receiving and distribution among the FPGA, each processor and the interface.
According to the method and the device, functional demand analysis is carried out firstly, each sub-functional module is built in the FPGA according to the demand analysis, including SRIO, DMA and the like, and function and performance testing is carried out. And then calling each sub-function module particle, and building an FPGA hardware platform through a reconfigurable technology. The FPGA soft core realizes different forwarding functions by modifying software codes.
The radar data forwarding refers to distributing radar data acquired by acquisition equipment to different processing equipment according to task requirements, and similarly, processing results (mainly, processing instructions) of different processing equipment need to be forwarded to different acquisition equipment, as shown in fig. 2, the radar data forwarding system provided by the application is a preprocessing module, the module is realized by adopting FPGA hardware and a processor soft core, the equipment acquires radar data from acquisition equipment such as AD optical fibers and recorder optical fibers, the radar data acquired from the AD optical fibers are transmitted through an ARUORA protocol and a radio frequency optical fiber interface, the radar data acquired from the recorder optical fibers are transmitted through an SRIO protocol and a recorder optical fiber interface or an SRIO interface, the data are pre-processed by the system and then distributed to other processing equipment, for example, the data are transmitted to other FPGA/DSP arrays through an SRIO switching network, and the preprocessing module and a master control interface module of the SRIO switching network correspondingly, And each FPGA/DSP processor and the like are transmitted through an SRIO protocol and an SRIO interface.
Returning to fig. 1, in the present application, data received by the acquisition device through each interface is first read through the protocol processing unit, then mapped to the buffer area through the DMA controller, and then processed by the pulse compression unit, such as pulse compression and distribution, and the processed data is sent to other external FPGA/DSP processing devices through the protocol processing unit. The processor soft core is used for changing parameters of the protocol processing unit, the DMA controller and the pulse compression unit according to needs, so that reconstruction of different forwarding functions is realized. The parameters of the protocol processing unit are mainly used for configuring a data receiving party, a data receiving cache address, DMA (direct memory access) data size, interruption and the like, and the parameters of the pulse compression unit are mainly used for realizing the controllable point number, resource and precision of Fourier transform and the controllable internal execution function, such as whether to perform Fourier transform, whether to perform inverse Fourier transform and the like. The parameter configuration register groups are used for storage, can be accessed by reading and writing of the soft core, and are used for testing the functions and the performances of the modules.
The processor soft core initializes the sub-function modules (the protocol processing unit, the DMA controller and the pulse compression unit) through the register. Receiving data, analyzing key parameters such as a waveform code, a frame header, a packet header and a packet tail, data volume, distribution ID and the like, placing the data in different memory cache regions according to requirements, and sending the data out according to the requirements. When the forwarded waveform changes or the requirement is increased, the logic platform does not need to be built again, and the parameters of the protocol processing unit, the DMA controller and the pulse compression unit can be changed only by changing codes in the soft core, so that the function of the FPGA preprocessing module is updated.
The DMA controller of the present application is a unique peripheral that transfers data within the system and can be viewed as a controller that can connect internal and external memory to each DMA capable peripheral over a set of dedicated buses. The DMA controller is adopted, so that the DMA controller has the capability of accessing any required resource without the intervention of the processor, and the data processing resource is saved.
In some optional embodiments, the protocol processing unit includes an SRIO protocol processing unit and an ARUORA protocol processing unit, the SRIO protocol processing unit is configured to control data interaction between the FPGA and an external recorder optical fiber and between the FPGA and an external AD optical fiber.
Referring to fig. 1, the protocol processing unit has a plurality of main units, which are used by the FPGA preprocessing module to implement data communication, and is a dynamically configurable sub-module adopted by the PL side of the FPGA preprocessing module, and the configurable sub-modules include a DMA controller, a pulse compression operator module, a space domain stabilization operator module, and the like, in addition to the SRIO protocol processing module and the ARUORA protocol processing module. These modules are granular partitioned according to the technical model, existing as protocol middleware and computing middleware. For vector operation, the parallel advantage of the FPGA is fully considered, and the accelerated particle design of specific vector operation is realized by adopting a production line, resource replication and ping-pong cache mode.
In some optional embodiments, the parameter configuration register set of each of the protocol processing unit and the pulse compression unit communicates with the processor soft core 2 through a first AXI bus switch.
In some optional embodiments, the DMA controller comprises a plurality, each of the DMA controllers in communication with the processor soft core 2 through a second AXI bus switch.
It can be understood that the first AXI bus switch communication duplex mainly completes modification of parameters of each protocol processing unit, and the second AXI bus switch communication duplex mainly completes processing on a data FPGA.
In some alternative embodiments, the processor soft core 2 comprises a microblaze soft core. The MicroBlaze embedded soft core is a RISC processor soft core which is optimized by Xilinx company and can be embedded in FPGA, and has the advantages of high running speed, less occupied resources, strong configurability and the like.
In some optional embodiments, the processor soft core divides an address space for each protocol processing unit, the DMA controller, and the pulse compression unit by means of a Memory Map, and configures each parameter configuration register set through an AXI bus.
In this embodiment, each particle module is interconnected with the soft-core processor at high speed through the AXI bus switch, each particle has a parameter configuration register set, the soft core divides an address space for each particle in a Memory Map manner, the particle register sets are configured through the AXI bus, the particle functions can be rapidly reconstructed, and the reconstruction time can be completed within 1 ms.
In some optional embodiments, the FPGA preprocessing module 1 further comprises a DDR controller, and the DDR controller is configured to send data of the DMA controller to a buffer through a DDR interface.
In this embodiment, all parameters required for implementing the model exist as a structural body, software code normalization is implemented, function definition is clear, software code portability is improved, and the parameter configuration function is responsible for completing transmission of structural body data to each particle configuration register group. By mounting the DDR controller, the Memory Map space of the processor is expanded, and meanwhile, a large-bandwidth data caching function is provided. The maximum read-write bandwidth of DDR is about 10GB/s, the soft core can apply for and release the cache space in real time, and the cache requirement of data processing is guaranteed.
In a second aspect of the present application, a radar data forwarding method based on FPGA is provided, as described above, the radar data is sent from an external acquisition device in a form of a data packet with a plurality of packet bodies in a packet header, where data forwarding refers to splitting the data packet according to total requirements and capabilities of different processors, where each packet header carries one packet body to form a new data packet, and the new data packet is sent to other processing devices. The sending process is realized by configuring each protocol processing unit through the soft core, and the processing process is realized by configuring the DMA controller and the pulse compression unit through the soft core.
For example, the received radar data format: frame header + pack 1+ pack 2+. pack n + frame header + pack 1+ pack 2+. pack n. Each package consists of: header + data.
The radar data format ultimately distributed to the various processors is:
frame header + packet 1; frame header + packet 2; frame header + packet 3; header + packet 4 … ….
As shown in fig. 3, the radar data forwarding method based on the FPGA mainly includes:
step S1, power up, the soft core starts configuring sub-modules (i.e. programmable logic particles), here including DMA, SRIO, etc.
Step S2, waiting for data interruption, triggering aurora interruption when detecting the frame head or the packet head, and the soft core jumping to step S3 after receiving the interruption.
And step S3, detecting whether the received data is a frame header, if so, jumping to step S5, otherwise, jumping to step S4.
Step S4, detecting whether the received data is the last packet of the current frame, if so, switching the memory pointer to the frame header receiving buffer area to prepare for receiving the frame header data of the next frame, and sending the current recombined data packet out according to the requirement; if not, the memory pointer is switched to the data receiving buffer area to prepare for receiving the next packet of data, and the current recombined data packet is sent out according to the requirement. Ending jumping to step S2;
and step S5, extracting key information such as waveform codes, distribution IDs, packet data volumes and the like, and waiting for the completion of the last data transmission. Detecting whether the waveform code is abnormal. If the abnormal condition exists, the memory pointer is switched to a frame header receiving buffer area to prepare for re-receiving the frame header, the currently received frame header data is lost, and then the step S2 is skipped; if there is no exception, the sub-module parameters are reconfigured, the memory pointer is switched to the data receiving buffer area to prepare for receiving the data packet, and the process goes to step S2.
Wherein the addresses allocated to the frame header receiving buffer and the data receiving buffer are adjacent to each other in a memory. And the current packet sending means sends the current frame header receiving buffer zone and the data receiving buffer zone data out by the current finger at one time to complete the reconstruction of the radar data packet.
The application realizes the change of the function through the soft core, and completes the replacement through increasing and decreasing the particles or the particles, thereby shortening the development period and reducing the complexity of test verification.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (8)
1. An FPGA-based radar data forwarding architecture for data interaction of radar data between a radar data acquisition device and a plurality of radar data processors, the forwarding architecture comprising:
the system comprises an FPGA preprocessing module (1), a plurality of protocol processing units, a DMA controller and a pulse compression unit are configured on the FPGA preprocessing module, each protocol processing unit is used for receiving radar data sent by other equipment from an interface which is correspondingly configured on the FPGA, and performing data interaction with a memory which is configured on the FPGA preprocessing module and the pulse compression unit through the DMA controller, and each protocol processing unit, the pulse compression unit and the DMA controller are provided with parameter configuration register groups for performing parameter configuration on the protocol processing unit, the pulse compression unit and the DMA controller;
the processor soft core (2) is connected with each parameter configuration register set of the FPGA preprocessing module (1) through an AXI high-speed bus, and the processor soft core (2) comprises:
the data storage reconstruction unit is used for configuring parameters of a DMA (direct memory access) controller and a pulse compression unit of the FPGA (field programmable gate array) preprocessing module (1), so that pulse pressure and distribution processing of received radar data are completed, and a plurality of data packets are formed;
and the data forwarding unit is used for configuring parameters of each protocol processing unit so as to complete the forwarding of different data packets to each radar data processor and realize the data receiving and distribution among the FPGA, each processor and the interface.
2. The FPGA-based radar data forwarding architecture of claim 1, wherein the protocol processing units include an SRIO protocol processing unit for controlling data interaction between the FPGA and an external recorder fiber, each radar data processor, and an ARUORA protocol processing unit for controlling data interaction between the FPGA and an external AD fiber.
3. The FPGA-based radar data forwarding architecture of claim 1, wherein a parameter configuration register set of each of the protocol processing units and pulse compression units communicates with the processor soft core (2) through a first AXI bus switch.
4. The FPGA-based radar data forwarding architecture of claim 1 wherein the DMA controller comprises a plurality, each of the DMA controllers in communication with the processor soft core (2) through a second AXI bus switch.
5. The FPGA-based radar data forwarding architecture of claim 1 wherein the processor soft core (2) comprises a microblaze soft core.
6. The FPGA-based radar data forwarding architecture of claim 1, wherein the processor soft core partitions address spaces for the protocol processing units, the DMA controller, and the pulse compression unit in a Memory Map manner, and configures the parameter configuration register sets through an AXI bus.
7. The FPGA-based radar data forwarding architecture of claim 1, wherein the FPGA preprocessing module (1) further comprises a DDR controller, the FPGA is connected with an external DDR3 memory through the DDR controller, and both the processor soft core and the DMA controller can access the DDR3 memory through the second AXI bus.
8. A radar data forwarding method based on FPGA is characterized by comprising the following steps:
step S1, electrifying, the soft core starts to configure DMA controller and each protocol processing unit;
step S2, waiting for data interruption, triggering aurora interruption when detecting a frame header or a packet header, and jumping to step S3 when the soft core receives the interruption;
step S3, detecting whether the received data is a frame header, if so, jumping to step S5, otherwise, jumping to step S4;
step S4, detecting whether the received data is the last packet of the current frame, if so, switching the memory pointer to the frame header receiving buffer area to prepare for receiving the frame header data of the next frame, and sending the current recombined data packet out according to the requirement; if not, the memory pointer is switched to the data receiving buffer area to prepare for receiving the next packet of data, and the current recombined data packet is sent out as required, and the process skips to the step S2 after the end;
step S5, extracting waveform codes, distributing ID, packet data volume key information, and waiting for the completion of the last data transmission; detecting whether the waveform code is abnormal, if so, switching the memory pointer to a frame header receiving buffer area to prepare for re-receiving the frame header, discarding the currently received frame header data, and then jumping to the step S2; if there is no exception, the sub-module parameters are reconfigured, the memory pointer is switched to the data receiving buffer area to prepare for receiving the data packet, and the process goes to step S2.
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