CN110362512B - SCA and SDR-oriented rapid system reconstruction method - Google Patents
SCA and SDR-oriented rapid system reconstruction method Download PDFInfo
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Abstract
The invention discloses a rapid system reconstruction method facing SCA and SDR, the system is composed of a main control module and a waveform module, the main control module and the waveform module are interconnected and communicated through a VPX bus of a backboard, a PCIE X45.0GT/s interface is adopted, an X86 hardware platform of the main control module is used as a root component RC of the PCIE interface, a ZYNQ chip of the waveform module is used as PCIE interface terminal equipment EP, wherein the main control module comprises an X86 hardware platform, an operating system, SCA Core Framework (CF), CORBA Middleware (CORBA), SCA Device, POSIX AEP and SCA Applications, the SCA Device comprises a driver of the waveform module, the waveform module comprises ZYNQ series, FPGA7 series, DDR and other chips, the interface between the ZYNQ and the FPGA7 comprises SelectMAP, LVDS, SRIO and the like, and the external memory of the ZYNQ is a large-capacity DDR. The invention comprehensively utilizes the technologies and resources of a high-speed bus, PCIE and SRIO interfaces, DMA, an interrupt mechanism, a large-capacity DDR and the like, and realizes the rapid reconfiguration of the FPGA waveform, the rapid configuration of waveform parameters, the real-time return of waveform states and the high-speed transmission of waveform data.
Description
Technical Field
The invention relates to the technical field of software communication architecture and software radio, in particular to a rapid system reconstruction method oriented to SCA and SDR.
Background
SCA is a standard architecture defined for software radio SDR, supporting development of SDR communication systems to make waveform application software easier to migrate across wireless level platforms, and provides a unique way for waveform software and other elements of a software radio to interact with hardware. By normalization, waveforms are compatible, not only for one platform, but also for any device supporting SCA. Waveform software can be used with many different radios, whether handheld or other communication devices.
The SCA creates SCA domain configuration file elements through a set of XML description files with complex semantics by defining a core framework interface and application program environment description (AEP) so that waveform software has good portability and reusability, and the SCA is used for identifying functions, attributes, interdependencies and positions of hardware devices and software components in an SCA compatible system. The general SCA system comprises GPP, DSP, FPGA chips, and GPP, DSP, FPGA chips in the system need to be reconfigured to complete system reconfiguration when system deployment and waveform loading are performed.
Along with the continuous expansion of GPP, DSP, FPGA chip scale, the configuration file is larger and larger, the time spent for completing configuration has seriously affected the performance of SCA system reconstruction, and according to the current research situation, the time requirement of a user on system reconstruction cannot be met by adopting a single optimization method, and the rapid system reconstruction must be realized by comprehensively designing in terms of architecture, interfaces and flow.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides a rapid system reconstruction method for SCA and SDR, which comprehensively utilizes technologies and resources such as a high-speed bus, PCIE and SRIO interfaces, DMA, an interrupt mechanism, a large-capacity DDR and the like to realize rapid waveform reconfiguration of an FPGA, rapid configuration of waveform parameters, real-time return of waveform states and high-speed transmission of waveform data.
In order to achieve the above purpose, the invention adopts the following technical scheme:
a rapid system reconstruction method facing SCA and SDR comprises a main control module and a waveform module, wherein the main control module and the waveform module are interconnected and communicated through a VPX bus of a backboard, an interface adopts PCIE X4.0 GT/s, an X86 hardware platform of the main control module is used as a root component RC of a PCIE interface, a ZYNQ chip of the waveform module is used as PCIE interface terminal equipment EP, the main control module comprises an X86 hardware platform, an operating system, SCA Core Framework (CF), CORBA Middleware (CORBA), SCA Device, POSIX AEP and SCA Applications, the SCA Device comprises a driver of the waveform module, the waveform module comprises chips such as ZYNQ series, FPGA7 series, DDR and the like, the interface between the ZYNQ and the FPGA7 comprises SelectMAP, LVDS, SRIO and the like, and an external memory of the ZYNQ is a large-capacity DDR.
For further description of the present invention, the waveform module ZYNQ chip internal program includes ZYNQ7Processing System (PS), 3 AXI interconnects, 3 AXI BRAM Controller, AXI Memory Mapped PCI Express (M2 PCIE), AXI Central Direct Memory Access (CDMA), AXI select map, DDR, BRAM, data read/write control logic, interrupt control logic function module, wherein ZYNQ7Processing System (PS) interconnects with AXI interconnects 1 via an m_axi_gpo interface to access address space of M2PCIE, CDMA, selectMAP, AXI BRAM Controller1, data read/write control logic, AXI Memory Mapped PCI Express (M2 PCIE) interconnects with AXI interconnects 3 via AXI bus to access address space of DDR, AXI BRAM Controller2, AXI BRAM Controller3, AXI Central Direct Memory Access (CDMA) interconnects with AXI interconnects 2 via AXI bus, and cascades with AXI interconnects 1 and AXI interconnects 3 to access address space of M2PCIE, selectMAP, AXI BRAM Controller, AXI BRAM Controller3, data read/write control logic, and connects with AXI interconnects 4 (ps_pcis) via AXI bus to address space of AXI Interconnect3 via AXI bus to implement address space of AXI Interconnect 29, AXI BRAM Controller via a corresponding to address space of PS 4 (ps_pcis) interface and address space of AXI Interconnect AXI BRAM Controller.
For further description of the present invention, the BAR address of AXI Memory Mapped PCI Express (M2 PCIE) maps the address spaces of DDR, AXI BRAM Controller, and AXI BRAM Controller3, respectively, and the three address spaces are directly accessed through the BAR address of PCIE by the master control module.
For further description of the present invention, the PCIE interface of AXI Memory Mapped PCI Express (M2 PCIE) is interconnected with the PCIE interface of the main control module, the AXI SelectMAP is interconnected with the SelectMAP interface of the FPGA7, AXI BRAM Controller3 is interconnected with the LVDS interface of the FPGA7, the data read-write control logic is interconnected with the SRIO interface of the FPGA7, and PS configures registers of the data read-write control logic.
The invention is further described, comprising two interrupt mechanisms, namely a main control module PCIE MSI interrupt mechanism and PS interrupt control logic, wherein when ZYNQ sends a specific TLP packet to the main control module through a PCIE interface to trigger MSI interrupt of the main control module PCIE, a corresponding interrupt service routine will clear the interrupt, when the main control module writes data to a specific address of AXI BRAM Controller2 of ZYNQ through the PCIE interface, the PS interrupt control logic will trigger PS interrupt, and when PS reads data from a specific address of AXI BRAM Controller through an AXI bus, the PS interrupt control logic will clear PS interrupt.
The invention is further described as comprising two data streams, namely a downstream data stream from the main control module to the ZYNQ or FPGA7 and an upstream data stream from the ZYNQ or FPGA7 to the main control module.
For further description of the present invention, the BRAM includes two special 32-bit registers, namely a master control status register (address 0) and a PS control status register (address 4), for the exchange of control and status information in the system, where the registers define a flag (1 bit), a read/write flag (1 bit), a control command (6 bits), a data type (8 bits), and a data length (16 bits) according to bits.
The invention is further described and comprises 4 data types, namely an FPGA7BIT file, a parameter file, waveform parameters, state data and waveform input and output data;
the invention is further described and comprises 6 data processing flows, namely a BIT file, a configuration parameter file, a configuration waveform parameter, a waveform reading state, waveform data input and waveform data output flow for configuring an FPGA7 chip respectively.
The invention is further described, wherein the flow of the BIT file of the FPGA7 chip comprises the following steps:
(101): PS has finished the system initialization in waiting for the state that the interrupt triggers, SCA device driver program of the main control module opens FPGA7BIT file, and write the file data into PCIE BAR0 address space, write the data into DDR of the waveform module through BAR address mapping of M2PCIE module;
(102): the master control module driver writes the written data length, the data type (FPGA BIT file), the control command (configuration FPGA), the read/write flag (write) and the completion flag (Y) into a register of address 0 of PCIE BAR1 (a master control state register, actually a 32-BIT space of address 0 of BRAM) to enter an MSI interrupt triggering state waiting for PCIE; the operation of the driver program writing the control state register of the master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service routine of PS reads the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to acquire file data length, data type, control command, read/write mark and completion mark, meanwhile, the interrupt control logic module clears the interrupt bit, and the interrupt service routine reads the file data in DDR by configuring the CDMA module to start a DMA mode and stores the file data in a Linux file system;
(103): writing the read data length, a read/write flag (read) and a completion flag (Y) into a register (a control state register of the PS, which is actually a 32-bit space of an address 4 of a BRAM) with an address 4 of AXI BRAM Controller by a program of the PS, and writing a TLP packet of an MSI interrupt to a PCIE interface through an M2PCIE module, wherein the packet triggers the main control PCIE MSI interrupt and runs a PCIE interrupt service routine, the PCIE interrupt service routine clears an interrupt bit, reads the register (which is actually the 32-bit space of the address 4 of the BRAM) of the address 4 of the PCIE BAR1 to acquire related information set by the PS program, and entering a trigger state to be interrupted again after the program of the PS writes the register;
(104): after the host module driver finishes downloading the BIT file, writing a command for configuring the FPGA into a control state register of the host, wherein the control state register comprises a configuration file name and a mark; meanwhile, the interrupt control logic module triggers PS interrupt, the interrupt service routine reads a control state register of the main control to acquire parameters configuring the FPGA7, then opens a BIT file of the FPGA7, starts DMA to write file data into the AXI select MAP module, and checks a mark of successful configuration of the FPGA;
(105): writing configuration results into a control state register of the PS by a program of the PS, wherein the configuration results comprise flag state parameters for whether the FPGA is configured successfully, writing a TLP packet of an MSI interrupt to a PCIE interface through an M2PCIE module to trigger a main control PCIE MSI interrupt, clearing interrupt BITs by a main control PCIE interrupt service routine, reading the control state register of the PS to obtain the FPGA configuration state parameters, and ending the configuration of the FPGA7BIT file;
the waveform data input flow comprises the following steps:
(201): PS has finished the system initialization in waiting for interrupt to trigger the state, SCA device driver of the main control module opens the waveform input file, and write the file data into PCIE BAR0 address space, the data is written into DDR of the waveform module directly in fact;
(202): the master control module driver writes the written data length, the data type (waveform data file), the control command (data input), the read/write mark (write) and the completion mark (Y) into a register (master control state register) of address 0 of the PCIE BAR1, and enters an MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service routine of PS reads the register (32 bits) of BRAM address 0 through AXI BRAM Controller to obtain the file data length, data type, control command, read/write mark and completion mark, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service routine sets the register of the data read/write logic module, sets the data direction, length and whether to circulate mark, and then the CDMA module is configured to start the DMA mode to read the file data in DDR, and the file data is sent to the SRIO interface (input to waveform) of the data read/write control logic module;
(203): the PS program writes the read data length, the read/write flag (read) and the completion flag (Y) into a AXI BRAMController register (control status register of the PS) with the address of 4, writes a TLP packet of MSI interrupt to a PCIE interface through an M2PCIE module, triggers the main control PCIE MSI interrupt and runs a PCIE interrupt service routine, clears interrupt bits, reads the register with the address of 4 of PCIE BAR1 and acquires related information set by the PS program;
(204): the read-write control logic module judges a cyclic read-write mark, if the cyclic write mark is cyclic write, the DMA mode is started to read data in the DDR after the data is written, the data is sent to the waveform through the SRIO until the cyclic write is exited, and the process of inputting the waveform data is ended;
the waveform data output flow comprises the following steps:
(301): the PS has completed the initialization of the system and is in a state of waiting for interrupt triggering, the SCA device driver of the main control module starts a waveform reading output data process, writes a data length to be read, a data type (waveform data file), a control command (data output), a reading/writing mark (reading) and a completion mark (N) into a register (a main control state register) of address 0 of the PCIE BAR1, and enters an MSI interrupt triggering state of waiting for PCIE;
(302): the operation of the control state register of the driver write master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service routine of PS acquires file data length, data type, control command, read/write mark and completion mark by reading the register (32 bits) of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears interrupt bit, the interrupt service routine sets the register of the data read/write logic control module, sets data direction, length and whether to circulate mark, and then starts data read/write logic control to read data from the SRIO interface to DDR;
(303): the PS program writes the read data length, the read/write flag (read) and the completion flag (Y) into a AXI BRAM Controller register (control status register of the PS) with the address of 4, writes a TLP packet of MSI interrupt to a PCIE interface through an M2PCIE module, triggers the main control PCIE MSI interrupt and runs a PCIE interrupt service routine, clears interrupt bits, reads the register with the address of 4 of PCIE BAR1 and acquires related information set by the PS program;
(304): the driver program starts the DMA mode to read the waveform output data in the PCIE BAR0 (DDR), judges the cyclic read-write mark, if the cyclic read is the cyclic read, starts the DMA mode to read the data in the PCIE BAR0 after the data is read, and ends the process of outputting the waveform data until the cyclic read is exited.
Compared with the prior art, the invention has the advantages that: and the technology and resources such as a high-speed bus, PCIE and SRIO interfaces, DMA, an interrupt mechanism, a large-capacity DDR and the like are comprehensively utilized, so that the rapid reconfiguration of the FPGA waveform, the rapid configuration of waveform parameters, the real-time return of waveform states and the high-speed transmission of waveform data are realized.
Drawings
FIG. 1 is a system architecture diagram of the method of the present invention.
Fig. 2 is a connection diagram of internal functional modules of the ZYNQ according to the method of the present invention.
FIG. 3 is a flow chart for configuring an FPGA7BIT file.
FIG. 4 is a flow chart of configuration waveform parameters and read waveform states.
Fig. 5 is a waveform data input flow chart.
Fig. 6 is a waveform data output flow chart.
Detailed Description
The following description of the embodiments of the present invention will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1:
as shown in FIG. 1, the verification system of the invention consists of a main control module and a waveform module, and is interconnected and communicated through the VPX bus of the backboard, adopts a PCIE interface and is configured as X4.5.0 GT/s.
The main control module comprises a hardware platform of an X86 architecture, a core framework CF for running an operating system and SCA, CORBA middleware and waveform application of the SCA, POSIX compatible application program environment description AEP provides standard application program function interface API for the waveform application of the SCA, device under the control of an SCA Device manager provides driving and proxy functions for an FPGA7 chip in the waveform module, the driving realizes an access interface to each hardware resource in the waveform module, and the proxy realizes a management interface of the SCA to the Device, wherein the management interface comprises Device initialization (initialization), loading program (load), running program (execute), configuration parameter (configuration), query state (termination), unloading program (unloading), release object (release object) and the like. The X86 hardware platform comprises a root component RC of the PCIE interface, and realizes communication and configuration of the PCIE interface of the waveform module.
The waveform module mainly comprises ZYNQ series and FPGA7 series FPGA chips, high-capacity DDR chips and the like. The interfaces between ZYNQ and FPGA7 mainly comprise SelectMAP, LVDS, SRIO and the like, the SelectMAP interface realizes the waveform reconfiguration of ZYNQ to the FPGA7 chip, the differential LVDS interface realizes the waveform parameter configuration and waveform state query of ZYNQ to the FPGA7 chip, and the SRIO interface is used as a waveform data input and output interface and is communicated with the PCIE interface of the main control module through the PCIE interface terminal equipment EP of the ZYNQ. DDR is used as a transfer device of data and large files, and is mapped onto BAR0 of a PCIE interface of a main control module through a PCIE interface of ZYNQ.
The functional modules and connection relations in the ZYNQ are shown in FIG. 2, and mainly comprise a PS (ZYNQ 7Processing System), a bus interconnection module (AXI Interconnect), a block memory controller (AXI BRAM Controller), an M2PCIE memory mapping module (AXI Memory Mapped PCI Express), a CDMA module (AXI Central Direct Memory Access), a SelectMAP interface module (AXI SelectMAP), DDR, BRAM, a data read-write control logic module and an interrupt control logic module.
During design, firstly configuring system parameters of PS, including parameters of DDR configuration, parameters of GPO (M_AXI_GPO) interface configuration, parameters of HPO (S_AXI_HPO) interface bit width configuration and parameters of interrupt triggering; and adding each functional module to the project, connecting interfaces of each functional module and configuring corresponding parameters, wherein the width of the AXI bus is 32 bits in the embodiment. PS is connected with an AXI bus slave port of AXIINTERCONECt 1 through a master port M_AXI_GPO of the GPO, is connected with an AXI bus master port of AXI Interconnect2 through a slave port of the HPO, and the output of the interrupt control logic is connected with an interrupt request of PS (corresponding to PL to PS interrupt numbers); an AXI bus main port of the AXI Interconnect1 is respectively connected with AXI bus slave ports of 5 modules of CDMA, M2PCIE, AXI BRAM Controller1, AXI SelectMAP and data read-write control logic, and PS is supported to access 5 module address spaces. The PCIE interface of the M2PCIE module is interconnected with the PCIE interface of the main control module through a VPX bus, an AXI bus main port is connected with an AXI bus slave port of AXI Internect 3, the AXI bus main port of AXI Internect 3 is respectively connected with AXI bus slave ports of DDR, AXI BRAM Controller2 and AXI BRAM Controller3, parameters of the M2PCIE module are configured, a channel is X4, the bandwidth rate is 5.0GT/s,3 BAR addresses are mapped to address spaces of DDR, AXI BRAM Controller2 and AXI BRAM Controller3 respectively, and the main control module can directly access the address spaces of DDR, AXI BRAM Controller2 and AXI BRAMController through the PCIE interface. The AXI bus main port of the CDMA module is connected with the AXI bus slave port of the AXI Internect 2, the AXI bus main port of the AXI Internect 2 is cascaded with the AXI Internect 1 and the AXI Internect 3 and is connected with the HPO slave port of the PS, and the access of the CDMA to the address space of the DDR, M2PCIE, selectMAP, AXI BRAM Controller1, AXI BRAM Controller3 and the data read-write control logic module is realized. The AXI SelectMAP module is directly connected with the FPGA7 through a SelectMAP interface, the AXI BRAM Controller module is connected with the FPGA7 through an LVDS interface, and the data read-write control logic module is connected with the FPGA7 through an SRIO interface. Two ports of the BRAM are respectively connected with AXI BRAM Controller and AXI BRAM Controller, so that the main control module accesses the address space of the same BRAM through a PCIE interface and PS through an AXI bus, and the first 8 bytes in the BRAM are used as a control state register and a control state register of the main control module
The method comprises the steps that a SelectMAP module is used for configuring an FPGA7BIT file to be divided into two stages, wherein the first stage is for downloading the BIT file, and the second stage is for configuring the FPGA; the whole configuration process needs to be carried out by matching the SCA device driver of the main control module with the program in the PS, and the detailed steps are shown in FIG. 3:
the first step: PS has finished the system initialization in waiting for the state that the interrupt triggers, SCA device driver of the main control module opens FPGA7BIT file, and write the file data into PCIE BAR0 address space, actually through BAR address mapping of M2PCIE module, the data is written into DDR of the waveform module directly;
and a second step of: the master control module driver writes the written data length, the data type (FPGA BIT file), the control command (configuration FPGA), the read/write flag (write) and the completion flag (Y) into a register of address 0 of PCIE BAR1 (a master control state register, actually a 32-BIT space of address 0 of BRAM) to enter an MSI interrupt triggering state waiting for PCIE; the operation of the driver program writing the control state register of the master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service routine of PS reads the register (32 bits) of BRAM address 0 through AXI BRAM Controller1 to obtain file data length, data type, control command, read/write mark, completion mark and the like, meanwhile, the interrupt control logic module clears the interrupt bit, and the interrupt service routine reads the file data in DDR by configuring the CDMA module to start a DMA mode and stores the file data in a Linux file system;
and a third step of: writing the read data length, a read/write flag (read), a completion flag (Y) and the like into a register (a control state register of the PS, which is actually a 32-bit space of an address 4 of a BRAM) with an address 4 of AXI BRAM Controller by a program of the PS, writing a TLP packet of MSI interrupt to a PCIE interface through an M2PCIE module, triggering PCIE MSI to be controlled by the packet and running a PCIE interrupt service routine, clearing interrupt bits by the PCIE interrupt service routine, reading the register (which is actually the 32-bit space of the address 4 of the BRAM) with the address 4 of the PCIE BAR1 to obtain related information set by the PS program, and entering a waiting interrupt triggering state again after the program of the PS is written into the register;
fourth step: after the host module driver finishes downloading the BIT file, writing a command for configuring the FPGA into a control state register of the host, wherein the control state register comprises a configuration file name, a mark and the like; meanwhile, the interrupt control logic module triggers PS interrupt, the interrupt service routine reads a control state register of the main control to acquire parameters configuring the FPGA7, then opens a BIT file of the FPGA7, starts DMA to write file data into the AXI select MAP module, and checks a mark of successful configuration of the FPGA;
fifth step: the PS program writes configuration results into a control state register of the PS, wherein the configuration results comprise parameters such as a flag state for whether the FPGA is configured successfully or not, a TLP packet for MSI interrupt is written into a PCIE interface through an M2PCIE module to trigger the main control PCIE MSI interrupt, a main control PCIE interrupt service routine clears interrupt BITs and reads the control state register of the PS to acquire parameters such as the FPGA configuration state, and the configuration of the FPGA7BIT file is finished.
The BAR2 of the main control module PCIE maps AXI BRAM Controller3 address space through the M2PCIE module, and implements configuration waveform parameters and reading waveform forms through the LVDS interface, and the detailed flow is shown in fig. 4:
the SCA device driver of the main control module firstly opens a waveform parameter file, then writes the waveform parameter file into a BAR2 address space according to addresses through a PCIE interface, and then outputs a clock, addresses, parameter data and write enable signals to an LVDS interface by a AXI BRAM Controller3 module, and the driver completes configuration of waveform parameters;
the SCA device driver of the main control module reads waveform, firstly reads BAR2 address space according to address through PCIE interface, AXI BRAM Controller module outputs clock, address, read enable signal to LVDS interface, returns corresponding value of parameter address to PCIE interface when next clock rising edge comes, and the driver completes reading waveform.
The BAR0 of the main control module PCIE maps the DDR address space through the M2PCIE module, and the SCA device driver writes to the PCIE interface BAR0 address space to implement waveform data input, and the detailed flow is shown in fig. 5:
the first step: PS has finished the system initialization in waiting for interrupt to trigger the state, SCA device driver of the main control module opens the waveform input file, and write the file data into PCIE BAR0 address space, the data is written into DDR of the waveform module directly in fact;
and a second step of: the master control module driver writes the written data length, the data type (waveform data file), the control command (data input), the read/write mark (write) and the completion mark (Y) into a register (master control state register) of address 0 of the PCIE BAR1, and enters an MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service routine of PS reads the register (32 bits) of BRAM address 0 through AXI BRAM Controller to obtain file data length, data type, control command, read/write mark, completion mark and the like, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service routine sets the register of the data read/write logic module, after setting the marks of data direction, length, whether to circulate and the like, the interrupt service routine starts a DMA mode to read the file data in DDR through configuring a CDMA module, and sends the file data to an SRIO interface (input to waveform) of the data read/write control logic module;
and a third step of: the program of the PS writes the read data length, read/write flag (read), completion flag (Y) and the like into a register (control status register of the PS) with address 4 of AXI BRAM Controller, writes a TLP packet of MSI interrupt to a PCIE interface through an M2PCIE module, triggers main control PCIE MSI interrupt and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads the register with address 4 of PCIE BAR1 and acquires related information set by the PS program;
fourth step: the read-write control logic module judges a cyclic read-write flag, if the cyclic write flag is cyclic write, the DMA mode is started to read data in the DDR after the data is written, the data is sent to waveforms through SRIO until the cyclic write is exited, and the process of inputting waveform data is ended.
The SCA device driver realizes waveform data output by reading from the PCIE interface BAR0 address space, and the detailed flow is as shown in fig. 6:
the first step: the PS has completed the initialization of the system and is in a state of waiting for interrupt triggering, the SCA device driver of the main control module starts a waveform reading output data process, writes a data length to be read, a data type (waveform data file), a control command (data output), a reading/writing mark (reading) and a completion mark (N) into a register (a main control state register) of address 0 of the PCIE BAR1, and enters an MSI interrupt triggering state of waiting for PCIE;
and a second step of: the operation of the control state register of the drive program writing master control causes the interrupt control logic module to trigger PS interrupt, the interrupt service program of PS acquires file data length, data type, control command, read/write mark, completion mark and the like by reading the register (32 bits) of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read/write logic control module, and after setting the marks of data direction, length, whether circulation and the like, starts the data read/write logic control to read data from the SRIO interface to DDR;
and a third step of: the program of the PS writes the read data length, read/write flag (read), completion flag (Y) and the like into a register (control status register of the PS) with address 4 of AXI BRAM Controller, writes a TLP packet of MSI interrupt to a PCIE interface through an M2PCIE module, triggers main control PCIE MSI interrupt and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads the register with address 4 of PCIE BAR1 and acquires related information set by the PS program;
fourth step: the driver program starts the DMA mode to read the waveform output data in the PCIE BAR0 (DDR), judges the cyclic read-write mark, if the cyclic read is the cyclic read, starts the DMA mode to read the data in the PCIE BAR0 after the data is read, and ends the process of outputting the waveform data until the cyclic read is exited.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature "above" and "over" a second feature includes a first feature that is "above" and diagonally above, or simply indicates that the first feature is higher in level than the second feature, and a first feature "below" and "beneath" a second feature includes a first feature that is "above" and diagonally above, or simply indicates that the first feature is lower in level than the first feature.
In the description of the present invention, a description with reference to the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention, and in the description, schematic representations of the terms described above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention.
Claims (6)
1. A rapid system reconstruction method facing SCA and SDR is characterized in that the system is composed of a main control module and a waveform module, the main control module and the waveform module are interconnected and communicated through a VPX bus of a backboard, an interface adopts PCIE X4.0 GT/S, an X86 hardware platform of the main control module is used as a root component RC of a PCIE interface, a ZYNQ chip of the waveform module is used as PCIE interface terminal equipment EP, the main control module comprises SCA Device components, each SCA Device component is a logic abstraction of one waveform module and comprises a driving program of the waveform module, the internal program of the waveform module ZYNQ chip comprises ZYNQ7Processing System, 3 AXI interfaces, 3 AXI BRAM Controller, AXI Memory Mapped PCI Express, AXI Central Direct Memory Access, AXI select MAP, DDR, BRAM, data read-write control logic and interrupt control logic function modules, the ZYNQ7Processing System is interconnected with AXI Internect 1 through an M_AXI_GPO interface to access AXI Memory Mapped PCI Express, AXI Central Direct Memory Access, AXI SelectMAP, AXI BRAM Controller1 and address space of data read-write control logic, AXI Memory Mapped PCI Express is interconnected with AXI Internect 3 through an AXI bus to access DDR, AXI BRAM Controller2 and AXI BRAM Controller3, AXI Central Direct Memory Access is interconnected with AXI Internect 2 through an AXI bus and is connected with AXI Internect 1 and AXI Internect 3 in cascade to access AXI Memory Mapped PCI Express, AXI SelectMAP, AXI BRAM Controller1, AXI BRAM Controller3 and address space of data read-write control logic, access to DDR address space is realized through an S_AXI_HPO interface of ZYNQ7Processing System, AXI BRAM Controller and AXI BRAM Controller are respectively connected with two ports of BRAM, and the master control module is connected with address space of the same BRAM through a PCIE interface, ZYNQ7Processing System and the AXI bus; also included are 4 data types that are of a type, respectively an FPGA7BIT file, a parameter file, waveform parameters, state data and waveform input and output data; the 6 data processing flows are respectively a flow for configuring a BIT file, a configuration parameter file, a configuration waveform parameter, a waveform reading state, waveform data input and waveform data output of the FPGA7 chip;
the process for configuring the BIT file of the FPGA7 chip comprises the following steps of:
(101): ZYNQ7PROCESSING SYSTEM has completed the system initialization in the state of waiting for interrupt triggering, the SCA device driver of the main control module opens the FPGA7BIT file, writes the file data into PCIE BAR0 address space, and writes the data into the DDR of the waveform module through the BAR address mapping of the AXI Memory Mapped PCI Express module;
(102): the master control module driver writes the written data length, the data type of the FPGA BIT file, the control command of the configuration FPGA, the writing mark and the finishing mark of 'Y' into a master control state register of which the address is 0 of PCIE BAR1, wherein the register is actually positioned in a 32-BIT space of address 0 of BRAM and enters an MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM obtains the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, and the interrupt service program reads the file data in DDR through a DMA mode started by the configuration AXI Central Direct Memory Access module and stores the file data in a Linux file system;
(103): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a control state register of ZYNQ7PROCESSING SYSTEM with address 4 of AXI BRAM Controller, wherein the register is actually located in a 32-bit space of address 4 of BRAM, writes a TLP packet of MSI interrupt to a PCIE interface through AXI Memory Mapped PCI Express module, the packet triggers PCIE MSI interrupt and runs a PCIE interrupt service routine, the PCIE interrupt service routine clears interrupt bit, reads a control state register of ZYNQ7PROCESSING SYSTEM with address 4 of PCIE BAR1, is actually located in a 32-bit space of address 4 of BRAM, acquires relevant information set by the ZYNQ7PROCESSING SYSTEM, and enters a trigger state to be interrupted again after the program of ZYNQ7PROCESSING SYSTEM writes the register;
(104): after the host module driver finishes downloading the BIT file, writing a command for configuring the FPGA into a control state register of the host, wherein the control state register comprises a configuration file name and a mark; meanwhile, the interrupt control logic module triggers ZYNQ7PROCESSING SYSTEM to interrupt, an interrupt service routine reads a control state register of the main control to acquire parameters configuring the FPGA7, then a BIT file of the FPGA7 is opened, DMA is started to write file data into the AXI select MAP module, and a mark that the configuration of the FPGA is successful is checked;
(105): the program of ZYNQ7PROCESSING SYSTEM writes configuration results into a control state register of ZYNQ7PROCESSING SYSTEM, wherein the configuration results comprise flag state parameters of whether the configuration of the FPGA is successful or not, a TLP packet of MSI interrupt is written into a PCIE interface through a AXI Memory Mapped PCI Express module to trigger PCIE MSI interrupt to be controlled, a PCIE interrupt service routine of the main control clears interrupt BITs and reads the control state register of ZYNQ7PROCESSING SYSTEM to obtain the configuration state parameters of the FPGA, and the configuration of the FPGA7BIT file is finished;
the waveform data input flow comprises the following steps:
(201): ZYNQ7PROCESSING SYSTEM has completed the system initialization in the state of waiting for interrupt triggering, the SCA device driver of the main control module opens the waveform input file and writes the file data into PCIE BAR0 address space, in fact, the data is directly written into DDR of the waveform module;
(202): the master control module driver writes the written data length, the data type representing the waveform data file, the control command representing the data input, the writing mark and the finishing mark representing 'Y' into the master control state register of address 0 of PCIE BAR1, and enters the MSI interrupt triggering state waiting for PCIE; the operation of the control state register of the driver program writing master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM obtains the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read/write logic control module, after the data direction, the length and the cycle mark are set, the data read/write logic module is started to read the file data in the DDR through the configuration AXI Central Direct Memory Access module, and the data is sent to the SRIO interface of the data read/write control logic module to realize the data input to waveforms;
(203): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a AXI BRAM Controller control status register of ZYNQ7PROCESSING SYSTEM with address 4, writes a TLP packet of MSI interrupt to a PCIE interface through a AXI Memory Mapped PCI Express module, triggers PCIE MSI interrupt to be controlled and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads a register with address 4 of PCIE BAR1 and acquires related information set by the ZYNQ7PROCESSING SYSTEM program;
(204): the read-write control logic module judges a cyclic read-write mark, if the cyclic write mark is cyclic write, the DMA mode is started to read data in the DDR after the data is written, the data is sent to the waveform through the SRIO until the cyclic write is exited, and the process of inputting the waveform data is ended;
the waveform data output flow comprises the following steps:
(301): ZYNQ7PROCESSING SYSTEM is in a state of waiting for interrupt triggering after completing system initialization, the SCA device driver of the main control module starts a waveform output data reading process, writes a to-be-read data length, a waveform data file data type, a data output control command, a reading mark and an 'N' completion mark into a control state register of the main control of address 0 of PCIE BAR1, and enters an MSI interrupt triggering state of waiting for PCIE;
(302): the operation of the control state register of the driver write master control causes the interrupt control logic module to trigger ZYNQ7PROCESSING SYSTEM to interrupt, the interrupt service program of ZYNQ7PROCESSING SYSTEM acquires the file data length, the data type, the control command, the read/write mark and the completion mark by reading the 32-bit register of BRAM address 0 through AXI BRAM Controller1, meanwhile, the interrupt control logic module clears the interrupt bit, the interrupt service program sets the register of the data read/write logic control module, and after the data direction, the length and the cycle mark are set, the data read/write logic control is started to read data from the SRIO interface to DDR;
(303): the program of ZYNQ7PROCESSING SYSTEM writes the read data length, the read flag and the completion flag representing 'Y' into a AXI BRAM Controller control status register of ZYNQ7PROCESSING SYSTEM with address 4, writes a TLP packet of MSI interrupt to a PCIE interface through a AXI Memory Mapped PCI Express module, triggers PCIE MSI interrupt to be controlled and runs a PCIE interrupt service routine, clears interrupt bit by the PCIE interrupt service routine, reads a register with address 4 of PCIE BAR1 and acquires related information set by the ZYNQ7PROCESSING SYSTEM program;
(304): the driver program starts the DMA mode to read PCIE BAR0, namely waveform output data in DDR, judges a cycle read-write mark, if the cycle read is completed, starts the DMA mode to read the data in PCIE BAR0 again after the data is read, and ends the process of outputting waveform data until the cycle read is exited.
2. The rapid system reconstruction method for SCA and SDR of claim 1 wherein the BAR addresses of AXI Memory Mapped PCI Express map the address spaces of DDR, AXI BRAM Controller, and AXI BRAM Controller3, respectively, and three address spaces of DDR, AXI BRAM Controller2, and AXI BRAM Controller3 are accessed directly by the master control module through the BAR addresses of PCIE.
3. The rapid system reconstruction method for SCA and SDR according to claim 1, wherein a PCIE interface of AXI Memory Mapped PCI Express is interconnected with a PCIE interface of a main control module, AXI SelectMAP is interconnected with an AXI SelectMAP interface of FPGA7, AXI BRAM Controller3 is interconnected with an LVDS interface of FPGA7, data read-write control logic is interconnected with an SRIO interface of FPGA7, and ZYNQ7PROCESSING SYSTEM configures registers of the data read-write control logic.
4. The rapid system reconfiguration method for SCA and SDR according to claim 1, comprising two interrupt mechanisms, namely a main control module PCIE MSI interrupt mechanism and a ZYNQ7PROCESSING SYSTEM interrupt control logic, wherein when the ZYNQ sends a specific TLP packet to the main control module through a PCIE interface, the MSI interrupt of the main control module PCIE will be triggered, the corresponding interrupt service routine will clear the interrupt, when the main control module writes data to a specific address of AXI BRAM Controller of the ZYNQ through the PCIE interface, the ZYNQ7PROCESSING SYSTEM interrupt control logic will trigger the ZYNQ7PROCESSING SYSTEM interrupt, and when the ZYNQ7PROCESSING SYSTEM reads data from a specific address of AXI BRAM Controller1 through an AXI bus, the ZYNQ7PROCESSING SYSTEM interrupt control logic will clear the ZYNQ7PROCESSING SYSTEM interrupt.
5. The rapid system reconstruction method for SCA and SDR according to claim 1, comprising two data streams, namely downstream from the master control module to the ZYNQ or FPGA7 and upstream from the ZYNQ or FPGA7 to the master control module.
6. The rapid system reconfiguration method for SCA and SDR according to claim 1, wherein BRAM includes two special 32-bit registers, a master control status register and a control status register of ZYNQ7PROCESSING SYSTEM, respectively, for control in the system, exchange of status information, the registers being defined by bits: a 1-bit completion flag, a 1-bit read/write flag, a 6-bit control command, an 8-bit data type, a 16-bit data length.
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| CN111353235B (en) * | 2020-03-13 | 2021-05-04 | 上海介方信息技术有限公司 | Component port modeling method based on model drive and terminal |
| CN111427823B (en) * | 2020-03-30 | 2023-05-02 | 天津光电通信技术有限公司 | Driving design method supporting PC and FPGA to communicate through PCIE |
| CN111857839B (en) * | 2020-06-05 | 2023-06-27 | 北京航天测控技术有限公司 | Linux-based PXI/PXIe bus device driving system |
| CN112131176B (en) * | 2020-09-29 | 2023-12-12 | 中国船舶集团有限公司第七二四研究所 | FPGA (field programmable Gate array) quick local reconstruction method based on PCIE (peripheral component interface express) |
| CN113297112B (en) * | 2021-04-15 | 2022-05-17 | 上海安路信息科技股份有限公司 | PCIe bus data transmission method and system and electronic equipment |
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Denomination of invention: A Fast System Refactoring Method for SCA and SDR Granted publication date: 20230425 Pledgee: Agricultural Bank of China Limited by Share Ltd. Chengdu high tech Industrial Development Zone Branch Pledgor: Chengdu Xieying Technology Co.,Ltd. Registration number: Y2024510000088 |