CN114116270A - Novel embedded system monitoring method - Google Patents
Novel embedded system monitoring method Download PDFInfo
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- CN114116270A CN114116270A CN202111155966.9A CN202111155966A CN114116270A CN 114116270 A CN114116270 A CN 114116270A CN 202111155966 A CN202111155966 A CN 202111155966A CN 114116270 A CN114116270 A CN 114116270A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3664—Environments for testing or debugging software
Abstract
The invention relates to a novel embedded system monitoring method, belongs to the technical field of embedding, and overcomes the defects that a software watchdog is invalid during initial configuration and a hardware watchdog cannot be shielded after being started in the traditional monitoring method. The novel monitoring method provided by the invention realizes dog feeding by adopting a software and hardware combined mode, can simultaneously monitor the running conditions of software and logic in the system, and resets the system when running is abnormal. The watchdog monitoring method has the advantages that the watchdog monitoring chip can be switched in a watchdog feeding mode through the RS422 serial port command, only the logic operation condition is monitored during pure logic watchdog feeding, and the operation condition of software and logic is monitored simultaneously during software and hardware logic combined watchdog feeding.
Description
Technical Field
The invention belongs to the technical field of embedded systems, and particularly relates to a novel embedded system monitoring method.
Background
The traditional monitoring method of the embedded system comprises 2 methods: software watchdog and hardware watchdog. The software watchdog mostly adopts a timer in the processor as the watchdog, the software is used for feeding the watchdog within a limited time, and the software is reset after timeout. The watchdog in the mechanism needs initialization configuration time, and if software runs away during initialization, the watchdog cannot reset the system, so that the watchdog is low in reliability. The hardware watchdog usually uses a timer circuit, the program clears the timer in limited time to realize dog feeding, and the timer circuit outputs a reset signal after timeout. The watchdog mechanism can run when being electrified, has high reliability, and has the defects that the watchdog mechanism cannot be stopped once being electrified, and is not beneficial to online debugging of programs. The watchdog mechanism realized by combining software and hardware can run after being electrified, has no initial configuration time and high reliability, and can be switched into a hardware logic dog feeding mode through a serial port when software needs to be debugged on line, so that the software is independent of the watchdog mechanism.
Disclosure of Invention
The technical problem to be solved is as follows:
in order to avoid the defects of the prior art, the invention provides a novel embedded system monitoring method, which solves the defects that the traditional software watchdog is invalid in the initial configuration period and cannot be shielded after the hardware watchdog is started.
The technical scheme of the invention is as follows: a novel embedded system monitoring method is characterized by comprising the following specific steps:
the method comprises the following steps: the processor runs the RS422 order that the software receives the upper computer and sends, analyze the result and write into different control words to the run logic according to the order, the control logic is in different dog feeding modes;
step two: in the first step, different dog feeding modes have different monitoring ranges, and 2 kinds of dog feeding signals are generated logically according to different dog feeding modes: when the device is in a pure logic dog feeding mode, a dog feeding signal is a square wave with a period of 500ms, is completely generated by logic and is irrelevant to software, and only the running condition of the logic is monitored at the moment; when the device is in a software and hardware combined dog feeding mode, a dog feeding signal is a square wave with a period of 1s, and is generated by combining software and logic, namely the software and hardware are used for feeding dogs in a combined mode, and the running conditions of the software and the logic are monitored;
the dog feeding signal is output to the watchdog monitoring chip by the logic chip, the watchdog monitoring chip cannot detect the dog feeding signal in 1.6S, namely, the watchdog monitoring chip outputs a reset pulse with the width of 200ms, and simultaneously resets software and logic.
The further technical scheme of the invention is as follows: and the power-on default is that the software and hardware are combined to feed the dog, the watchdog has no initialization configuration time, the watchdog function can still normally work when the software runs away accidentally during the initialization period, and the system is restarted.
The further technical scheme of the invention is as follows: the software runs in the processor, the processor receives a command through a peripheral RS422 interface, and the dog feeding mode of the watchdog chip is switched through analyzing the command; the logic runs in the FPGA or the CPLD and is communicated with the processor through the bus; a dog feeding mode register is arranged in the logic, when software writes 1 into the logic internal register through a bus, the mode is switched to a software and hardware combined dog feeding mode, and when software writes 0 into the logic internal register through the bus, the mode is switched to a pure logic dog feeding mode.
The further technical scheme of the invention is as follows: the different dog feeding modes are different in monitoring objects; when the device is in a pure logic dog feeding mode, the logic running condition is monitored, the software running condition is not monitored, and the software debugging can be facilitated; when the logic operation is abnormal and the correct dog feeding signal cannot be output on time, resetting the system by the watchdog chip, if the logic operation is normal and the software operation is abnormal, enabling the dog feeding signal to be normal and enabling the watchdog chip not to reset the system; when the watchdog chip is in a software and hardware combined watchdog feeding mode, the running conditions of software and logic are monitored simultaneously, once the software or the logic or the software and the logic or the logic are abnormal simultaneously, a watchdog feeding signal cannot be normally output, and the watchdog chip resets the system.
The further technical scheme of the invention is as follows: the dog feeding signal is output by a pin of the FPGA or the CPLD and is connected with a dog feeding signal pin of the monitoring chip; when the hardware and software combined dog feeding mode is adopted, the dog feeding signals are generated by software and logic together, the software needs to execute write operation to a logic fixed address within a period of 500ms, the logic generates the dog feeding signals according to the write operation of the software, and the period is 1 s; when the software does not execute the write operation to the logic due to running and the like, the logic does not generate the dog feeding signal, when the period of the software executing the write operation to the logic is more than 500ms, the logic overtimes to generate the dog feeding signal, and the period is more than or equal to 3 s.
The further technical scheme of the invention is as follows: the default state of the logic internal dog feeding mode register is 1, namely the logic internal dog feeding mode register is in a software and hardware combined dog feeding mode, the watchdog function is electrified and is effective, the configuration starting time of the traditional software watchdog is not available, and the defect that the traditional software watchdog is ineffective before configuration starting is overcome.
The further technical scheme of the invention is as follows: the watchdog monitoring chip adopts two watchdog monitoring chips MAX823, two paths of dog feeding signals are the same, one watchdog monitoring chip is used for resetting logic, and the other watchdog monitoring chip is used for resetting software;
the time length of a watchdog timer in the watchdog is 1.6s, when the dog feeding signal does not turn over within 1.6s, the timer finishes timing, negative pulses with the pulse width of 200ms are output as reset signals, one path of the reset signals is connected with a reset pin of the processor, the other path of the reset signals is connected with a reset pin of the FPGA/CPLD, and software and logic are reset simultaneously.
Advantageous effects
The invention has the beneficial effects that: the novel embedded system monitoring method overcomes the defects that the traditional software watchdog is invalid during the initialization configuration period and the hardware watchdog cannot be shielded after being started, can run after being electrified, does not need initialization, reduces the occupation of software resources and has strong reliability. Can switch the dog feeding mode of watchdog monitoring chip through RS422 serial port command, when being in pure logic dog feeding mode, the software does not participate in feeding the dog, does not monitor the software behavior, can realize software online debugging, and it is nimble convenient to use, when being in software and hardware and jointly feeding the dog mode, monitors software and logic behavior simultaneously, in case unusual reset system.
Drawings
FIG. 1 is a schematic diagram of a novel monitoring method;
FIG. 2 is a schematic diagram of WDI _ COMBINE dog feeding signal generation;
fig. 3 is a circuit diagram of a watchdog monitor.
Detailed Description
The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The software of the invention runs in a DSP processor of TI company, model TMS320C6414T, and the logic runs in an FPGA of Altera company, model EP1S20F 484. The DSP periphery articulates RS422 agreement chip and interface chip, realizes RS422 communication. The frequency of an external crystal oscillator of the FPGA is 40MHz, and the external crystal oscillator is used as a logic working clock.
The DSP processor is connected with the FPGA through an EMIF bus, and the DSP can read and write the internal register of the FPGA through the EMIF bus. The DSP processor receives an RS422 serial port command in an interrupt mode, when a command word is '0 xaa 0x1e 0x 55', the DSP writes 1 into an FPGA internal register WDI _ CTL through an EMIF bus and switches to a software and hardware combined dog feeding mode, and when the RS422 command word received by the DSP is '0 xaa 0x1F 0x 55', the DSP writes 0 into the FPGA internal register WDI _ CTL through the EMIF bus and switches to a pure logic dog feeding mode.
The working clock in the FPGA is 40MHz, the logic counts the 40MHz clock, the value of the signal PULSE _1ms is inverted every 20000 times to generate the signal PULSE _1ms with the period of 1ms, then the signal PULSE _1ms is counted, the value of the signal PULSE _500ms is inverted every 250 times to obtain the signal PULSE _500ms with the period of 500ms, and when the value of the register WDI _ CTL is 0, the signal PULSE _500ms is output as a dog feeding signal. When the value of the register WDI _ CTL is 1, the dog feed signal WDI _ COMBINE, WDI _ COMBINE with a logic output cycle of 1s is generated as follows:
(1) when the logic detects the rising edge of the signal PULSE _500ms, setting 1 to the signal WDI _ FLAG;
(2) when software in the DSP performs write operation on the logical internal address 0x900000A0 within a period of 500ms, clearing a signal WDI _ FLAG;
(3) when the logic detects a rising edge of WDI _ FLAG, WDI _ COMBINE is negated, generating a valid feed dog signal.
The WDI _ COMBINE dog feeding signal is generated schematically and shown in FIG. 2.
The power-on default value of the register WDI _ CTL is 1, namely the register WDI _ CTL is in a software and hardware combined dog feeding mode, the DSP software is required to execute write operation to an address 0x900000A0 within 500ms of a period to ensure normal dog feeding, if the write operation cannot be executed timely after the software flies, a dog feeding signal cannot be generated normally, two watchdog monitoring chips are triggered to output reset signals, one reset signal resets a reset pin of a processor, the other reset signal is connected with a reset pin of the FPGA/CPLD, and the software and logic are reset simultaneously.
The MAX823 is selected for monitoring peripheral watchdog, and the circuit diagram is shown in figure 3. The chip has the functions of power supply detection and manual RESET, as shown in fig. 3, wherein S1 is a manual RESET switch, when the pin of the power supply voltage VCC is lower than 1V or the RESET switch is pressed, the RESET signal RESET is always low, when the VCC is 3.3V and the RESET switch is not pressed, the dog feeding signal WDI _ COMBINE is not turned over within 1.6S, a negative pulse with the pulse width of 200ms is output for resetting software and logic, after the negative pulse with the pulse width of 200ms is ended, the chip restarts to detect whether the dog feeding signal WDI _ COMBINE is turned over within 1.6S, and if not, the negative pulse RESET signal with the pulse width of 200ms is output again.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention.
Claims (7)
1. A novel embedded system monitoring method is characterized by comprising the following specific steps:
the method comprises the following steps: the processor runs the RS422 order that the software receives the upper computer and sends, analyze the result and write into different control words to the run logic according to the order, the control logic is in different dog feeding modes;
step two: in the first step, different dog feeding modes have different monitoring ranges, and 2 kinds of dog feeding signals are generated logically according to different dog feeding modes: when the device is in a pure logic dog feeding mode, a dog feeding signal is a square wave with a period of 500ms, is completely generated by logic and is irrelevant to software, and only the running condition of the logic is monitored at the moment; when the device is in a software and hardware combined dog feeding mode, a dog feeding signal is a square wave with a period of 1s, and is generated by combining software and logic, namely the software and hardware are used for feeding dogs in a combined mode, and the running conditions of the software and the logic are monitored;
the dog feeding signal is output to the watchdog monitoring chip by the logic chip, the watchdog monitoring chip cannot detect the dog feeding signal in 1.6S, namely, the watchdog monitoring chip outputs a reset pulse with the width of 200ms, and simultaneously resets software and logic.
2. The novel embedded system monitoring method according to claim 1, characterized in that: and the power-on default is that the software and hardware are combined to feed the dog, the watchdog has no initialization configuration time, the watchdog function can still normally work when the software runs away accidentally during the initialization period, and the system is restarted.
3. The novel embedded system monitoring method according to claim 1, characterized in that: the software runs in the processor, the processor receives a command through a peripheral RS422 interface, and the dog feeding mode of the watchdog chip is switched through analyzing the command; the logic runs in the FPGA or the CPLD and is communicated with the processor through the bus; a dog feeding mode register is arranged in the logic, when software writes 1 into the logic internal register through a bus, the mode is switched to a software and hardware combined dog feeding mode, and when software writes 0 into the logic internal register through the bus, the mode is switched to a pure logic dog feeding mode.
4. The novel embedded system monitoring method according to claim 1, characterized in that: the different dog feeding modes are different in monitoring objects; when the device is in a pure logic dog feeding mode, the logic running condition is monitored, the software running condition is not monitored, and the software debugging can be facilitated; when the logic operation is abnormal and the correct dog feeding signal cannot be output on time, resetting the system by the watchdog chip, if the logic operation is normal and the software operation is abnormal, enabling the dog feeding signal to be normal and enabling the watchdog chip not to reset the system; when the watchdog chip is in a software and hardware combined watchdog feeding mode, the running conditions of software and logic are monitored simultaneously, once the software or the logic or the software and the logic or the logic are abnormal simultaneously, a watchdog feeding signal cannot be normally output, and the watchdog chip resets the system.
5. The novel embedded system monitoring method according to claim 1, characterized in that: the dog feeding signal is output by a pin of the FPGA or the CPLD and is connected with a dog feeding signal pin of the monitoring chip; when the hardware and software combined dog feeding mode is adopted, the dog feeding signals are generated by software and logic together, the software needs to execute write operation to a logic fixed address within a period of 500ms, the logic generates the dog feeding signals according to the write operation of the software, and the period is 1 s; when the software does not execute the write operation to the logic due to running and the like, the logic does not generate the dog feeding signal, when the period of the software executing the write operation to the logic is more than 500ms, the logic overtimes to generate the dog feeding signal, and the period is more than or equal to 3 s.
6. The novel embedded system monitoring method according to claim 1, characterized in that: the default state of the logic internal dog feeding mode register is 1, namely the logic internal dog feeding mode register is in a software and hardware combined dog feeding mode, the watchdog function is electrified and is effective, the configuration starting time of the traditional software watchdog is not available, and the defect that the traditional software watchdog is ineffective before configuration starting is overcome.
7. The novel embedded system monitoring method according to claim 1, characterized in that: the watchdog monitoring chip adopts two watchdog monitoring chips MAX823, two paths of dog feeding signals are the same, one watchdog monitoring chip is used for resetting logic, and the other watchdog monitoring chip is used for resetting software;
the time length of a watchdog timer in the watchdog is 1.6s, when the dog feeding signal does not turn over within 1.6s, the timer finishes timing, negative pulses with the pulse width of 200ms are output as reset signals, one path of the reset signals is connected with a reset pin of the processor, the other path of the reset signals is connected with a reset pin of the FPGA/CPLD, and software and logic are reset simultaneously.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115016977A (en) * | 2022-08-09 | 2022-09-06 | 南方电网数字电网研究院有限公司 | Hierarchical reset control method and system for heterogeneous multi-core power chip |
| CN115098304A (en) * | 2022-06-20 | 2022-09-23 | 中国科学院空间应用工程与技术中心 | Embedded system, electronic equipment and software running method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115098304A (en) * | 2022-06-20 | 2022-09-23 | 中国科学院空间应用工程与技术中心 | Embedded system, electronic equipment and software running method |
| CN115098304B (en) * | 2022-06-20 | 2022-11-29 | 中国科学院空间应用工程与技术中心 | Embedded system, electronic equipment and software running method |
| CN115016977A (en) * | 2022-08-09 | 2022-09-06 | 南方电网数字电网研究院有限公司 | Hierarchical reset control method and system for heterogeneous multi-core power chip |
| CN115016977B (en) * | 2022-08-09 | 2022-12-27 | 南方电网数字电网研究院有限公司 | Hierarchical reset control method and system for heterogeneous multi-core power chip |
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