CN114116195A - QPSK phase ambiguity resolver based on MPI and multithreading - Google Patents

QPSK phase ambiguity resolver based on MPI and multithreading Download PDF

Info

Publication number
CN114116195A
CN114116195A CN202111180864.2A CN202111180864A CN114116195A CN 114116195 A CN114116195 A CN 114116195A CN 202111180864 A CN202111180864 A CN 202111180864A CN 114116195 A CN114116195 A CN 114116195A
Authority
CN
China
Prior art keywords
data
decoding
mpi
frame synchronization
thread
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111180864.2A
Other languages
Chinese (zh)
Inventor
田梦雪
王静温
郦家骅
李小梅
刘文俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Beijing Research Institute of Telemetry
Aerospace Long March Launch Vehicle Technology Co Ltd
Original Assignee
Beijing Research Institute of Telemetry
Aerospace Long March Launch Vehicle Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Beijing Research Institute of Telemetry, Aerospace Long March Launch Vehicle Technology Co Ltd filed Critical Beijing Research Institute of Telemetry
Priority to CN202111180864.2A priority Critical patent/CN114116195A/en
Publication of CN114116195A publication Critical patent/CN114116195A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/52Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00Indexing scheme relating to G06F9/00
    • G06F2209/50Indexing scheme relating to G06F9/50
    • G06F2209/5018Thread allocation

Abstract

The invention provides a QPSK phase ambiguity resolver based on MPI and multithreading, which comprises n MPI processes arranged in parallel, wherein each MPI process comprises a demodulation code synchronization module and a ambiguity resolution module which are sequentially connected, and the demodulation code synchronization module is used for receiving a QPSK signal, demodulating and synchronizing to generate I path code synchronization data and Q path code synchronization data and outputting the I path code synchronization data and the Q path code synchronization data to the ambiguity resolution module; the deblurring module comprises 4 data decoding combined threads, 4 shared caches and 4 frame synchronization threads which are arranged in parallel, each data decoding combined thread is sequentially connected with 1 shared cache and 1 frame synchronization thread, and each frame synchronization thread is connected with 4 data decoding combined threads. The invention realizes a multithreading parallel two-stage fuzzy solving software framework and a self-defined thread dynamic scheduling model based on multiple Sections of OpenMP. The data integrity is guaranteed while the real-time performance of ambiguity resolution is improved, and the number of the working threads can be dynamically adjusted by the user-defined thread dynamic scheduling model according to the data code rate.

Description

QPSK phase ambiguity resolver based on MPI and multithreading
Technical Field
The invention relates to the technical field of electrical digital data processing, in particular to a QPSK phase ambiguity resolver based on MPI and multithreading.
Background
Satellite communications are limited in both bandwidth and power and therefore constant envelope type modulation is often used as the transmission scheme. QPSK is the most typical of constant inclusion type modulation and is widely used for applications including civilian wireless communications, satellite navigation, and deep space communications. When the receiver demodulates and decodes, operations such as carrier recovery, code synchronization, and phase ambiguity resolution are required to recover the carrier, and a 4-order square loop, costas loop, and other non-linear carrier recovery methods are usually used, so that phase ambiguity is brought, and the phase ambiguity may be quadruple phase ambiguity of 0 °, 90 °, 180 °, or 270 °.
At present, a method for implementing a QPSK demodulation phase ambiguity resolution function in a baseband device applied in a communication system is based on FPGA (Field Programmable Gate Array) programming, and determines which phase ambiguity state the demodulation data belongs to by identifying frame header data through frame synchronization. The traditional engineering practice method needs to judge four kinds of data with fuzzy phases in sequence, supposing the phase of the demodulated data, carries out frame synchronization on the data, and if the frame synchronization fails, then changes the next phase to judge. This process results in loss of demodulated data and waste of information, which is unacceptable in deep space communications.
Disclosure of Invention
The invention aims to solve the problems of poor computation performance and data incompleteness of QPSK demodulation phase ambiguity resolution, and provides a QPSK demodulation phase ambiguity resolver based on MPI and multithreading.
The invention provides a QPSK phase ambiguity resolver based on MPI and multithreading, which comprises n MPI processes arranged in parallel, wherein n is more than or equal to 1; each MPI process comprises a demodulation code synchronization module and a de-fuzzy module which are connected in sequence, wherein the demodulation code synchronization module is used for receiving QPSK signals, demodulating and synchronizing the QPSK signals to generate I path code synchronization data and Q path code synchronization data and outputting the I path code synchronization data and the Q path code synchronization data to the de-fuzzy module;
the ambiguity resolving module comprises 4 data decoding combination threads, 4 shared caches and 4 frame synchronization threads which are arranged in parallel, each data decoding combination thread is sequentially connected with 1 shared cache and 1 frame synchronization thread, and each frame synchronization thread is connected with 4 data decoding combination threads; the data decoding combined thread is used for receiving I way code synchronous data and Q way code synchronous data, carrying out Gray decoding, IQ combination and code type conversion to generate decoding combined data, writing the decoding combined data into a shared cache, the shared cache is used for storing the decoding combined data, the frame synchronization thread is used for reading the decoding combined data from the shared cache and carrying out frame synchronization processing, the frame synchronization thread is used for generating frame synchronization locking information after completing frame synchronization processing and simultaneously sending the frame synchronization locking information to 4 data decoding combined threads, the data decoding combined thread is used for receiving the frame synchronization locking information and judging whether the frame synchronization locking information is the frame synchronization locking information corresponding to the data decoding combined thread, if yes, the data decoding combination process continues the data combination and decoding, if no, stopping the data combination and decoding until receiving the frame synchronization locking message corresponding to the data decoding combination process.
The QPSK phase ambiguity resolver based on MPI and multithreading is used as a preferred mode, and n is the same as the path number of QPSK signals; the activated MPI process is always activated from the process 0 according to the sequence of the process numbers; the MPI process is created on the same machine.
The MPI and multithreading-based QPSK phase ambiguity resolver comprises a data decoding combination thread as a preferred mode, wherein the data decoding combination thread comprises an OpenMP Sections software architecture which is used for performing segmented covering operation on I path code synchronous data and Q path code synchronous data.
The invention relates to an MPI and multithreading QPSK phase ambiguity resolver, which is used as a preferred mode, a data decoding combination thread is used for carrying out segmentation processing on I path code synchronous data and Q path code synchronous data, the lengths of all data Sections are the same, adjacent data Sections keep a Section of coverage area, each Section of an OpenMP Sections software architecture processes Gray decoding, data combination and code type conversion of one data Section, the data decoding combination thread copies output data of each Section to a unified result buffer area, and a result obtained by processing the next Section of data covers the tail part corresponding to the previous Section of data.
The invention discloses an MPI and multithreading QPSK phase ambiguity resolver, which is used as a preferred mode, the length of output data is the same and is integral multiple of bytes, a coverage area comprises M bytes, M is the k power of 2, and k is larger than or equal to 1.
The QPSK phase ambiguity resolver based on MPI and multithreading is used as an optimal mode, and a data decoding combined thread is created by using pthread.
The invention relates to a QPSK phase ambiguity resolver based on MPI and multithreading, which is used as an optimal mode, wherein IQ combination is used for combining I path code synchronous data and Q path code synchronous data after Gray decoding into I + Q data, I-Q data, Q + I data and Q-I data;
and the code pattern transformation is used for carrying out code pattern transformation on the I + Q data, the I-Q data, the Q + I data and the Q-I data to generate decoding combined data and writing the decoding combined data into the shared cache.
The MPI and multithreading QPSK phase ambiguity decoder is preferably implemented by a Gray decoding mode comprising a Gray0 decoding mode, a Gray1 decoding mode, a Gray2 decoding mode, a Gray3 decoding mode, a Gray4 decoding mode, a Gray5 decoding mode, a Gray6 decoding mode and a Gray7 decoding mode which conform to the CCSDS standard.
The QPSK phase-shift ambiguity decoder based on MPI and multithreading is characterized in that as an optimal mode, code pattern transformation comprises an NRZ-L code pattern, an NRZ-M code pattern, an NRZ-S code pattern, a BI phi-L code pattern, a BI phi-S code pattern and a BI phi-M code pattern.
The MPI and multithreading-based QPSK phase ambiguity resolver is used as a preferred mode, and the frame synchronization locking message comprises the sequence number of the frame synchronization thread sending the frame synchronization locking message and a frame synchronization flag bit.
The technical scheme of the invention is as follows:
MPI process parallel software framework implementation
The MPI process parallel software framework of the invention is composed of thread pairs for decoding combination and frame synchronization aiming at different QPSK code synchronization data I, Q sequences.
The MPI process parallel software framework in the step is realized as follows:
(1a) and when the n paths of QPSK demodulation data are deblurred, activating n MPI processes, and starting 2 pthread threads in each MPI process, wherein the total number of the pthread threads is 2 n. The pthread threads 0 to n-1 belong to a first-level processing module, Gray decoding, data combination and code pattern conversion are executed, I, Q paths of data are input, are combined into a form of I + Q, I-Q, Q + I, Q-I after Gray decoding, and are written into the corresponding shared cache 1 to the shared cache 4 after code pattern conversion.
(1b) And the pthread threads n to 2n-1 belong to a second-level processing module, read data from the shared cache 1 to the shared cache 4 respectively, and perform frame synchronization processing. When a frame synchronization pthread thread enters a frame synchronization locking state, a locking message is sent to all pthread threads in the MPI process in a global variable mode.
(1c) And after the data decoding combined thread receives the frame synchronization locking message, judging whether the combined data result corresponding to the thread is frame-synchronized successfully. If the judgment result is yes, the data decoding combination work is continued, if the judgment result is no, the data decoding combination work is stopped, and the data decoding combination work and the corresponding frame synchronization thread wait for the next reset command at the same time and then start the work.
Whether the created MPI process is activated and starts working depends on the way number setting of the input QPSK data. The activated MPI process always starts with process 0.
MPI processes need to be created on the same machine, so that memory buffers can be shared among the MPI processes.
In the data decoding combination module, I, Q paths of data are input, and the Gray code decoding adopts eight decoding modes of Gray 0-Gray 7 which accord with the CCSDS standard; the code pattern conversion adopts six code patterns of NRZ-L, NRZ-M, NRZ-S, BI phi-L, BI phi-S, BI phi-M which conform to IRIGB-106 standard.
In the data decoding combination module, I, Q data are input, and four combination modes of I + Q, I-Q, Q + I and Q-I are formed according to the mode shown in figure 2.
(II) multiple OpenMP Sections to realize data segmentation covering parallel decoding combination
The invention realizes the data segmentation coverage and carries out decoding combination on the data through OpenMP multiple Sections, and the processing process comprises the following steps:
(2a) the input I, Q data stream is segmented, each data segment has the same length, and adjacent data segments maintain a coverage area, as shown in fig. 3.
(2b) And setting an OpenMP Sections software architecture as shown in fig. 4. Each Section handles Gray decoding, data combining and pattern transformation of one data segment.
(2c) And copying the result output by each Section to a unified result buffer area, wherein the result obtained by the subsequent Section of data processing covers the tail part corresponding to the previous Section of data.
The length of the coverage area is set to meet the requirement that the length of the output data is integral multiple of bytes. In order to ensure the accuracy of the output result at the tail part of each block of data, at least 2 bytes of data in the coverage area needs to be covered by the data of the next section.
The invention comprises n MPI defuzzification processes, 4n shared caches, 4n data decoding combined threads and 4n frame synchronization threads; the data decoding combination thread, the shared cache and the frame synchronization thread are in one-to-one correspondence;
each MPI deblurring process contains 4 data decode combination threads and 4 frame synchronization threads. The data decoding combination thread is used for carrying out Gray decoding, IQ combination and code pattern conversion on I, Q paths of code synchronous data and writing the decoding combination data into a corresponding shared cache; the frame synchronization thread reads the data after the decoding combination from the corresponding shared cache, carries out frame synchronization processing, and sends a frame synchronization locking message to 4 data decoding combination threads at the same time once the frame synchronization is finished; the frame synchronization locking message comprises a frame synchronization line program number and a frame synchronization flag bit for sending the message;
and the data decoding combination thread judges whether the decoding combination data result corresponding to the data decoding combination thread completes frame synchronization after receiving the frame synchronization locking message, if so, the data combination and decoding work is continued, and if not, the data combination and decoding work is stopped.
The number of MPI processes is equal to the number of paths of QPSK signals needing to solve the phase ambiguity, and the minimum value is 1. The activated MPI process always starts from process 0 and is activated in order of process number. The MPI process needs to be created on the same machine.
The data entering the data decoding combination thread is in the form of I, Q two paths of data synchronized by QPSK codes.
The data decoding combined thread is created by using pthread, and the creation sequence can be not according to the thread number sequence.
And in each decoding combination thread, OpenMP Sections are used for realizing data segmentation covering parallel decoding combination. The data length of each Section is the same, and the data of adjacent sections have M byte repetition. M is minimum 2 and M should be raised to the nth power of 2.
The invention realizes a multithreading parallel two-stage fuzzy solving software framework and a self-defined thread dynamic scheduling model based on multiple Sections of OpenMP. The data integrity is guaranteed while the real-time performance of ambiguity resolution is improved, and the number of the working threads can be dynamically adjusted by the user-defined thread dynamic scheduling model according to the data code rate.
The invention has the following advantages:
(1) according to the invention, decoding combination and frame synchronization of different input data are executed in parallel according to MPI + multithreading, so that data is not lost in the phase ambiguity resolution process;
(2) the invention divides the data decoding combination module and the frame synchronization module into two stages of processing by utilizing the data cache, which is beneficial to adapting to different code rates and frame lengths;
(3) the invention utilizes MPI form to activate multiple processes, which is beneficial to adapting to the ambiguity resolution of QPSK demodulation signals with different paths; MPI multi-process parallel processing is carried out, and QPSK demodulation signals of different paths cannot interfere with each other;
(4) the invention utilizes multiple Sections of OpenMP to carry out subsection coverage operation on data, and can dynamically adjust the data throughput of one-time parallel deblurring, thereby meeting the requirement of real-time performance of engineering application.
Drawings
FIG. 1 is a block diagram of a MPI and multithreading-based QPSK phase ambiguity resolver software framework;
FIG. 2 is a MPI and multithreading based QPSK demodulator demodulating data combination input sequence diagram;
FIG. 3 is a block diagram of a QPSK demodulator demodulating data based on MPI and multithreading;
fig. 4 is a schematic diagram of a QPSK de-phase ambiguity solution OpenMP multiple Sections based on MPI and multithreading.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Example 1
As shown in FIG. 1, a QPSK phase ambiguity resolver based on MPI and multithreading comprises n MPI processes which are arranged in parallel, wherein n is more than or equal to 1; each MPI process comprises a demodulation code synchronization module and a de-fuzzy module which are connected in sequence, wherein the demodulation code synchronization module is used for receiving QPSK signals, demodulating and synchronizing the QPSK signals to generate I path code synchronization data and Q path code synchronization data and outputting the I path code synchronization data and the Q path code synchronization data to the de-fuzzy module;
the ambiguity resolving module comprises 4 data decoding combination threads, 4 shared caches and 4 frame synchronization threads which are arranged in parallel, each data decoding combination thread is sequentially connected with 1 shared cache and 1 frame synchronization thread, and each frame synchronization thread is connected with 4 data decoding combination threads; the data decoding combined thread is used for receiving I way code synchronous data and Q way code synchronous data, carrying out Gray decoding, IQ combination and code type conversion to generate decoding combined data, writing the decoding combined data into a shared cache, the shared cache is used for storing the decoding combined data, the frame synchronization thread is used for reading the decoding combined data from the shared cache and carrying out frame synchronization processing, the frame synchronization thread is used for generating frame synchronization locking information after completing frame synchronization processing and simultaneously sending the frame synchronization locking information to 4 data decoding combined threads, the data decoding combined thread is used for receiving the frame synchronization locking information and judging whether the frame synchronization locking information is the frame synchronization locking information corresponding to the data decoding combined thread, if yes, the data decoding combination process continues the data combination and decoding, if no, stopping data combination and decoding until receiving the frame synchronization locking message corresponding to the data decoding combination process;
n is the same as the path number of the QPSK signal; the activated MPI process is always activated from the process 0 according to the sequence of the process numbers; MPI processes are created on the same machine;
the data decoding combined thread is created by using pthread;
as shown in FIG. 2, the IQ combination is used to combine Gray decoded I-way code synchronous data and Q-way code synchronous data into I + Q data, I-Q data, Q + I data and Q-I data;
the code pattern transformation is used for carrying out code pattern transformation on the I + Q data, the I-Q data, the Q + I data and the Q-I data to generate decoding combined data and writing the decoding combined data into the shared cache;
as shown in fig. 3 to 4, the data decoding combination procedure includes an OpenMP connections software architecture, where the OpenMP connections software architecture is used to perform segment overlay operation on the I-way code synchronization data and the Q-way code synchronization data;
the data decoding combination thread is used for carrying out segmentation processing on the I path code synchronous data and the Q path code synchronous data, the lengths of all data Sections are the same, adjacent data Sections keep a Section of coverage area, each Section of the OpenMP Sections software architecture processes Gray decoding, data combination and code type conversion of one data Section, the data decoding combination thread copies output data of each Section to a unified result buffer area, and a result obtained by processing the next Section of data covers the tail part corresponding to the previous Section of data;
the length of the output data is the same and is integral multiple of bytes, the coverage area comprises M bytes, M is the k power of 2, and k is more than or equal to 1;
the Gray decoding comprises a Gray0 decoding mode, a Gray1 decoding mode, a Gray2 decoding mode, a Gray3 decoding mode, a Gray4 decoding mode, a Gray5 decoding mode, a Gray6 decoding mode and a Gray7 decoding mode which conform to the CCSDS standard;
the code pattern transformation comprises an NRZ-L code pattern, an NRZ-M code pattern, an NRZ-S code pattern, a BI phi-L code pattern, a BI phi-S code pattern and a BI phi-M code pattern;
the frame synchronization locking message includes a sequence number and a frame synchronization flag bit of a frame synchronization thread that transmits the frame synchronization locking message.
Example 2
A QPSK phase ambiguity resolver based on MPI and multithreading comprises an MPI multiprocess software framework, a pthread-based multithreading realization data decoding combination and a frame synchronization asynchronous framework.
As shown in fig. 1, the specific implementation steps of an MPI + multithreading-based QPSK phase ambiguity resolver of the present invention are as follows:
MPI process parallel software framework implementation
The MPI process parallel software framework of the invention is composed of thread pairs for decoding combination and frame synchronization aiming at different QPSK code synchronization data I, Q sequences.
The MPI process parallel software framework in the step is realized as follows:
(1a) and when the n paths of QPSK demodulation data are deblurred, activating n MPI processes, and starting 2 pthread threads in each MPI process, wherein the total number of the pthread threads is 2 n. The pthread threads 0 to n-1 belong to a first-level processing module, Gray decoding, data combination and code pattern conversion are executed, I, Q paths of data are input, are combined into a form of I + Q, I-Q, Q + I, Q-I after Gray decoding, and are written into the corresponding shared cache 1 to the shared cache 4 after code pattern conversion.
(1b) And the pthread threads n to 2n-1 belong to a second-level processing module, read data from the shared cache 1 to the shared cache 4 respectively, and perform frame synchronization processing. When a frame synchronization pthread thread enters a frame synchronization locking state, a locking message is sent to all pthread threads in the MPI process in a global variable mode.
(1c) And after the data decoding combined thread receives the frame synchronization locking message, judging whether the combined data result corresponding to the thread is frame-synchronized successfully. If the judgment result is yes, the data decoding combination work is continued, if the judgment result is no, the data decoding combination work is stopped, and the data decoding combination work and the corresponding frame synchronization thread wait for the next reset command at the same time and then start the work.
Whether the created MPI process is activated and starts working depends on the way number setting of the input QPSK data. The activated MPI process always starts with process 0.
MPI processes need to be created on the same machine, so that memory buffers can be shared among the MPI processes.
In the data decoding combination module, I, Q paths of data are input, and the Gray code decoding adopts eight decoding modes of Gray 0-Gray 7 which accord with the CCSDS standard; the code pattern conversion adopts six code patterns of NRZ-L, NRZ-M, NRZ-S, BI phi-L, BI phi-S, BI phi-M which conform to IRIGB-106 standard.
In the data decoding combination module, I, Q data are input, and four combination modes of I + Q, I-Q, Q + I and Q-I are formed according to the mode shown in figure 2.
(II) multiple OpenMP Sections to realize data segmentation covering parallel decoding combination
The processing process of the invention for realizing data segmentation coverage and parallel decoding and combining data through OpenMP multiple Sections is as follows:
(2a) the input I, Q data stream is segmented, each data segment has the same length, and adjacent data segments maintain a coverage area, as shown in fig. 3.
(2b) And setting an OpenMP Sections software architecture as shown in fig. 4. Each Section handles Gray decoding, data combining and pattern transformation of one data segment.
(2c) And copying the result output by each Section to a unified result buffer area, wherein the result obtained by the subsequent Section of data processing covers the tail part corresponding to the previous Section of data.
The length of the coverage area is set to meet the requirement that the length of the output data is integral multiple of bytes. In order to ensure the accuracy of the output result at the tail part of each block of data, at least 2 bytes of data in the coverage area needs to be covered by the data of the next section.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (10)

1. A QPSK phase ambiguity resolver based on MPI and multithreading is characterized in that: comprises n MPI processes which are arranged in parallel, wherein n is more than or equal to 1; each MPI process comprises a demodulation code synchronization module and a de-blurring module which are sequentially connected, wherein the demodulation code synchronization module is used for receiving QPSK signals, demodulating and synchronizing the QPSK signals to generate I path code synchronization data and Q path code synchronization data and outputting the I path code synchronization data and the Q path code synchronization data to the de-blurring module;
the deblurring module comprises 4 data decoding combined threads, 4 shared caches and 4 frame synchronization threads which are arranged in parallel, each data decoding combined thread is sequentially connected with 1 shared cache and 1 frame synchronization thread, and each frame synchronization thread is connected with 4 data decoding combined threads; the data decoding combination thread is used for receiving the I-way code synchronous data and the Q-way code synchronous data, performing Gray decoding, IQ combination and code type conversion to generate decoding combination data, writing the decoding combination data into the shared cache, the shared cache is used for storing the decoding combination data, the frame synchronization thread is used for reading the decoding combination data from the shared cache and performing frame synchronization processing, the frame synchronization thread is used for generating frame synchronization locking information after completing the frame synchronization processing and simultaneously sending the frame synchronization locking information to 4 data decoding combination threads, the data decoding combination thread is used for receiving the frame synchronization locking information and judging whether the frame synchronization locking information corresponds to the data decoding combination thread, if so, the data decoding combination thread continues to perform data combination and decoding work, if not, stopping the data combination and decoding until receiving the frame synchronization locking message corresponding to the data decoding combination process.
2. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: n is the same as the path number of the QPSK signal; the activated MPI process is always activated from process 0 according to the sequence of process numbers; the MPI process is created on the same machine.
3. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the data decoding combination thread comprises an OpenMP Sections software architecture, and the OpenMP Sections software architecture is used for performing section covering operation on the I path code synchronous data and the Q path code synchronous data.
4. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 3, wherein: the data decoding combination thread is used for carrying out segmentation processing on the I-path code synchronous data and the Q-path code synchronous data, the lengths of all data Sections are the same, adjacent data Sections keep a Section of coverage area, each Section of the OpenMP Sections software framework processes Gray decoding, data combination and code type conversion of one data Section, the data decoding combination thread copies output data of each Section to a unified result buffer area, and a result obtained by processing the next Section of data covers the tail part corresponding to the previous Section of data.
5. The MPI and multithreading-based QPSK de-phase ambiguity resolver of claim 4, wherein: the length of the output data is the same and is integral multiple of bytes, the coverage area comprises M bytes, M is the k power of 2, and k is larger than or equal to 1.
6. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the data transcoding combining thread is created using pthread.
7. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the IQ combination is used for combining I path code synchronous data and Q path code synchronous data after Gray decoding into I + Q data, I-Q data, Q + I data and Q-I data;
and the code pattern transformation is used for carrying out code pattern transformation on the I + Q data, the I-Q data, the Q + I data and the Q-I data to generate the decoding combined data and writing the decoding combined data into the shared cache.
8. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the Gray decoding comprises a Gray0 decoding mode, a Gray1 decoding mode, a Gray2 decoding mode, a Gray3 decoding mode, a Gray4 decoding mode, a Gray5 decoding mode, a Gray6 decoding mode and a Gray7 decoding mode which conform to the CCSDS standard.
9. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the code pattern transformation comprises an NRZ-L code pattern, an NRZ-M code pattern, an NRZ-S code pattern, a BI phi-L code pattern, a BI phi-S code pattern and a BI phi-M code pattern.
10. The MPI and multithreading-based QPSK phase ambiguity resolver of claim 1, wherein: the frame synchronization locking message comprises a sequence number and a frame synchronization flag bit of the frame synchronization thread which sends the frame synchronization locking message.
CN202111180864.2A 2021-10-11 2021-10-11 QPSK phase ambiguity resolver based on MPI and multithreading Pending CN114116195A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111180864.2A CN114116195A (en) 2021-10-11 2021-10-11 QPSK phase ambiguity resolver based on MPI and multithreading

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111180864.2A CN114116195A (en) 2021-10-11 2021-10-11 QPSK phase ambiguity resolver based on MPI and multithreading

Publications (1)

Publication Number Publication Date
CN114116195A true CN114116195A (en) 2022-03-01

Family

ID=80441908

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111180864.2A Pending CN114116195A (en) 2021-10-11 2021-10-11 QPSK phase ambiguity resolver based on MPI and multithreading

Country Status (1)

Country Link
CN (1) CN114116195A (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1138795A (en) * 1995-06-07 1996-12-25 迪维安公司 Signal processing apparatus and method
US20130024871A1 (en) * 2011-07-19 2013-01-24 International Business Machines Corporation Thread Management in Parallel Processes
CN103078727A (en) * 2013-01-06 2013-05-01 中国电子科技集团公司第十研究所 Method for improving frame synchronization performance of data transmission receiver
WO2016192321A1 (en) * 2015-06-03 2016-12-08 深圳市中兴微电子技术有限公司 Phase ambiguity correction method and device, and computer storage medium
CN110808772A (en) * 2019-11-26 2020-02-18 上海航天测控通信研究所 Baseband signal processing method and device for receiver of near-moon space communication
CN110995280A (en) * 2019-12-19 2020-04-10 北京遥测技术研究所 Parallel Viterbi decoder

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1138795A (en) * 1995-06-07 1996-12-25 迪维安公司 Signal processing apparatus and method
US20130024871A1 (en) * 2011-07-19 2013-01-24 International Business Machines Corporation Thread Management in Parallel Processes
CN103078727A (en) * 2013-01-06 2013-05-01 中国电子科技集团公司第十研究所 Method for improving frame synchronization performance of data transmission receiver
WO2016192321A1 (en) * 2015-06-03 2016-12-08 深圳市中兴微电子技术有限公司 Phase ambiguity correction method and device, and computer storage medium
CN110808772A (en) * 2019-11-26 2020-02-18 上海航天测控通信研究所 Baseband signal processing method and device for receiver of near-moon space communication
CN110995280A (en) * 2019-12-19 2020-04-10 北京遥测技术研究所 Parallel Viterbi decoder

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
曹颖鹏;杨光文;靳一;: "QPSK信号旋转方向对调制解调的影响", 空间电子技术, no. 03, 25 June 2020 (2020-06-25) *
闫迪;王元钦;吴涛;孙克;: "基于数据分解的高速QPSK并行解调方法", 系统工程与电子技术, no. 07, 25 January 2018 (2018-01-25) *

Similar Documents

Publication Publication Date Title
JPH09214578A (en) Carrier reproduction circuit
US20150078486A1 (en) Code modulation and demodulation method and apparatus for high order modulation
JPH06326742A (en) Method and equipment for restoring level/phase multiplex-modulation data
JPH10190484A (en) Synchronizing method of viterbi decoder and its device
JPH0230216B2 (en)
JP5020578B2 (en) Hierarchical modulation signal independent stream extraction and soft decision apparatus and method
US7065696B1 (en) Method and system for providing high-speed forward error correction for multi-stream data
CN114116195A (en) QPSK phase ambiguity resolver based on MPI and multithreading
CN112532306B (en) Low-delay VDE satellite-borne downlink digital signal processing system based on FPGA
USRE43204E1 (en) Data transmission process with auto-synchronized correcting code, auto-synchronized coder and decoder, corresponding to transmitter and receiver
CN109245853A (en) It is a kind of that synchronized communication method is exempted from based on polarization code
JP4554451B2 (en) COMMUNICATION DEVICE, COMMUNICATION SYSTEM, MODULATION METHOD, AND PROGRAM
EP1755303B1 (en) Method and apparatus for wide dynamic range reduction
CN110995280B (en) Parallel Viterbi decoder
CN100558096C (en) A kind of quadrature amplitude modulation demodulation method and device that is applied to communication system
JPH11220504A (en) Digital demodulator
JPH08265370A (en) Error detection device of packet exchanger
JP4130165B2 (en) Demodulator circuit
JP3363768B2 (en) Digital demodulator
JPH03274933A (en) Interleave synchronizing circuit
JP2006279686A (en) Frame synchronization detection method
JPS62137933A (en) Radio system with error correction
CN1152976A (en) Direct conversion receiver
JP3381286B2 (en) Viterbi decoding method and device
JPS613529A (en) Error correction system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination