CN114115600A - Design method for reducing poor touch circuit of inner layer of panel - Google Patents
Design method for reducing poor touch circuit of inner layer of panel Download PDFInfo
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- CN114115600A CN114115600A CN202111405171.9A CN202111405171A CN114115600A CN 114115600 A CN114115600 A CN 114115600A CN 202111405171 A CN202111405171 A CN 202111405171A CN 114115600 A CN114115600 A CN 114115600A
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- 238000013461 design Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims abstract description 15
- 230000007547 defect Effects 0.000 claims abstract description 7
- 230000002159 abnormal effect Effects 0.000 claims description 8
- 230000008901 benefit Effects 0.000 abstract description 5
- 238000003475 lamination Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 16
- 230000006872 improvement Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 2
- 239000003086 colorant Substances 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007405 data analysis Methods 0.000 description 1
- 238000013480 data collection Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0416—Control or interface arrangements specially adapted for digitisers
- G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
Abstract
The invention discloses a design method for reducing the defect of a panel inner layer touch circuit, which comprises the following steps: s1: digging out a part of BC at the joint of the CM and the BC without the VA opening; s2: after the unnecessary BC is dug out, the contact area between the CM and the BC is reduced, and a VA hole is reserved; s3: the VA hole is normally overlapped and used by the CM and the BC so as to realize the touch function of the panel. According to the design method for reducing the poor touch circuit of the inner layer of the panel, the pixel BC wiring position is changed, the unnecessary lamination area of CM and BC is reduced, foreign matters are further reduced, and the probability of short circuit of CM and BC caused by falling is reduced. The yield of the TIC machine type products is improved, and the economic benefit is improved.
Description
Technical Field
The invention belongs to the technical field of touch screens, and particularly relates to a design method for reducing poor touch circuits on an inner layer of a panel.
Background
At present, touch in cell structure panels are used for touch screens, TFT panels are of a laminated structure, wherein foreign matters under touch line layers (touch screen signal conduction lines, hereinafter referred to as CM) cause poor deposition of a protective film, and an insulating protective layer (hereinafter referred to as VA) is punctured, so that the CM and an ITO layer (hereinafter referred to as BC) are short-circuited, as shown in the first drawing. The product generates abnormal quality of different colors of the block touch screen (for short, TIC NG in fig. 3). Data analysis and collection show that this failure mode results in a TIC NG yield loss of over 80%.
Aiming at the failure mode, the BC wiring position is changed when the panel is designed, so that the BC area above the CM is reduced, when foreign matters exist under the CM, ITO does not exist on the upper film layer, short circuit cannot be formed, the quality of the panel cannot be abnormal, and the product yield is improved. Therefore, a design method for reducing the defects of the touch circuit on the inner layer of the panel is proposed to solve the above-mentioned problems in the background art.
Disclosure of Invention
The present invention is directed to a design method for reducing the defects of the inner touch circuit of the panel, so as to solve the problems mentioned in the background art.
The invention mainly changes the position of pixel BC wiring during product design, reduces the unnecessary lamination area of CM and BC, further reduces the falling foreign matters, and reduces the probability of short circuit of CM and BC.
In order to achieve the purpose, the invention provides the following technical scheme: a design method for reducing the defects of a touch circuit on an inner layer of a panel comprises the following steps:
s1: digging out a part of BC (namely digging out a part d in figure 4) at the joint of CM and BC without VA opening;
s2: after the unnecessary BC is dug out, the contact area between the CM and the BC is reduced, and a VA hole is reserved;
s3: the VA hole is normally overlapped and used by the CM and the BC so as to realize the touch function of the panel.
The BC cut out portion in step S1 is a region that can be avoided without any actual function in the CM-BC overlapping area. BC is a common electrode, and the area touch signals which can be avoided without actual functions are normally open due to short circuit between CM and BC, so that abnormal touch is caused.
Compared with the prior art, the invention has the beneficial effects that: according to the design method for reducing the poor touch circuit of the inner layer of the panel, the pixel BC wiring position is changed, the unnecessary lamination area of CM and BC is reduced, foreign matters are further reduced, and the probability of short circuit of CM and BC caused by falling is reduced. The yield of the TIC machine type products is improved, and the economic benefit is improved.
Drawings
FIG. 1 is a schematic diagram of CM and BC short circuit caused by foreign matter under CM puncturing the insulating layer;
FIG. 2 is a schematic diagram of the short circuit region and the normal region of FIG. 1;
FIG. 3 is a schematic diagram of imaging of a blocky touch panel by lighting up an abnormal color;
FIG. 4 is a schematic view of reducing the contact area between CM and BC across layers;
fig. 5 is a schematic diagram illustrating the invention after cutting off unnecessary BC.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The CM touch routing by blocks are grouped, and when a finger touches the panel, an induction capacitor is generated and then is sensed to an IC (integrated circuit) for analyzing the touch position. BC is a common electrode, and the short circuit between CM and BC causes the touch signal in the area to be normally open, thereby causing abnormal touch.
In the overlapping area about present volume product CM and BC, there is the region that no actual function can avoid, with this place CM or BC figure bypass or reduce, can effectively promote this region because of the foreign matter leads to the short circuit unusual.
Considering the influence of other layer positions, the CM is not easy to change, so that the BC layer is appropriately modified, as shown in fig. 5, to reduce the overlapping area ratio, i.e., the yield improvement ratio can be obtained. To reduce the CM and BC overlap area.
In fig. 1, a foreign object under CM pierces an insulating layer to cause short circuit of CM and BC, in fig. 2, a foreign object causes short circuit of CM and BC, and b is a normal region; in fig. 3, c is the quality abnormal lighting imaging of the different colors of the block touch screen, referred to as TIC NG for short; in fig. 4, d is the reduction of the contact area between CM and BC across layers; FIG. 5 is a schematic diagram showing the unnecessary BC after being dug off, and the contact area between the CM and the BC (reserved with VA holes) is reduced.
The yield loss of the existing product is 0.6% due to TIC NG, yield improvement is a permanent and unchangeable work item in the panel industry, and the yield improvement percentage is the benefit improvement percentage and is improved for the purpose of improving the yield and the benefit.
The invention mainly changes the position of pixel BC wiring during product design, reduces the unnecessary lamination area of CM and BC, further reduces the falling foreign matters, and reduces the probability of short circuit of CM and BC.
The invention provides a design method for reducing the poor touch circuit of the inner layer of a panel as shown in FIG. 5, which comprises the following steps:
s1: digging out a part of BC (namely digging out a part d in figure 4) at the joint of CM and BC without VA opening;
s2: after the unnecessary BC is dug out, the contact area between the CM and the BC is reduced, and a VA hole is reserved;
s3: the VA hole is normally overlapped and used by the CM and the BC so as to realize the touch function of the panel.
The BC cut out portion in step S1 is a region that can be avoided without any actual function in the CM-BC overlapping area.
BC is a common electrode, and the area touch signals which can be avoided without actual functions are normally open due to short circuit between CM and BC, so that abnormal touch is caused.
Taking an example: dropping of particles according to the current 6.5 inch model resulted in TIC NG ratio of 1.4/glass kill defects. The estimated new 6.5 inch model TIC loss should be 1.75%, and the actual P-test data is 0.5-0.6%, and the improvement rate of 60% is the improvement contribution of the design.
The method is applied to the Touch in cell structure in the field of panels, and the TIC yield is improved. Meanwhile, the concept can be applied to any panel and semiconductor product which are damaged due to short circuit caused by foreign matter rupture in the cross layer.
In summary, compared with the prior art, the invention can improve the yield of TIC model products. Based on the 6.5 inch model with the largest MDT production, the current P-test TIC NG type has the good loss of 0.6 percent, and the change can improve the total yield by 0.2 percent. The energy input is estimated every month by 20K TIC, and the economic benefit is improved by nearly millions per month.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.
Claims (3)
1. A design method for reducing the bad touch circuit of the inner layer of a panel is characterized in that: the method comprises the following steps:
s1: digging out a part of BC at the joint of the CM and the BC without the VA opening;
s2: after the unnecessary BC is dug out, the contact area between the CM and the BC is reduced, and a VA hole is reserved;
s3: the VA hole is normally overlapped and used by the CM and the BC so as to realize the touch function of the panel.
2. The design method for reducing defects of touch lines on an inner layer of a panel as claimed in claim 1, wherein: the BC cut out portion in step S1 is a region that can be avoided without any actual function in the CM-BC overlapping area.
3. The design method of reducing defects of touch circuitry on an inner layer of a panel as claimed in claim 2, wherein: BC is a common electrode, and the area touch signals which can be avoided without actual functions are normally open due to short circuit between CM and BC, so that abnormal touch is caused.
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CN202111405171.9A CN114115600A (en) | 2021-11-24 | 2021-11-24 | Design method for reducing poor touch circuit of inner layer of panel |
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008083718A (en) * | 2004-01-28 | 2008-04-10 | Sharp Corp | Active matrix substrate and display device |
CN101266735A (en) * | 2007-03-14 | 2008-09-17 | 索尼株式会社 | Display panel, electronic device and method for manufacturing display panel |
CN113064511A (en) * | 2021-03-09 | 2021-07-02 | 武汉华星光电半导体显示技术有限公司 | Touch control display panel |
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2021
- 2021-11-24 CN CN202111405171.9A patent/CN114115600A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008083718A (en) * | 2004-01-28 | 2008-04-10 | Sharp Corp | Active matrix substrate and display device |
CN101266735A (en) * | 2007-03-14 | 2008-09-17 | 索尼株式会社 | Display panel, electronic device and method for manufacturing display panel |
CN113064511A (en) * | 2021-03-09 | 2021-07-02 | 武汉华星光电半导体显示技术有限公司 | Touch control display panel |
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Application publication date: 20220301 |