CN114095047A - Signal processing circuit, chip and receiver - Google Patents
Signal processing circuit, chip and receiver Download PDFInfo
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- CN114095047A CN114095047A CN202111402799.3A CN202111402799A CN114095047A CN 114095047 A CN114095047 A CN 114095047A CN 202111402799 A CN202111402799 A CN 202111402799A CN 114095047 A CN114095047 A CN 114095047A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The embodiment of the application provides a signal processing circuit, which comprises an amplitude processing circuit, a signal processing circuit and a signal processing circuit, wherein the amplitude processing circuit is used for converting an amplitude component in a signal into an amplitude quantization signal; a phase processing circuit for converting a phase component in the signal into a phase quantized signal; and the demodulator is electrically connected with the amplitude processing circuit and the phase processing circuit and used for synthesizing and mapping the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, wherein the demodulated signal comprises original data of the signal. The embodiment of the application also provides a chip and a receiver. Therefore, the signal processing circuit and the electronic device provided by the embodiment of the application can reduce the complexity and power consumption of a receiver circuit, and meanwhile, when the amplitude processing circuit is singly started, a low-power consumption awakenable mechanism can be realized under the condition that a signal modulation mode is not changed, so that the average power consumption of the receiver is further reduced.
Description
Technical Field
The present application relates to the field of wireless communication technologies, and in particular, to a signal processing circuit, a chip, and a receiver.
Background
With the rapid development of wireless communication, a wireless sensor network is also widely applied, the wireless sensor network comprises a plurality of wireless sensor nodes, and the wireless sensor nodes are usually powered by a battery, so that the wireless sensor nodes have higher requirements on low power consumption. The wireless sensing nodes comprise wireless receivers, and the wireless receivers are used for receiving and demodulating wireless signals transmitted among the nodes, however, the existing wireless receivers have complex circuit structures and high power consumption, and are not beneficial to being applied to wireless sensing networks in a large scale and a large range.
Disclosure of Invention
In view of the foregoing problems, embodiments of the present application provide a signal processing circuit and a receiver, where an amplitude processing circuit and a phase processing circuit are provided, so as to decouple and separate a wireless signal based on a polar coordinate form from both amplitude and phase, and perform signal processing separately, thereby implementing a low-power consumption wake-up mechanism, and thus reducing the complexity and power consumption of the receiver circuit.
A first aspect of embodiments of the present application provides a signal processing circuit, including:
the amplitude processing circuit is used for converting amplitude components in the wireless signal into amplitude quantized signals, and the amplitude components are used for indicating amplitude information in the wireless signal;
phase processing circuitry to convert a phase component in the wireless signal to a phase quantized signal, the phase component being indicative of phase information in the wireless signal;
and the demodulator is electrically connected with the amplitude processing circuit and the phase processing circuit and used for synthesizing and mapping the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, wherein the demodulated signal comprises original data of the wireless signal.
In some possible implementation manners, the signal processing circuit further includes a first amplifier, the first amplifier is electrically connected to the amplitude processing circuit and the phase processing circuit, and the first amplifier is configured to amplify the signal and output the amplified signal to the amplitude processing circuit and the phase processing circuit.
In some possible implementations, the amplitude processing circuit includes:
a detector for detecting amplitude information of the signal and outputting an envelope signal according to the amplitude information, the envelope signal being indicative of a signal peak of the signal;
the first filter is electrically connected to the detector, and is used for receiving the envelope signal and filtering the envelope signal to obtain a first filtered signal;
the second amplifier is electrically connected with the first filter, is used for receiving the first filtering signal and is used for amplifying the first filtering signal to obtain a first amplified signal;
and the comparator is electrically connected with the second amplifier, is used for receiving the first amplified signal and is used for converting the first amplified signal into an amplitude quantization signal.
In some possible implementations, the phase processing circuit includes:
the phase discriminator is used for detecting the phase difference between the phase of the signal and the reference signal to obtain a phase difference signal;
the third amplifier is electrically connected with the phase discriminator, and is used for receiving the phase difference signal and amplifying the phase difference signal to obtain a second amplified signal;
the second filter is electrically connected to the third amplifier, and is used for receiving the second amplified signal and filtering the second amplified signal to obtain a second filtered signal;
the first oscillator is electrically connected with the second filter and the phase discriminator, is used for receiving the second filtering signal and is used for outputting a reference signal to the phase discriminator according to the second filtering signal;
and the analog-to-digital converter is electrically connected with the second filter and is used for converting the second filtered signal into a phase quantization signal.
In some possible implementations, the phase processing circuit further includes a frequency tracking circuit and a frequency calibration circuit;
the frequency tracking circuit is electrically connected with the second filter and the first oscillator and is used for compensating carrier frequency drift of the signal;
the frequency calibration circuit is electrically connected to the first oscillator and the phase detector, and is configured to calibrate the frequency of the reference signal.
In some possible implementations, the signal processing circuit further includes a gain control circuit electrically connected to the second amplifier, the first filter, and the third amplifier, and configured to adjust amplification gains of the second amplifier and the third amplifier according to the first filtered signal.
In some possible implementations, the gain control circuit includes a second oscillator, a counter, a control circuit, a resistor array;
the second oscillator is electrically connected to the first filter and is used for outputting an oscillation signal according to the first filtering signal, wherein the oscillation signal is used for indicating amplitude information of the first filtering signal;
the counter is electrically connected to the second oscillator and used for receiving the oscillation signal, calculating the frequency of the oscillation signal and outputting a frequency signal, wherein the frequency signal is used for indicating the frequency information of the oscillation signal and further indicating the amplitude information of the first filtering signal;
the control circuit is electrically connected with the counter, the resistor array, the second amplifier and the third amplifier and used for receiving the frequency signal, calculating the receiving power of the signal according to the frequency signal and adjusting the resistance value of the resistor array, the amplification gain of the second amplifier and the amplification gain of the third amplifier according to the receiving power;
the resistor array is electrically connected to the comparator, and the threshold voltage of the comparator is adjusted by the resistor array according to the resistance value of the resistor array.
In some possible implementations, the demodulator outputs a wake-up signal to the phase processing circuit based on the amplitude quantization signal matching a preset sequence, where the wake-up signal is used to start the phase processing circuit.
A second aspect of the embodiments of the present application provides a chip, including:
a signal processing circuit as claimed in any one of the above claims; and the matching circuit is electrically connected with an antenna and the signal processing circuit and is used for matching the input impedance of the antenna and the signal processing circuit.
A third aspect of the embodiments of the present application provides a receiver, including the chip as described above.
Therefore, according to the signal processing circuit and the receiver provided by the embodiment of the application, by arranging the amplitude processing circuit and the phase processing circuit, the wireless data based on the polar coordinate form is decoupled and separated from the amplitude and the phase, and is respectively subjected to signal processing and demodulation, so that the complexity and the power consumption of the receiver circuit are reduced, and meanwhile, when the amplitude processing circuit is singly started, a low-power-consumption awakenable mechanism can be realized under the condition that the signal modulation mode is not changed, and the average power consumption of the receiver is further reduced.
Drawings
Fig. 1 is a diagram of an application scenario of a receiver according to an embodiment of the present application.
Fig. 2 is a schematic diagram of a chip according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of the amplitude processing circuit and the phase processing circuit in fig. 2.
Fig. 4 is a circuit diagram of the gain control circuit of fig. 3.
Fig. 5 is a constellation diagram of a wireless signal received by the signal processing circuit in fig. 2.
Fig. 6 is a schematic signal diagram illustrating the processing of the wireless signal by the signal processing circuit in fig. 2.
Description of the main elements
Matching circuit 20
Frequency divider 105
Analog-to-digital converter 204
Second oscillator 301
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
In the embodiments of the present application, the terms "first", "second", and the like are used only for distinguishing different objects, and are not intended to indicate or imply relative importance, nor order to indicate or imply order. For example, a first application, a second application, etc. is used to distinguish one application from another application and not to describe a particular order of applications, and features defined as "first" and "second" may explicitly or implicitly include one or more of the features.
Referring to fig. 1, fig. 1 is a diagram illustrating an application scenario of a receiver 300 according to an embodiment of the present application, and as shown in fig. 1, the receiver 300 may be configured to receive a wireless signal sent by a wireless device 400, demodulate the wireless signal, and restore data of the wireless signal. The radio signal may be represented in polar form, for example, the radio signal S ═ a × ejθWherein A is an amplitude component of the wireless signal S and is expressed by a mode from a pole to a coordinate point of the wireless signal S in a polar coordinate system, and theta is a phase component of the wireless signal S and is expressed by an included angle between a connecting line from the pole to the wireless signal S and a horizontal axis in the polar coordinate system; the amplitude component a is used to indicate amplitude information of the wireless signal S, and the phase component θ is used to indicate phase information of the wireless signal S.
In some embodiments, the wireless device 400 may be an electronic device that may transmit radio and wireless signals, such as a base station, a radio station, a terminal device, and the like.
Referring to fig. 2, fig. 2 is a schematic diagram of a chip 200 according to an embodiment of the present disclosure. The chip 200 may be disposed within the receiver 300.
As shown in fig. 1, the chip 200 may include a matching circuit 20 and a signal processing circuit 100, the matching circuit 20 is electrically connected to an antenna 10, the antenna 10 is configured to receive a wireless signal and transmit the wireless signal to the matching circuit 20, and the matching circuit 20 is configured to match impedances of the antenna 10 and an input end of the signal processing circuit 100, so as to reduce interference between a reflected wave and radiation of the wireless signal and improve transmission efficiency of the wireless signal.
It should be noted that the antenna 10 may be integrated on the chip 200, or may be independently disposed on the receiver 300, and the positional relationship of the antenna 10 is not limited in this application.
In some embodiments, the Antenna 10 may be a monopole Antenna, a Planar Inverted F-shaped Antenna (PIFA), a multi-branch Antenna, or the like, and the matching circuit 20 may be an L-type matching circuit, a T-type matching circuit, a pi-type matching circuit, or other capacitors, inductors, and combinations of capacitors and inductors.
In this embodiment, the signal processing circuit 100 may include a first amplifier 30, an amplitude processing circuit 40, a phase processing circuit 50, and a demodulator 70, wherein the first amplifier 30 is electrically connected to the matching circuit 20, and is configured to receive the wireless signal output through the matching circuit 20 and amplify the wireless signal.
In some embodiments, the first amplifier 30 may be a low noise amplifier, and the first amplifier 30 has a low noise coefficient, so that the wireless signal may be amplified with low noise, and the signal-to-noise ratio of the wireless signal may be improved, thereby facilitating subsequent signal processing of the wireless signal.
The amplitude processing circuit 40 is electrically connected to the first amplifier 30, and the amplitude processing circuit 40 is configured to receive an amplitude component of the wireless signal, demodulate and quantize the amplitude component of the wireless signal, and convert the amplitude component into an amplitude quantized signal; the phase processing circuit 50 is electrically connected to the first amplifier 30, and the phase processing circuit 50 is configured to receive a phase component of the wireless signal, demodulate and quantize the phase component of the wireless signal, and convert the phase component into a phase quantized signal; the demodulator 70 is electrically connected to the amplitude processing circuit 40 and the phase processing circuit 50, and the demodulator 70 is configured to receive the amplitude quantized signal and the phase quantized signal, and map and combine the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal. The mapping synthesis is to match the amplitude quantized signal and the phase quantized signal with a preset matching table respectively to obtain amplitude information and phase information corresponding to the wireless signal, and then synthesize the amplitude information and the phase information to obtain the demodulated signal, thereby obtaining data of the wireless signal.
In some embodiments, the signal processing circuit 100 includes a low power consumption mode and a normal power consumption mode, when the signal processing circuit 100 operates in the low power consumption mode, the phase processing circuit 50 is turned off, the demodulator 70 only receives the amplitude quantized signal, and determines whether to turn on the phase processing circuit according to the received amplitude quantized signal, specifically, the demodulator 70 may compare the amplitude quantized signal with a preset sequence, if the amplitude quantized signal is consistent with the preset sequence, the demodulator 70 may output a wake-up signal to the phase processing circuit 50, the wake-up signal is used to start the phase processing circuit 50, the signal processing circuit 100 enters the normal power consumption mode, and the amplitude processing circuit 40, the phase processing circuit 50, and the demodulator 70 all start operating; if the amplitude quantized signal is not consistent with the preset sequence, the demodulator 70 continues to receive the amplitude quantized signal.
It should be noted that the preset sequence may be configured in advance, and the preset sequence may be a specific binary sequence.
Referring to fig. 3, fig. 3 is a schematic structural diagram of the amplitude processing circuit 40 and the phase processing circuit 50 in fig. 2. The amplitude processing circuit 40 may include a detector 101, a first filter 102, a second amplifier 103, a comparator 104, and a frequency divider 105, the detector 101 is configured to receive the wireless signal amplified by the first amplifier 30 and is configured to detect amplitude information of the wireless signal, the detector 101 outputs an envelope signal according to the amplitude information, and the envelope signal may indicate a signal peak of the wireless signal; meanwhile, the detector 101 may perform down-conversion on the envelope signal, where the down-conversion is to convert a high-frequency signal into a lower-frequency signal by removing most of the carrier frequency in the high-frequency signal, so as to improve the efficiency of signal processing on the wireless signal.
It can be understood that the detector 101 has functions of performing down-conversion on the wireless signal and detecting amplitude information of the wireless signal, and no other electronic module is required, so that the circuit structure of the signal processing circuit 100 is simplified, and the power consumption of the signal processing circuit 100 is reduced.
The first filter 102 is electrically connected to the detector 101, and the first filter 102 is configured to filter the envelope signal after the down-conversion to filter out residual spurious signals and carrier harmonic signals in the envelope signal, so as to obtain a first filtered signal, and further improve a signal-to-noise ratio of the envelope signal.
In some embodiments, the first filter 102 may be a low pass filter.
The second amplifier 103 is electrically connected to the first filter 102, the second amplifier 103 is configured to amplify the first filtered signal, the comparator 104 is electrically connected to the second amplifier 103, and the comparator 104 is configured to compare the voltage value of the first filtered signal with a threshold signal and output an amplitude quantization signal according to the comparison result. It will be appreciated that the comparator 104 may act as an analog-to-digital converter that converts the analog first filtered signal by quantization into a digital amplitude quantized signal that may be indicative of amplitude information of an amplitude component of the wireless signal.
In some embodiments, the second amplifier 103 may be a variable gain amplifier.
The frequency divider 105 is electrically connected to the comparator 104 and the external clock source 106, and the frequency divider 105 is configured to receive a clock signal provided by the external clock source 106 and adjust the operating frequency of the comparator 104 according to the frequency of the clock signal. Specifically, the frequency divider 105 may be configured to have a preset frequency division coefficient, and the frequency divider 105 may convert the frequency of the clock signal provided by the external clock source 106 into the operating frequency of the comparator 104 according to the frequency division coefficient.
The phase processing circuit 50 may include a phase detector 201, a third amplifier 202, a second filter 203, an analog-to-digital converter 204, a frequency tracking circuit 205, a first oscillator 206, and a frequency calibration circuit 207, wherein the phase detector 201 is electrically connected to the first amplifier 30, the phase detector 201 is configured to receive the wireless signal output by the first amplifier 30, down-convert the wireless signal, and calculate a phase difference between the wireless signal and a reference signal to output a phase difference signal.
It can be understood that the phase detector 201 has the functions of performing down-conversion on the wireless signal and calculating the phase difference between the wireless signal and a reference signal, and does not need to provide other electronic modules (e.g., additional frequency synthesizers such as a phase-locked loop) to generate local oscillation signals, thereby simplifying the circuit structure of the signal processing circuit 100 and improving the energy efficiency of the phase processing circuit 50.
The third amplifier 202 is electrically connected to the phase detector 201, the third amplifier 202 is configured to amplify the phase difference signal, the second filter 203 is electrically connected to the third amplifier 202, and the second filter 203 is configured to filter the amplified phase difference signal and output a second filtered signal.
In some embodiments, the third amplifier 202 may be a variable gain amplifier, the second filter 203 may be a loop low pass filter, and the second filter 203 is configured to band-limit filter the amplified phase difference signal.
The first oscillator 206 is electrically connected to the second filter 203, and the first oscillator 206 is configured to output a reference phase signal to the phase detector 201 according to the second filtered signal. In some embodiments, the first oscillator 206 may be a voltage-controlled oscillator, the first oscillator 206 may control the frequency of the outputted reference phase signal according to the voltage of the second filtered signal, and the frequency f ═ v × Kvco of the reference phase signal is set, where v is the voltage value of the second filtered signal and Kvco is the voltage-controlled gain of the first oscillator 206.
It can be understood that the phase detector 201, the third amplifier 202, the second filter 203, and the first oscillator 206 form a phase tracking loop, and have a feature of closed-loop control, and the phase of the reference signal can be dynamically adjusted according to the first filtered signal, so as to improve the operation stability of the phase processing circuit 50 when the phase of the wireless signal fluctuates.
The analog-to-digital converter 204 is electrically connected to the second filter 203 and the external clock source 106, and the analog-to-digital converter 204 is configured to quantize the analog second filtered signal and convert the second filtered signal into a phase quantized signal.
In some embodiments, the analog-to-digital converter 204 may be a successive approximation analog-to-digital converter.
In this embodiment, the phase processing circuit 50 further includes a frequency tracking circuit 205 and a frequency calibration circuit 207, the frequency tracking circuit 205 is electrically connected to the first oscillator 206 and the second filter 203, and the frequency tracking circuit 205 is configured to compensate the low-frequency of the wireless signal when the carrier frequency of the wireless signal drifts at a low frequency; the frequency calibration circuit 207 is electrically connected to the phase detector 201 and the first oscillator 206, and the frequency calibration circuit 207 is configured to calibrate the frequency of the reference signal output by the first oscillator 206.
The demodulator 70 is electrically connected to the comparator 104 and the analog-to-digital converter 204, and the demodulator 70 is configured to receive the amplitude quantized signal output by the comparator 104 and the phase quantized signal output by the analog-to-digital converter 204, and map and combine the amplitude quantized signal and the phase quantized signal to obtain a demodulated signal, where the demodulated signal includes data of the wireless signal.
It is to be understood that the signal processing circuit 100 may enable only the first amplifier 30, the amplitude processing circuit 40 and the demodulator 70 to achieve continuous listening detection on the wireless signal, when the signal processing circuit 100 is in the low power consumption mode, the signal processing circuit 100 may receive and quantize the amplitude information in the wireless signal and output the amplitude quantized signal, and the demodulator 70 may enable the phase processing circuit 50 by comparing the amplitude quantized signal with the preset sequence to output an enable signal, so as to receive and process the amplitude information and the phase information of the wireless signal. Therefore, the signal processing circuit 100 does not need an independent wake-up response circuit, can further reduce the power consumption level, and is suitable for a wireless sensor network with duty cycle operation.
In this embodiment, the signal processing circuit 100 further includes a gain control circuit 60, the gain control circuit 60 is electrically connected to the first filter 102, the second amplifier 103 and the third amplifier 202, and the gain control circuit 60 is configured to adjust amplification gains of the second amplifier 103 and the third amplifier 202 according to a voltage value of the first filtered signal output by the first filter 102. Specifically, when the power of the wireless signal received by the first amplifier 30 changes, the voltage value of the first filtered signal also changes, and the gain control circuit 60 may calculate the signal output power at the receiving end of the first amplifier 30 based on the voltage value of the first filtered signal, and adjust the amplification gains of the second amplifier 103 and the third amplifier 202 based on the calculation result.
It can be understood that, when the power of the wireless signal changes, the gain control circuit 60 can ensure that the quantization threshold of the comparator 104 is appropriate, and keep the loop bandwidth of the phase processing circuit 50 stable, thereby reducing the error rate to the maximum extent, expanding the dynamic operating range of the signal processing circuit 100, and improving the dynamic response performance of the signal processing circuit 100, and the gain control circuit 60 can operate only in the header stage of the data frame of the wireless signal, so that the power consumption is low.
Referring to fig. 4, fig. 4 is a circuit diagram of the gain control circuit 60 of fig. 3. As shown in fig. 4, the gain control circuit 60 includes a second oscillator 301, a counter 302, a control circuit 303, and a resistor array 304.
The second oscillator 301 is electrically connected to the first filter 102, and the second oscillator 301 is configured to receive the first filtered signal and output an oscillating signal according to a voltage value of the first filtered signal, where a frequency of the oscillating signal is related to the voltage value of the first filtered signal. It is understood that the voltage value of the first filtered signal is envelope information of the first filtered signal, i.e. the frequency of the oscillation signal may be used to indicate the envelope information of the wireless signal.
The counter 302 is electrically connected to the second oscillator 301, and the counter 302 is configured to receive the oscillation signal, calculate a frequency of the oscillation signal, and output a frequency signal, where the frequency signal is configured to indicate frequency information of the oscillation signal, and further indicate amplitude information of the first filtered signal. Specifically, the counter 302 may count pulses of the oscillation signal in a unit time, thereby calculating the frequency of the oscillation signal.
The control circuit 303 is electrically connected to the counter 302, the resistor array 304, the second amplifier 103, and the third amplifier 202, and the control circuit 303 is configured to receive the frequency signal, calculate the received power of the wireless signal according to the frequency signal, and adjust the resistance value of the resistor array 304, the amplification gain of the second amplifier 103, and the amplification gain of the third amplifier 202 according to the received power. Specifically, the control circuit 303 may set a preset matching code table, and the control circuit 303 may map the frequency of the frequency signal to the received power of the first amplifier 30 according to the matching code table, so as to calculate the received power of the wireless signal according to the frequency of the frequency signal. The control circuit 303 may adjust the amplification gains of the second amplifier 103 and the third amplifier 202 according to the received power, for example, when the control circuit 303 calculates that the received power is lower than a preset threshold, the control circuit 303 may increase the amplification gains of the second amplifier 103 and the third amplifier 202 to ensure that a loop unit of the phase tracking loop is stable, so as to demodulate the wireless signal better.
The resistor array 304 is electrically connected to the comparator 104, the resistor array 304 may be formed by a plurality of resistors connected in series or in parallel, and the threshold voltage of the comparator 104 is adjusted according to a total resistance value of the resistors, for example, when the control circuit 303 calculates that the received power is lower than a preset threshold, the control circuit 303 may change the resistance value of the resistor array 304, so as to reduce the threshold voltage of the comparator 104, and ensure accuracy of quantization decision of the comparator 104.
Referring to fig. 5, fig. 5 shows a constellation diagram of the wireless signal received by the signal processing circuit 100 in fig. 2. As shown in fig. 5, the wireless signal may be a Star-type hexadecimal Quadrature Amplitude Modulation (Star-16 QAM) signal, and the Star-16 QAM signal includes a total of 16 different symbols, each represented by a four-bit binary number, where the highest-order digit represents the Amplitude bit of the symbol and the lower three-order digits represent the phase bit of the symbol. For example, the amplitude bit of the symbol 0111 is 1, the phase bit is 011, and on a constellation diagram, the amplitude bit corresponds to a mode of the symbol coordinate point and the coordinate origin, and the phase bit corresponds to an included angle between a connecting line of the symbol and the coordinate origin and a horizontal axis of a coordinate system.
It should be noted that, the amplitude bit and the phase bit are both encoded, and the actual amplitude value and the actual phase value represented by the amplitude bit and the phase bit are also different according to different encoding modes, and the encoding mode is not limited in any way in the present application.
It is to be appreciated that the Star-16 QAM symbol may be considered a sum of a Differential 8Phase Shift Keying (D8 PSK) symbol and an Amplitude Modulation (AM) symbol, wherein the D8PSK symbol corresponds to a Phase bit of the Star-16 QAM symbol and the D8PSK symbol may represent eight different phases, the AM signal corresponds to an Amplitude bit of the Star-16 QAM symbol and the AM symbol may represent two different amplitudes, e.g., the Star-16 QAM symbol 0111 may be considered a sum of the D8PSK symbol 011 and the AM symbol 1.
The operation of the signal processing circuit 100 is described below by taking three consecutive Star-16 QAM symbols 0001, 0111, 1110 as an example.
Referring to fig. 6, fig. 6 is a signal diagram illustrating the signal processing circuit 100 in fig. 2 processing a wireless signal.
The wireless signal is amplified by the first amplifier 30 to obtain a first amplified signal having a waveform as shown by a curve L1, wherein the first amplified signal includes three consecutive bands corresponding to symbols 0001, 0111, and 1110, respectively.
In the amplitude domain, the detector 101 receives the first amplified signal, and the waveform of the second amplified signal is obtained through the detection of the detector 101, the filtering of the first filter 102, and the amplification of the second amplifier 103 as shown by the curve L2, it can be understood that the amplitude bits corresponding to the symbol 0001 and the symbol 0111 in three consecutive bands of the second amplified signal are 1, the amplitude bit corresponding to the symbol 1110 is 0, and the amplitude value corresponding to the amplitude bit 0 is smaller than the amplitude value corresponding to the amplitude bit 1. The comparator 104 compares the second amplified signal with a threshold voltage, so as to quantize the analog second amplified signal into a digital amplitude quantized signal, and complete analog-to-digital conversion in an amplitude domain, and a waveform of a signal output by the comparator is shown as a curve L3.
In the phase domain, the phase detector 201 receives the first amplified signal, and obtains a second filtered signal waveform as shown by a curve L5 through the amplification of the third amplifier 202 and the filtering of the second filter 203, and it can be understood that the second filtered signal includes three consecutive bands, corresponding to the phase values of the symbols 0001, 0111 and 1110. The phase position of the initial reference signal is 000, and referring to the constellation diagram shown in fig. 3, the counterclockwise direction is positive, the phase difference between the symbol 0001 and the reference signal is 0, the phase difference between the symbol 0111 and the reference signal is +2, and the phase difference between the symbol 1110 and the reference signal is-3, corresponding to three consecutive voltage values 0, +2, -3 in the second filtered signal. The analog-to-digital converter 204 performs analog-to-digital conversion on the second filtered signal, so as to obtain a digital phase quantization signal, thereby completing analog-to-digital conversion in a phase domain.
The demodulator 70 receives the amplitude quantized signal output by the comparator 104 and the phase quantized signal output by the analog-to-digital converter 204, synthesizes the amplitude quantized signal and the phase quantized signal, and demodulates original symbols 0001, 0111 and 1110 through mapping, thereby completing the demodulation process.
Therefore, according to the signal processing circuit and the receiver provided by the embodiment of the application, by arranging the amplitude processing circuit and the phase processing circuit, the wireless data based on the polar coordinate form is decoupled and separated from the amplitude and the phase, and the signal processing and the demodulation are respectively carried out, so that the complexity and the power consumption of the receiver circuit are reduced, and meanwhile, when the amplitude processing circuit is singly started, the average power consumption of the receiver can be further reduced under the condition that the signal modulation mode is not changed.
It should be understood by those skilled in the art that the above embodiments are only for illustrating the present application and are not used as limitations of the present application, and that suitable modifications and changes of the above embodiments are within the scope of the claims of the present application as long as they are within the spirit and scope of the present application.
Claims (10)
1. A signal processing circuit, characterized in that the signal processing circuit comprises:
the amplitude processing circuit is used for receiving a wireless signal output by a wireless device and converting an amplitude component in the wireless signal into an amplitude quantized signal, wherein the amplitude component is used for indicating amplitude information in the wireless signal;
the phase processing circuit is used for receiving the wireless signal output by the wireless device and converting a phase component in the wireless signal into a phase quantization signal, wherein the phase component is used for indicating phase information in the wireless signal;
and the demodulator is electrically connected with the amplitude processing circuit and the phase processing circuit and used for demodulating the wireless signal according to the amplitude quantized signal and the phase quantized signal.
2. The signal processing circuit of claim 1, further comprising a first amplifier electrically connected to the amplitude processing circuit and the phase processing circuit, the first amplifier being configured to amplify the wireless signal and output the amplified wireless signal to the amplitude processing circuit and the phase processing circuit.
3. The signal processing circuit of any of claims 1-2, wherein the amplitude processing circuit comprises:
a detector for detecting amplitude information of the wireless signal and outputting an envelope signal according to the amplitude information, wherein the envelope signal is used for indicating a signal peak value of the wireless signal;
the first filter is electrically connected to the detector, and is used for receiving the envelope signal and filtering the envelope signal to obtain a first filtered signal;
the second amplifier is electrically connected with the first filter, is used for receiving the first filtering signal and is used for amplifying the first filtering signal to obtain a first amplifying signal;
and the comparator is electrically connected with the second amplifier and used for receiving the first amplified signal and converting the first amplified signal into an amplitude quantization signal.
4. The signal processing circuit of claim 3, wherein the phase processing circuit comprises:
the phase discriminator is used for detecting the phase difference between the phase of the wireless signal and the reference signal to obtain a phase difference signal;
the third amplifier is electrically connected with the phase discriminator, and is used for receiving the phase difference signal and amplifying the phase difference signal to obtain a second amplified signal;
the second filter is electrically connected to the third amplifier, and is used for receiving the second amplified signal and filtering the second amplified signal to obtain a second filtered signal;
the first oscillator is electrically connected with the second filter and the phase discriminator, is used for receiving the second filtering signal and is used for outputting a reference signal to the phase discriminator according to the second filtering signal;
and the analog-to-digital converter is electrically connected with the second filter and is used for converting the second filtered signal into a phase quantization signal.
5. The signal processing circuit of claim 4 wherein the phase processing circuit further comprises a frequency tracking circuit and a frequency calibration circuit;
the frequency tracking circuit is electrically connected with the second filter and the first oscillator and is used for compensating the carrier frequency drift of the wireless signal;
the frequency calibration circuit is electrically connected to the first oscillator and the phase detector, and is configured to calibrate the frequency of the reference signal.
6. The signal processing circuit of claim 4, further comprising a gain control circuit electrically connected to the second amplifier, the first filter, and the third amplifier for adjusting amplification gains of the second amplifier and the third amplifier according to the first filtered signal.
7. The signal processing circuit of claim 6, wherein the gain control circuit comprises a second oscillator, a counter, a control circuit, a resistor array;
the second oscillator is electrically connected to the first filter and is used for outputting an oscillation signal according to the first filtering signal, wherein the oscillation signal is used for indicating amplitude information of the first filtering signal;
the counter is electrically connected to the second oscillator and is used for receiving the oscillation signal, calculating the frequency of the oscillation signal and outputting a frequency signal, wherein the frequency signal is used for indicating the frequency information of the oscillation signal and further indicating the amplitude information of the first filtering signal;
the control circuit is electrically connected with the counter, the resistor array, the second amplifier and the third amplifier, and is used for receiving the frequency signal, calculating the receiving power of the wireless signal according to the frequency signal, and adjusting the resistance value of the resistor array, the amplification gain of the second amplifier and the amplification gain of the third amplifier according to the receiving power;
the resistor array is electrically connected to the comparator, and the threshold voltage of the comparator is adjusted by the resistor array according to the resistance value of the resistor array.
8. The signal processing circuit of claim 1 wherein the demodulator outputs an enable signal to the phase processing circuit based on the amplitude quantized signal matching a predetermined sequence, the enable signal for enabling the phase processing circuit.
9. A chip, wherein the chip comprises:
the signal processing circuit of any of claims 1-8; and
and the matching circuit is electrically connected with the antenna and the signal processing circuit and is used for matching the input impedance of the antenna and the signal processing circuit.
10. A receiver, characterized in that the receiver comprises a chip according to claim 9.
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