CN115940977A - Signal receiver awakening circuit - Google Patents
Signal receiver awakening circuit Download PDFInfo
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- CN115940977A CN115940977A CN202310150210.8A CN202310150210A CN115940977A CN 115940977 A CN115940977 A CN 115940977A CN 202310150210 A CN202310150210 A CN 202310150210A CN 115940977 A CN115940977 A CN 115940977A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application discloses signal receiver wake-up circuit includes: the peak detection circuit detects a pulse train of an input signal and outputs a direct current signal to the low-pass filter circuit, the low-pass filter circuit separates out a low-frequency signal and transmits the signal to the threshold comparison module, the threshold comparison module outputs a high level to the anti-interference delayer, and the anti-interference delayer filters a narrow pulse width signal to the input end of the signal receiver; the anti-interference delayer is adopted to filter the narrow pulse signal, so that the signal receiver is prevented from being frequently awakened by the narrow pulse signal, the signal receiver consumes extremely low power and current, and the technical scheme can obviously prolong the standby time of equipment powered by a battery.
Description
Technical Field
The invention relates to the technical field of wired communication, in particular to a signal receiver wake-up circuit.
Background
To reduce power consumption of a wired communication receiver, the receiver is in a sleep, low power, or power down state when the channel is idle, i.e., when the transmitter is not transmitting signals. In order to detect the wake-up signal sent by the transmitter at any time, a part of circuits of the conventional receiver are still in a normal working state, and the current and power consumption are relatively large.
The traditional technical implementation is to put the front end of the receiver into a receiving state, so that the current and power consumption are relatively large, and for a battery-powered device, the disadvantage of large power consumption is particularly prominent, and the endurance time of the system in the battery-powered state is seriously influenced.
Disclosure of Invention
In view of the above problems in the prior art, it is an object of the present invention to provide a signal receiver wake-up circuit for waking up a signal receiver in a sleep or power-down state.
The specific technical scheme is as follows:
designing a signal receiver wake-up circuit, comprising: a voltage input terminal receiving a signal of the transmitter; a peak detection circuit connected to the voltage input terminal; the low-pass filter circuit is connected with the output end of the peak detection circuit; the threshold comparison module is connected with the output end of the low-pass filter circuit; the anti-interference delayer is connected with the output end of the threshold comparison module;
the peak detection circuit detects a pulse train of an input signal and outputs a direct current signal to the low-pass filter circuit, the low-pass filter circuit separates out a low-frequency signal and transmits the signal to the threshold comparison module, the threshold comparison module outputs a high level to the anti-interference delayer, and the anti-interference delayer outputs a narrow pulse width signal to the input end of the signal receiver.
Preferably, the peak detection circuit performs positive and negative peak detection on the voltage input terminal to obtain a positive peak detection signal and a negative peak detection signal.
Preferably, the peak detector circuit is mainly composed of a peak detector and a capacitor, and processes the signal of the transmitter to obtain a relatively gentle dc signal
Preferably, the threshold comparison module includes an in-phase comparator, the output voltage of the signal is connected to the in-phase end of the in-phase comparator, and the reference voltage Vr is connected from the inverting input end.
Preferably, the peak detector circuit is mainly composed of a peak detector and a capacitor, and when the input signal is in a peak period, the peak detector charges a charging capacitor to a peak value, and the charging capacitor maintains the peak value of the pulsating direct current signal output by rectification to obtain a relatively gentle direct current signal.
Preferably, the low-pass filter circuit is mainly composed of a capacitor and a current source, and is used for performing low-pass filtering processing on the signal, filtering out a high-frequency signal, and separating out a low-frequency signal.
Preferably, the low-pass filter circuit passes the low-frequency signal lower than a predetermined frequency, and the high-frequency signal higher than the predetermined frequency is shunted to a reference ground without output, so as to achieve the purpose of low-pass.
Preferably, the threshold comparison module detects the low frequency signal, and when the output voltage of the low frequency signal is higher than the reference voltage Vr, the threshold comparison module outputs a high level.
Preferably, the high level wakes up a signal receiver with higher power consumption through the anti-interference delayer.
Preferably, the immunity delay filters a narrower pulse input signal.
The technical scheme has the following advantages or beneficial effects:
the signal receiver awakening circuit is used for realizing the detection of received signals in a very simplified mode, a peak detection circuit and a low-pass filter circuit are used for processing pulses of input signals to obtain low-frequency direct current signals, a threshold comparison module is used for outputting high levels, the high levels pass through the anti-interference delayer, the anti-interference delayer filters narrow pulse signals, and the signal receiver with high power consumption is awakened to receive normal signals; the anti-interference delayer filters the narrow pulse signal, avoids signal receiver to be awakened by the narrow pulse signal frequently for signal receiver consumes extremely low power and electric current, and to battery powered equipment, this technical scheme can show extension stand-by time.
Drawings
Fig. 1 is a functional block diagram of a wake-up circuit of a signal receiver according to the present invention.
Illustration of the drawings:
the device comprises a peak detection circuit 1, a low-pass filter circuit 2, a threshold comparison module 3, an anti-interference delayer 4 and a signal receiver 5.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
Referring to fig. 1, a signal receiver wake-up circuit includes: a voltage input terminal receiving a signal of the transmitter; a peak detection circuit 1 connected to the voltage input terminal and detecting a pulse train of an input signal; a low-pass filter circuit 2 connected to the output end of the peak detector circuit 1; the threshold comparison module 3 is connected with the output end of the low-pass filter circuit 2; and the anti-interference delayer 4 is connected with the output end of the threshold comparison module 3.
The peak detection circuit 1 performs positive and negative peak detection on the voltage input terminal to obtain a positive peak detection signal and a negative peak detection signal.
The peak detection circuit 1 is mainly composed of a peak detector and a capacitor, when an input signal is in a peak time period, the peak detector charges a charging capacitor to a peak value, and the charging capacitor keeps the peak value of a pulsating direct current signal output by rectification to obtain a relatively gentle direct current signal. The input to the peak detector circuit is the signal being detected and the output is ideally a stable voltage.
The peak detector circuit 1 is used for a peak detector circuit for a narrow pulse test, and requires that a capacitor can be charged to a peak value quickly in a short time. The peak detector may alternatively be a differential peak detector comprising two peak detectors arranged symmetrically to generate an output voltage in response to a received input signal by means of a positive peak detection circuit and a negative peak detection circuit.
The triode which can be adopted in the peak detector is an insulated gate bipolar transistor which is a solid semiconductor device with multiple functions of detection, rectification, amplification, switching, a regulator, signal modulation and the like, and can control output current according to input voltage.
The low-pass filter circuit 2 is mainly composed of a capacitor and a current source, and is used for performing low-pass filtering processing on the positive peak detection signal and the negative peak detection signal, filtering out high-frequency signals, and separating out low-frequency signals. The low-pass filter circuit 2 allows the low-frequency signal lower than the predetermined frequency to pass through, and the high-frequency signal higher than the predetermined frequency is shunted to the reference ground without output, so as to achieve the purpose of low-pass.
The threshold comparison module 3 detects the low-frequency signal, and when the output voltage of the low-frequency signal is higher than the reference voltage Vr, the threshold comparison module 3 outputs a high level.
The high level wakes up the signal receiver 5 with higher power consumption through the anti-interference delayer 4.
The threshold comparison module 3 comprises an in-phase comparator, the output voltage of the low-frequency signal is connected to the in-phase end of the in-phase comparator, and the reference voltage Vr is connected from the reverse-phase input end. The in-phase comparator is used for judging whether the input voltage is higher than a higher voltage to be limited or not, and outputting a high potential when the input voltage is higher than a reference voltage; the reference voltage Vr may be provided by a series node between a current source and a resistor, which are connected in series between a power supply and a ground reference.
The anti-interference delayer 4 filters the input signal with narrow pulse width, and prevents the signal receiver from being frequently awakened by the narrow pulse signal.
The working principle is as follows: referring to fig. 1, the micro-power consumption received signal detector of the present invention includes a peak detection circuit 1, a low pass filter circuit 2, a threshold comparison module 3, and an interference-free delay 4. When a transmitter signal appears in a channel, a peak detection circuit 1 detects a signal pulse train, smoothes the waveform of the pulse train, and converts the pulse train into a relatively stable direct current signal; the low-pass filter circuit 2 passes the low-frequency signal lower than a predetermined frequency; if the signal is higher than the preset threshold voltage, the comparator outputs high level; after passing through the anti-interference delayer 4, the narrow pulse signal is filtered, the signal receiver is prevented from being frequently awakened by the narrow pulse signal, the signal receiver consumes extremely low power and current, and for equipment powered by a battery, the technical scheme can obviously prolong the standby time.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A signal receiver wake-up circuit, comprising:
a voltage input terminal receiving a signal of the transmitter;
a peak detection circuit (1) connected to the voltage input terminal;
a low-pass filter circuit (2) connected to an output terminal of the peak detector circuit (1);
the threshold comparison module (3) is connected with the output end of the low-pass filter circuit (2);
the anti-interference delayer (4) is connected with the output end of the threshold comparison module (3);
peak detection circuit (1) detects input signal's pulse train, output direct current signal extremely low pass filter circuit (2), low frequency signal is isolated in low pass filter circuit (2), and transmission signal extremely threshold value comparison module (3), threshold value comparison module (3) output high level to anti-interference delayer (4), anti-interference delayer (4) filter narrow pulse width signal to the input of sending to signal receiver (5).
2. The signal receiver wake-up circuit of claim 1, wherein: the peak detection circuit (1) performs positive and negative peak detection on the voltage input end respectively to obtain a positive peak detection signal and a negative peak detection signal.
3. The signal receiver wake-up circuit of claim 1, wherein: the peak detection circuit (1) mainly comprises a peak detector and a capacitor, and processes the signal of the transmitter to obtain a gentle direct current signal.
4. The signal receiver wake-up circuit of claim 1, wherein: the threshold comparison module (3) comprises an in-phase comparator, the output voltage of a signal is connected to the in-phase end of the in-phase comparator, and the reference voltage Vr is connected from the reverse-phase input end.
5. The signal receiver wake-up circuit of claim 4, wherein: the peak detection circuit (1) mainly comprises a peak detector and a capacitor, when an input signal is in a peak time period, the peak detector charges a charging capacitor to a peak value, and the charging capacitor keeps the peak value of a pulsating direct current signal output by rectification to obtain a gentler direct current signal.
6. The signal receiver wake-up circuit of claim 4, wherein: the low-pass filter circuit (2) mainly comprises a capacitor and a current source and is used for carrying out low-pass filtering processing on signals, filtering high-frequency signals and separating low-frequency signals.
7. The signal receiver wake-up circuit of claim 6, wherein: the low-pass filter circuit (2) allows the low-frequency signals lower than the preset frequency to pass through, and the high-frequency signals higher than the preset frequency are shunted to the reference ground without output, so that the purpose of low-pass is achieved.
8. The signal receiver wake-up circuit of claim 6, wherein: the threshold comparison module (3) detects the low-frequency signal, and when the output voltage of the low-frequency signal is higher than the reference voltage Vr, the threshold comparison module (3) outputs a high level.
9. The signal receiver wake-up circuit of claim 8, wherein: and the high level passes through the anti-interference delayer (4) to wake up the signal receiver (5) with higher power consumption.
10. The signal receiver wake-up circuit of claim 8, wherein: the interference rejection delayer (4) filters the input signal of the narrower pulse.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310150210.8A CN115940977B (en) | 2023-02-22 | 2023-02-22 | Signal receiver wake-up circuit |
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| CN202310150210.8A CN115940977B (en) | 2023-02-22 | 2023-02-22 | Signal receiver wake-up circuit |
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| CN115940977B CN115940977B (en) | 2023-06-02 |
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