WO2003077465A1

WO2003077465A1 - Device and method for recovering data

Info

Publication number: WO2003077465A1
Application number: PCT/EP2002/002596
Authority: WO
Inventors: Tord Haulin
Original assignee: Optillion Ab
Priority date: 2002-03-08
Filing date: 2002-03-08
Publication date: 2003-09-18
Also published as: AU2002257637A1

Abstract

A circuit and methods for recovering data, comprising means for acknowledging the data pattern of successively recovered digital data; means for comparing acknowledged data pattern against pre-stored data pattern; a unit for generating based on a first parameter set a tracking clock signal tracking phase variations up to a frequency limit in the data clock of the digital data signal; and/or for generating based on an other parameter set a phase lag value or a phase lead value indicative of a phase range of jitter in the digital data relative to tracking clock signal for higher frequencies. The circuit (or methods) further comprising a circuit for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and with a phase offset from the tracking clock signal adjustable in accordance with said phase lag value or said phase lead value.

Description

SPECIFICATION

DEVICE AND METHOD FOR RECOVERING DATA

TECHNICAL FIELD

The present invention relates to a device and a method for recovering data, and in particular for recovering data from a digital data signal received via a frequency limited transmission medium.

BACKGROUND OF THE IWEΝTIOΝ

A signal, which is in its analogue state a continuously variable voltage or current, is represented digitally by a limited number of discrete numerical values. These numerical values represent the signal only at specific time points, or sampling instants . Sampling instants are determined by various devices for clock and data recovery (CDR) .

Digital signal transmission is robust with respect to amplitude-domain-distortion, caused by e.g. line noise, flutter and cross-talk. However, technical actualities like oscillator instability, cable loss or noise pickup often affecting the digital signal in the time domain as jitter has become a significant source of errors when clock frequencies are increased. Jitter can occur on the interface carrying the digital signal at the end of a link like a transmission line and can result in data errors or loss of lock, which represent fault conditions . It should be taken in account in devices for clock and data recovery (CDR) .

Jitter is the variation in time of an event such as a regular clock signal from nominal. For example, the jitter on a regular clock signal is the difference between the actual pulse transition times of the real clock and the transition times that would have occurred had the clock been ideal . Against this nominal reference, the transitions of many of the pulses in a jittered data stream are varying in time from the ideal clock timing. That means jitter may be seen as a kind of unwanted phase noise of the digital signal.

The jitter component can be extracted from the clock or digital signal to be analysed as a separate signal. Useful ways of characterizing jitter comprise examining its frequency spectrum and identifying the significant frequency components of the jitter itself.

When very little jitter is present, the pulse transitions are moved back or forth by small time measures only. With an increase of jitter the transitions move across a larger time range. A measure of time displacement is called jitter amplitude and is expressed in units of time. The rate at which this phase-shifting is taking place is called jitter frequency. Like other noise or interference signals, jitter can be deterministic, random or a mixture of both. Jitter on a digital signal can be observed as pulse transitions that occur slightly before or after the transitions of the ideal signal .

In practice, serial data streams are interpreted by "sampling" at instants determined by a clock signal, synchronous to the serial data stream. Sometimes the source of the serial data stream also provides a synchronous clock signal, sometimes it does not. To obtain a clock, an oscillator can be phase-locked to the digital signal, using a phase-locked loop (PLL) . A PLL is a basic clock and data recovery block (CDR) . The basic PLL architecture comprises a phase detector, a low pass filter and a voltage controlled oscillator (VCO) ,

A PLL provides a clock signal useful as a sampling clock for data recovery. In the low frequency range up to a frequency related to the PLL loop filter corner frequency, the jitter on this clock signal is essentially equal to the input data signal jitter in the same frequency range. This is a key foundation for successful data recovery. In the frequency range above the PLL loop filter corner frequency however, input data and PLL clock signal j itter spectra are essentially uncorrelated.

The critical parameters of the PLL are intrinsic, i.e. additionally produced phase noise and jitter, DC phase error, acquisition time and acquisition range. Phase noise in the frequency domain translates into jitter in the time domain.

The time the PLL takes to converge within a certain phase error of the input signal is the acquisition time. It is inversely proportional to the loop bandwidth. The frequency range that the PLL can acquire lock to is called acquisition range. The acquisition range is directly proportional to the loop bandwidth of the PLL.

In the meantime the abovementioned basic PLL has been subject to several improvements. Nowadays monolithic PLLs are using phase frequency detectors (PFD) instead of phase detectors, charge pumps with filter functionality as loop filters, and an optional frequency divider in the feedback path. The frequency divider enables the PLL to lock to a frequency larger than the input frequency. This is used more in frequency synchronization and clock synthesis rather than CDR. The PFD effectively increases lock range and improves acquisition time without worsening its ability to filter input phase noise. The charge pump is used in conjunction with a PFD, eliminating any DC phase error in the PLL.

A variant of the PLL called the delay locked loop (DLL) is another popular unit in CDR. The delay locked loop comprises a controlled delay line (VCDL, for voltage controlled delay line) , which is controlled by the output of a loop filter like a charge pump and which is outputting a shifted clock signal. The loop filter filters the output of a phase detector or PFD, which compares a reference clock or input clock with the output of the delay line.

The major drawback of this system is the limited phase acquisition range. The VCDL has a bound on the minimum and maximum possible delays. Comparing basic PLL versus DLL shows the following major differences.

A basic PLL is a second or third order loop and not always stable. Because of the VCO, frequency synthesis is possible. With a PLL input jitter is filtered but phase error accumulates resulting in longer locking time. Also the frequency capture range is limited, the phase capture range is unlimited.

A DLL is a first order loop and always stable. It does not generate intrinsic jitter and the phase error does not accumulate. It is not able to adjust its frequency because of the usage of an VCDL, and its phase capture range is limited. Phaseblenders or phase rotators are "endless" "wrap-around" delay lines.

With some simplification, both basic PLL and DLL loop filters can be looked upon as creating a signal (having jitter) proportional to the input jitter for jitter frequencies lower than the loop filter bandwidth, and averaging jitter components with a jitter frequency higher than the loop filter bandwidth. An other type of PLL, the so called binary bang-bang PLL has the same basic structure with one main difference. In binary bang-bang PLLs the charge packets, i.e. the loop filter output, are of a unit size only; positive, when the clock signal should be advanced, and negative, when the clock signal should be retarded. At equilibrium, alternating unit size adjustments would occur. This kind of PLL is most commonly used together with sample-mode front-end data receivers. Then, two samples of the input data are taken per unit interval, to provide information to the phase lock procedure. When the PLL has locked, one sample is taken when the input data is stable and another sample is taken at the data transition instant. The separation between the samples is half a clock cycle. The phase of the sampling clock is advanced or retarded depending on whether the data edge occurred before or after the transition sample. With some jitter on the input data relative to the sampling clock, this kind of PLL will operate with the median of the data edge positions as the target for the non-strobing edge of the recovered clock.

Linear phase comparator PLL and DLL based data recovery circuits gather information on the phase difference between data edges and the sampling clock edge. The data sampling clock edge is phase adjusted in a feedback arrangement based on a single operation on the series of phase differences maintaining a weighted average of the phase differences by low pass filtering. In case of digital PLLs there is a digital calculation of the data sampling instant based on low pass filtering.

Data and clock recovery devices employing PLLs or DLLs as mentioned above are quite useful for clock recovery of signals having low frequency jitter or signals having merely random, i.e. pattern independent jitter components.

An other source of jitter results from the non-ideal nature of interconnections like transmission lines. Real cables cause dispersion of the pulse transitions. Since a digital signal is not a perfectly regular pulse stream of embedded ones or zeros but consists of bit patterns which may be changing all the time, the presence of dispersion gives rise to inter-symbol interference. If a digital signal is transmitted through a cable then the data pattern in the signal will modulate the signal timing, thus causing pattern- dependent (or deterministic) jitter. The amount of jitter depends on for example the length and bandwidth of the cable. The proximity and width of data pulses effectively shift the baseline for the neighbour pulses, and with the longer rise and fall times in the cable, the transitions are moved from their ideal zero crossings. Mechanisms that distort the symmetry of the waveform, such as un-equal rise and fall times of the data pulses, DC offsets in differential line receivers, logic level miss-matches between devices and transition asymmetries within devices generate additional pattern-dependent jitter.

Since in many cases the data signal is used to extract the data clock, it is possible to induce jitter on the clock as a result of the data modulation. This leads to mechanisms of interference between the data and the timing of the clock. A smearing of the waveform as a result of cable losses is one such mechanism.

US 6,178,213 Bl discloses the suggestion to place in an ideal data cell the optimum data strobe point in the middle of the opening of the eye pattern. Linear PLLs place the strobe point half a cycle from the average edge position of all jitter components with a bandwidth higher than the loop bandwidth. This is the best positioning if the input data signal has a symmetric jitter probability distribution for the jitter components with a frequency higher than the loop bandwidth. The same holds true for binary bang-bang PLLs. Strobing data in anti-phase with the median of the data transition jitter distribution also falls halfway between the jitter peaks, which is the best for symmetric distributions. However, jitter probability distributions are often non- symmetric . Since the PLL is capable of tracking low frequency jitter, just for the high frequency jitter components that placement of the strobe point half-way between peak values is of importance. Unfortunately, the jitter components with high jitter frequency in particular tend to haven non-symmetric edge position probability distributions. The above-mentioned pattern-dependent jitter is an example of high frequency jitter with non-symmetric probability distribution. Any PLL will have a limit for how much jitter it can handle. While data rates for transmitted signals increase more than the quality of transmission media, the relative jitter on data signals is increasing. Therefore optimum date strobe point positioning is becoming increasingly important.

Recently, a significant step forward was taken for an non- compromised dealing with non-symmetric data edge position probability distributions, as described by Y. Moon, D-K Jeong, and G. Ahn in "A 0.6 - 2.5 Gbaud CMOS Tracked 3x- Oversampling Transceiver with Dead-Zone Phase Detection for Robust Clock/Data Recovery", 2001 IEEE International Solid State Circuits Conference, pp. 212-213, Feb. 2001. This bang- dead-bang-type PLL has three data samplers with 120 degrees phase separation. One is used for data strobing and the other two for phase adjustment. As long as data edges fall between the two-phase adjustment samples, no phase adjustment is done. For low jitter amplitudes this creates a dead-band, which is acceptable for low jitter amplitudes if the low frequency jitter is insignificant. For high amplitude high frequency jitter, the phase adjustment samplers 120 degrees apart will ensure that the data sample is centred relative to the tails of the edge placement probability distributions. In equilibrium, the number of edges occurring before the early phase sample instant should equal that of edges occurring after the late phase sampling instant. Thus, the desired property of taking well-centred data samples also on data with non-symmetric edge placement probability distributions can be achieved. For this to occur however the input data signal jitter spectrum must have very low amplitude on all jitter components with frequencies less than the loop bandwidth of the PLL. In presence of low frequency jitter, this PLL is crippled in its ability to track the jitter components. Much fewer phase adjustment samples are available since it operates in the tails of the jitter distribution. This leads to a larger tracking error. This PLL, described by Moon, Jeong and Ahn as mentioned above, will not reach its high gain point until the data-sampling phase offset has moved 60 degrees away from the optimum. In most cases this offset deteriorates the data strobe margin more than what is gained from centring the data strobe between the tails of the jitter distributions .

DESCRIPTION OF THE INVENTION

Therefore, it would be desirable to provide a data recovery circuit with an improved capability of recovering data from a digital data signal received via a frequency limited transmission medium, a line receiver circuit comprising such data recovery circuit, and an improved method of recovering data from a digital data signal received via a frequency limited transmission medium.

According to an embodiment of one aspect of the present invention, a data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprises a phase tracking circuit for generating a tracking clock signal which tracks phase variations of the digital data signal, the phase variations tracked by the phase tracking circuit having frequency components reaching up to a tracking frequency limit; a circuit for analysing phase jitter in the digital data signal relative to the phase of the tracking clock signal, and outputting a phase lag value and a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to the tracking clock signal; a sampling clock generating circuit for generating a sampling clock signal with a phase related to the phase of the tracking clock signal, and with a phase offset from the tracking clock signal which is adjustable in accordance with the phase lag value and the phase lead value; and a data sampling circuit coupled to receive the digital data signal from the transmission medium, for sampling the amplitude of the digital data signal at time instants determined by the sampling clock signal.

The data recovery circuit according to an embodiment of the present invention creates a data-sampling signal (sampling clock) from multiple signal processing operations on a set of input variables, one of which is the data stream to be interpreted or recovered. The data recovery circuit generates one or more output signals one of which is the input data signal retimed to a local clock. Some embodiments of the invention may create auxiliary signals supporting data recovery process. The input variables can also include feedback from more than one signal created by the invented data recovery circuit.

The tracking clock signal tracks the phase of the input data signal. This tracking is accomplished in a feedback arrangement continuously adjusting the phase of an internal reference clock signal. This tracking clock signal can be separate from the clock signal for strobing input data signal. This is advantageous in order to optimize the synthesis procedures for the tracking clock signal just for phase tracking. Bit errors that would occur in presence of severe jitter if this signal was used for data strobing can be avoided by using another set of synthesis operations to create a data strobing sampling clock signal expressed as an offset from the tracking clock signal. This sampling clock signal can then be synthesized for data strobing without limitations implied from optimising the phase tracking mechanism. The phase tracking mechanism generating the tracking clock signal is preferably designed to track jitter components with lower jitter frequencies. The jitter components with higher frequencies then contribute to a remaining eye closure relative to the tracking clock signal. For the tracking clock signal the data recovery circuit may gather an estimate of the average, mean value or the median of the distribution of jitter in the stop band of the loop filter or any other suitable estimate. All data edges advantageously contribute to update information phase position of data transitions. However, practically it may be sufficient to calculate this estimate, e.g. the average or median, over a limited history of data transitions.

The weighting factor for the contribution to the median or average from a particular data transition may be de-rated with aging by a roll off function. The loop bandwidth of the PLL or DLL is a measure for this in the frequency domain. This means the contribution to the average, mean or median comes mainly from jitter components with a jitter frequency higher than the loop bandwidth. The average, mean or median value varies over time in accordance with the jitter components with a jitter frequency lower than the loop bandwidth of the PLL or DLL. In addition to keeping track of for example the mean or the median of the jitter distribution, the data recovery circuit according to the abovementioned embodiments of the invention advantageously maintains two more measures of properties of the high frequency portion of the jitter distribution, namely negative and positive jitter peak offsets from the estimate, e.g. mean value, average or median. These peak values are used for computing the optimum data strobe phase. Even if in the abovementioned embodiments of the invention negative and positive jitter peak offsets from the estimate are used to improve the recovering capability, depending on a specific case, i.e. depending on the data signal frequency, the transmission line/interface, the type of data coding etc. it can be sufficient to employ only a negative or only a positive jitter peak offset.

Tracking of low frequency jitter is advantageously separated from extracting an offset value - for example an average or median value - of pattern dependent high frequency jitter. The time constant used in calculating such contribution - for example the average or median - of the high frequency jitter is independent from the time constant used for maintaining an estimate of the data pattern dependent high frequency jitter peak value deviation from the tracking clock - for example the average or median data edge position value - used as an estimate of the instantaneous value of the low frequency jitter components. This leads to several advantages.

One significant advantage is that according to one embodiment of the invention phase variations due to low frequency jitter can be tracked from DC up to a higher frequency by taking the average or median of the high frequency jitter over a shorter period of time. Thus a smaller portion of the high frequency jitter spectrum contributes to eye diagram closure relative to the recovered clock. The data recovery circuit according to such embodiments of the invention can thereby withstand a larger total jitter.

Another significant advantage is that longer-term variations in exposure of the high frequency jitter can be coped with independently, without having to compromise the capability of tracking a wide spectrum of low frequency jitter by using a high PLL or DLL bandwidth.

The dominant parts of the high frequency jitter are inter- symbol interference and duty cycle distortion. Inter-symbol interference is caused mainly by bandwidth limitations in any element the signal has passed from the source to the destination. Duty cycle distortion occurs because of imperfections in the transmitter. Neither of these causes to high frequency jitter varies much over time. While the tracking clock - for example the average or median data edge position value - used as an estimate of the instantaneous value of the low frequency jitter components preferably should be updated as often as possible for best tracking - the high frequency jitter peak deviations from the average or median are fairly constant over time. The amount of inter-symbol interference exposed however, depends on the spectrum of the data pattern transmitted. Data patterns that are highly randomised provide a fairly constant exposure of the inter-symbol interference just about the whole high frequency jitter deviation from the tracking clock for example the average or median data edge position value - used as an estimate of the instantaneous value of the low frequency jitter components. Less randomised data patterns are fairly common. Idle signalling, dark image, and synchronization training are just few examples of conditions that often are mapped to some repetitive data pattern with low variability. Depending on the data content of these patterns, varying fractions of the maximum peak high frequency jitter on a given link is exposed. Often, some form of framing or packetizing of the data puts a limit on duration of a repetitive pattern. By using a time constant for adjusting the relative peak jitter value estimates that is long enough relative to the coding scheme, peak value estimates of the high frequency itter can be captured.

Since the data recovery circuit according to some embodiments of the invention uses one time constant for separating high frequency jitter from low frequency jitter and another for memorizing relative peak levels of jitter the adjustment to data pattern properties can be done without compromising tracking of low frequency jitter. The optimum data strobe position can advantageously be calculated from the relative peak jitter estimates.

Some of the data patterns that expose only a narrow jitter distribution have an average or median that is significantly shifted from the average or median of the full jitter distribution. If such a pattern lasts long enough to allow the low frequency jitter tracking mechanism (i.e. the tracking clock circuit according to the abovementioned embodiments) to adjust to the new average of median, the data strobe (i.e. the sampling clock) will also be adjusted accordingly. That adjustment is not desired. Data strobing moves toward the centre of the wider eye opening due to exposure of jitter primarily in one end of the full jitter distribution only. The exposed high frequency jitter distribution can change instantaneously with the pattern. If a data pattern exposing the full high frequency jitter distribution comes back, bit errors can occur if the pattern dependent offset is larger than the remaining strobe margin for patterns exposing the full high frequency jitter distribution. The data recovery circuit according to preferred embodiments of the invention can compensate for average of median shifts due to long sequences of low-jitter symbol patterns by creating a replica shift from the recovered data pattern using for example the same time constant as that for calculating the weighted average or median data edge position value used as an estimate of the instantaneous value of the low frequency jitter components. The magnitude of this compensation shift is a function of the ratio between the j itter exposed by the random pattern to that exposed by the low jitter pattern. The sign of the compensation is determined by the ratio of single to multiple equal sequences having occurred during the interval of the high frequency jitter averaging period.

The present invention can be applied to any phase or delay locked loop. With a linear phase comparator embodiment, preferably the average data edge position value may be used as an estimate of the instantaneous value of the low frequency jitter components implemented, while sampled phase comparator embodiments advantageously operate on the median of data edge positions. Representations of these values and other values used for the data recovery operation can be either digital or analogue or combinations thereof. Loop filtering and the other signal processing operations can be implemented in the analogue or digital domain.

For the abovementioned embodiments of the invention to have necessary information available regarding lead-jitter and lag-jitter finding a representation of the extreme jitter, i.e. extreme early and extreme late, respectively is an issue. Additionally advantageously updates should be obtained frequently enough.

To get this extreme jitter information, for example the first transition after maximum equal symbols can be used as the only criterion for a late sample and a second transition immediately after maximum equal symbols as the only criterion for an early sample. To obtain more frequent updates however, it would be in general advantageously to use e.g. the first transition after any of - for example - the three longest sequences of equal symbols as the criterion for a late sample, and any transition at the end of a - for example - 10 or 01 symbol sequence as the criterion for an early sample.

Since characteristic patterns, which need to be detected to get the phase lag value and the phase lead value, respectively, may be not always reliably available, preferably the data recovery circuit according to the present invention may comprise storing means for storing information depending on the phase lag value and the phase lead value . Depending on the kind of such information (analogue or digital value) such storing means can be realized by storing capacitors (analogue) or by digital memory means like semiconductor memory. The stored information derived from phase lag and phase lead values can be the value itself or a further processed value. Preferably, both the phase lag value and the phase lead value or related information are stored. An alternative solution is to store information regarding one of those values and the difference between the values. Other alternative solutions are storing the difference between a reference clock signal (for example, the tracking clock signal) and one (or both) of the phase lag and phase lead values. Additionally, if necessary, the difference between both values can be stored.

In a further preferred embodiment of a data recovery circuit according to the present invention the phase tracking circuit is a delay locked loop circuit having a reference clock signal circuit for providing a reference clock signal with a frequency corresponding to the data rate of the digital data signal. This delay locked loop circuit further has a signal delay circuit with controllable delay, for generating the tracking clock signal by receiving and delaying the reference clock signal in accordance with a delay control signal, a tracking phase detector coupled to receive the digital data signal and the tracking clock signal, and a loop filter. This loop filter has an input coupled to receive an output from the tracking phase detector, and an output which is coupled to provide the delay control signal for the signal delay circuit, and it has low pass filter characteristics and determines the tracking frequency limit.

The phase jitter analysing circuit of an advantageous data recovery circuit according to one embodiment of the invention comprises a first match detection unit for detecting the occurrence of a data pattern in the incoming digital data signal matching with a first pre-selected data pattern and for outputting a first pattern matching information (for example a first pattern matching signal) , and a second match detection unit for detecting the occurrence of a data pattern in the incoming digital data signal matching with a second pre-selected data pattern, and for outputting a second pattern matching information (for example a second pattern matching signal) . Such a favourable phase jitter analysing circuit is adapted for detecting in response to the first pattern matching information, a phase difference amount between an edge in the digital data signal and a corresponding edge in the tracking clock signal and outputting a signal indicative of the phase lag value, and for detecting in response to the second pattern matching information, a phase difference amount between an edge in the digital data signal and a corresponding edge in the tracking clock signal and outputting a signal indicative of the phase lead value.

Preferably such phase jitter analysing circuit may comprise a first delay locked loop and a second delay locked loop, each of the first and second delay locked loops comprising a controlled signal delay circuit coupled to receive and delay the tracking clock signal in accordance with a delay control signal, a phase detector and a loop filter circuit coupled to provide the delay control signal to the controlled signal delay circuit. Here the first phase locked loop is adapted to perform phase tracking when enabled by the first pattern matching information, and the second phase locked loop is adapted to perform phase tracking when enabled by the second pattern matching information. The delay control signal of both the first and second phase locked loops, respectively, is indicative of the phase lag amount and the phase lead amount, respectively.

According to an alternative embodiment of the present invention the phase jitter analysing circuit of a data recovery circuit comprises a first delay locked loop circuit and a second delay locked loop circuit, each of which comprising a controlled signal delay circuit coupled to receive and delay the reference clock signal in accordance with a respective delay control signal, a phase detector and a loop filter circuit coupled to provide the delay control signal to the controlled signal delay circuit. The output of such loop filter circuit is coupled with the output of such phase tracking circuit loop filter to generate the delay control signal with reference to the delay control signal generated by the phase tracking circuit loop filter. The first delay locked loop in such embodiments is adapted to perform phase tracking when enabled by the first pattern matching information, and the second delay locked loop is adapted to perform phase tracking when enabled by the second pattern matching information.

In analogue loop filter circuits of each of the phase jitter analysing circuits of such data recovery circuits preferably there may be a charge pump circuit.

In a preferred embodiment of a data recovery circuit with analogue delay locked loop circuits at least one of the delay locked loop circuits of the phase jitter analysing circuit may comprise a capacitive charge storage element having one terminal coupled with the output of loop filter circuit of this at least one delay locked loop circuit, and having another terminal coupled with the output of the loop filter of the phase tracking circuit. Such storage element may perform storage of the (positive or negative) time difference between the phase of the tracking clock and the high frequency jitter dependent component delivered by that phase jitter analysing circuit. Additionally such storage element may provide one possible solution of superposing the tracking clock information and the output of the phase jitter analysing circuit for creating a sampling clock signal.

In one embodiment of such a data recovery circuit the output of the loop filter circuit of the first delay locked loop of the phase jitter analysing circuit and the output of the loop filter circuit of the second delay locked loop of the phase jitter analysing circuit may be coupled by a capacitive charge storage element. Herewith storing an analogue value representing the difference between early jitter and late jitter is easily accomplished.

If the phase tracking circuit is an analogue circuit as mentioned above, preferably the output of its loop filter circuit may be coupled to a capacitive charge storage element. In a data recovery circuit according to a further embodiment of the present invention the sampling clock generating circuit preferably may comprise a controllable signal delay circuit coupled to receive the reference clock signal and may output the sampling clock signal based on phase delay of the reference clock signal.

In an other embodiment of a clock recovery circuit according to the present invention the phase tracking circuit may be a phase locked loop circuit and may have a controlled oscillator circuit for generating the tracking clock signal with a frequency controlled by a frequency control signal, a tracking phase detector coupled to receive the digital data signal and the tracking clock signal, and a loop filter. This loop filter then has an input coupled to receive an output from the tracking phase detector, and an output which is coupled to provide the frequency control signal for the controlled oscillator circuit. Such loop filter has low pass filter characteristics and determines the tracking frequency limit.

Still another embodiment of a data recovery circuit according to the present invention may have an alternative phase j itter analysing circuit, which comprises a jitter phase detector for detecting a phase difference between an edge occurring in the digital data signal and an associated edge occurring in the tracking clock signal, and outputting a signal indicative of the detected phase difference, a circuit for maintaining an estimate of a first extreme level of the jitter phase detector output signal, in order to generate a signal indicative of the phase lead value, and a circuit for maintaining an estimate of a second extreme level opposite to the first extreme level, of the jitter phase detector output signal, in order to generate a signal indicative of the phase lag value. Both of said extreme level jitter peak detectors equipped with a roll-off function gradually reducing the lead or lag peak estimate offset from the tracking clock such that extreme values occurring because of a one-time-only or very infrequent upset are reduced to a peak value occurring with a repetition rate at least equal to some predetermined rate.

Such kind of phase jitter analysing circuit may comprise first and second controllable delay circuits and first and second phase comparator circuits, whereby in some specific cases the first controllable delay circuit may be coupled to delay the tracking clock signal, and the second controllable delay circuit may be coupled to delay the tracking clock signal or the digital data signal.

In some embodiments of the present invention preferably the phase tracking circuit may be adapted to adjust the phase of the tracking clock signal based on the median of phase variations in the digital data signal relative to the tracking clock signal.

According to one possible alternative to the latter embodiments the phase tracking circuit can also be adapted to adjust the phase of the tracking clock signal based on an average of the phase variations in the digital data signal relative to the tracking clock signal.

In one preferred group of embodiments of data recovery circuit according to the present invention the sampling clock generating circuit is adjusting the phase of the sampling clock signal based on a weighted sum of the phase lag value and the phase lead value.

In a further embodiment of a data recovery circuit according to the present invention the sampling clock generating circuit may comprise a controllable signal delay circuit coupled to receive the tracking clock signal and output the sampling clock signal based on phase delay of the tracking clock signal.

In still a further embodiment of a data recovery circuit according to the present invention the phase offset of the sampling clock signal from the tracking clock signal is adjustable in accordance with the phase lag value and the phase lead value only.

One advantageous embodiment of the present invention is a data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising: a pattern acknowledging means for acknowledging the data pattern of successively recovered digital data from the digital data signal; a pattern comparator means for comparing acknowledged data pattern against pre-stored data pattern; a phase tracking / phase jitter analysing unit for generating based on a first parameter set a tracking clock signal which tracks phase variations in the data rate of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components reaching up to a tracking frequency limit; and/or for generating based on a second parameter set a phase lag value or a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, the phase variations tracked by said phase tracking circuit having frequency components reaching up to a jitter frequency limit, higher than the tracking frequency limit; a sampling clock generating circuit for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and with a phase offset from the tracking clock signal which is adjustable in accordance with said phase lag value or said phase lead value; and a data sampling circuit coupled to receive said digital data signal from said transmission medium, for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal, wherein the parameter set used in the phase tracking / phase jitter analysing unit is depending on the comparison result of the pattern comparator means . A further advantagous embodiment of the present invention is a data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising a pattern acknowledging means for acknowledging the data pattern of successively recovered digital data from the digital data signal; a pattern comparator means for comparing acknowledged data pattern against pre-stored data pattern; a phase tracking / phase jitter analysing unit for generating based on a first parameter set a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking / phase jitter analysing unit with said first parameter set having frequency components reaching up to a tracking frequency limit; for generating based on a second parameter set a phase lag value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, wherein the phase variations analysed by said phase tracking / phase jitter analysing unit to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidth; and for generating based on a third parameter set a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, wherein the phase variations analysed by said phase tracking / phase jitter analysing unit to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidth; a sampling clock generating circuit for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and with a phase offset from the tracking clock signal which is adjustable in accordance with said phase lag value or said phase lead value; and a data sampling circuit coupled to receive said digital data signal from said transmission medium, for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal, wherein the parameter set used in the phase tracking / phase jitter analysing unit is depending on the comparison result of the pattern comparator means.

In a particular embodiment of a data recovery circuit according to one of the two latter embodiments a weighting of said tracking clock signal phase and said phase offset for generating a sampling clock signal of said sampling clock generating circuit is depending on the comparison result of the pattern comparator means .

A specific embodiment of a data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium according to the present invention, comprises means for generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal in a first operating condition, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit; means for generating an extreme pattern tracking signal which tracks phase variations in the data clock of said digital data signal relative to the phase of the tracking clock signal in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data symbols, wherein the phase variations, which may be analysed to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidth; means for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and for the second operating condition adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said extreme pattern tracking clock phase offset ; and means for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal .

A further specific embodiment of a data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium according to the present invention, comprises means for generating a tracking clock signal which tracks phase variations in the data rate of said digital data signal in a first operating condition, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit; means for generating an extreme pattern tracking clock signal which tracks phase variations of said digital data signal in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data symbols, wherein the phase variations analysed to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the itter tracking bandwidth; means for generating a sampling clock signal with a phase related to the phase of said tracking clock signal for the first operating condition, and generating a sampling clock signal with a phase related to the phase of said extreme pattern tracking clock signal for the second operating condition; and means for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

Each of this means mentioned in the latter embodiments - for example the means for generating said specific signals or for sampling digital signals - can be implemented by means of analogue or digital technique or a mixture of both as described above and as will be described in more detail hereafter.

According to an other aspect of the present invention, a line receiver circuit is provided comprising any data recovery circuit as mentioned above.

According to a further aspect of the present invention, methods of recovering data from a digital data signal are provided, which digital data signal is received via a frequency limited transmission medium.

One preferred embodiment of such method comprising generating a tracking clock signal which tracks phase variations in the data rate of the digital data signal, the phase variations tracked by the phase tracking circuit having frequency components reaching up to a tracking frequency limit; analysing phase jitter in the digital data signal relative to the phase of the tracking clock signal, and providing a phase lag value and a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to the tracking clock signal; generating a sampling clock signal with a phase related to the phase of the tracking clock signal, and adjusting a phase offset of the sampling clock signal from the tracking clock signal based on the phase lag value and based on the phase lead value; and sampling the amplitude of the digital data signal at time instants determined by the sampling clock signal .

An other preferred embodiment of such method comprising acknowledging the data pattern of successively recovered digital data from the digital data signal; comparing said acknowledged data pattern against pre-stored data pattern being associated with high probability to jitter having a jitter frequency higher than a first frequency limit; generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components approximately reaching up to said first frequency limit; depending on the comparison result of the pattern comparing, generating a phase shift value relative to said tracking clock signal, wherein the phase variations analysed to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidth; generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said phase shift value; and sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

A further preferred embodiment of such method of recovering data from a digital data signal received via a frequency limited transmission medium, comprising in a first operating condition generating a tracking clock signal which tracks phase variations of said digital data signal, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit; in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, generating an extreme pattern tracking signal which tracks phase variations of said digital data signal relative to the phase of the tracking clock signal, wherein the phase variations analysed to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidth; generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and for the second operating condition adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said extreme pattern tracking clock phase offset; and sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

Still an other preferred embodiment of such method of recovering data from a digital data signal received via a frequency limited transmission medium, comprising in a first operating condition generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit; in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, generating an extreme pattern tracking clock signal which tracks phase variations in the data clock of said digital data signal, wherein the phase variations analysed to obtain said extreme pattern characteristic signal may have frequency components ranging from the tracking frequency limit to the bit rate frequency, while said extreme pattern characteristic signal has an upper frequency limit that is typically much lower than the jitter tracking bandwidt ; generating a sampling clock signal with a phase related to the phase of said tracking clock signal for the first operating condition, and generating a sampling clock signal with a phase related to the phase of said extreme pattern tracking clock signal for the second operating condition; and sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

Preferably an embodiment of such method of recovering data according to the invention comprises comparing the sampled amplitude against a decision threshold; and outputting the comparison result and the tracking clock signal. However, as one of several possible alternatives of this particular embodiment the output can also be this comparison result and the sampling clock signal or any other suitable clock signal.

Next some preferred embodiments of the present invention will be described more in detail . From this and the general description above it will be obvious to anyone with ordinary skills in the art how to implement variations of the present invention with less functionality and/or with alternate implementations of function blocks and signal representations as indicated in the previous general description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing schematically an example of the basic configuration of the data recovery circuit according to the present invention;

FIG. 2 shows in a schematic block diagram the first example of the practical configuration of a data recovery circuit using an DLL circuit for obtaining a tracking clock signal;

FIG. 3 shows in a schematic block diagram a second example of the practical configuration of a data recovery circuit using an DLL circuit for obtaining a tracking clock signal similar to the first example; FIG. 4 shows in a schematic block diagram a third example of the practical configuration of a data recovery circuit using an PLL circuit for obtaining a tracking clock signal; and

FIG. 5 is a block diagram schematically showing an basic embodiment example of the data recovery circuit according to the present invention from an other general point of view useful for analogue implementations, digital implementations or mixed analogue/digital implementations.

DESCRIPTION OF THE PREFERRED EMBODIMENT EXAMPLES

Since all figures are schematic block diagrams, hereafter lines, nodes and signals on this lines or nodes are referenced with the same respective reference. Similar function blocks and similar signal lines have the same references in all figures when appropriate.

FIG. 1 is a block diagram showing schematically an example of the basic configuration of the data recovery circuit according to the present invention.

Fig. 1 shows a data recovery circuit 1 for recovering data from a digital data signal A. A phase tracking circuit 2 for generating a tracking clock signal 3 tracks phase variations having frequency components reaching up to a tracking frequency limit in the data clock of said digital data signal A.

A phase jitter analysing circuit 4 is provided for analysing phase jitter in the digital data signal A relative to the phase of the tracking clock signal, and outputting a phase lag value 6 and a phase lead value 5. The phase lag value 6 and the phase lead value 5 are indicative of a phase range of jitter occurring in the digital data signal A relative to the tracking clock signal 3, respectively. A sampling clock generating circuit 7 for generating a sampling clock signal 8 with a phase related to the phase of the tracking clock signal 3, and with a phase offset from the tracking clock signal which is adjustable in accordance with the phase lag value 6 and the phase lead value 5 is coupled to the phase jitter analyser 4 and directly or indirectly with the phase tracking circuit 2.

A data sampling circuit 9 is coupled to receive the digital data signal A from said transmission medium, for sampling the amplitude of said digital data signal A at instants in time determined by said sampling clock signal 8 and delivering a sampled data signal B.

It has to be stated that connecting lines as shown in Fig. 1 indicate case by case signal flow and/or information flow. In all cases, but particularly in case of information flow there can be additional function blocks between shown function blocks .

FIG. 2 shows in a schematic block diagram as an example a first embodiment example of a data recovery circuit using a

DLL circuit with a linear phase comparator and analog signal processing.

For clarity and ease of description, dedicated instantiations (i.e. function blocks) are shown also for functions that can time-share the same element.

Generally, as already shown in Fig.l, Fig. 2 shows a data recovery circuit 1 for recovering data from a digital data signal A comprising a phase tracking circuit 2 for generating a tracking clock signal 3, a phase jitter analysing circuit 4 for outputting a phase lag value 6 and a phase lead value 5 , a sampling clock generating circuit 7 for generating a sampling clock signal 8, and a data sampling circuit 9 for sampling the amplitude of said digital data signal A and delivering a sampled data signal B. The data recovery circuit 1 has two inputs, the data stream A to be recovered and a reference clock signal 11, delivered by an internal (as shown) or external reference clock circuit 10.

The phase tracking circuit 2 of Fig. 2 is a delay locked loop (DLL) comprising a linear phase comparator 23 as phase detector for comparing the digital data A with the tracking clock signal 3. This tracking clock signal 3 is the output of a controlled delay element 25, which is shifting the phase of the reference clock in accordance with a control signal 13. This control signal 13 is the result of a low-pass filtering procedure filtering the output of the phase comparator 23. As loop filter having low-pass characteristics in the embodiment example of Fig. 2 a charge pump 24 with a capacitor 35 between its output 13 and Ground is provided.

The phase jitter analysing circuit 4 of Fig. 2 includes for each extreme jitter of higher frequencies (pattern dependent itter), i.e. early (lead) and late (lag) jitter, a delay locked loop (DLL) 22 and 21, each comprising a linear phase comparator 26 and 31 as phase detector, respectively. The phase comparator 26 is comparing the digital data A with the output 15 of a controlled delay element 28 of the DLL 22, which is shifting the phase of the reference clock in accordance with a control signal 5. This control signal 5 is the result of a low-pass filtering procedure filtering the output of the phase comparator 26. As loop filter having low- pass characteristics in the embodiment example of Fig. 2 a charge pump 27 with a capacitor network 41, 35 (and 40,42) between its output 5 and Ground is provided. The phase comparator 32 is comparing the digital data A with the output 36 of a controlled delay element 33 of the DLL 21, which is shifting the phase of the reference clock 11 in accordance with a control signal 6. This control signal 6 is the result of a low-pass filtering procedure filtering the output of the phase comparator 32. As loop filter having low-pass characteristics in the embodiment example of Fig. 2 a charge pump 32 with a capacitor network 42, 35 (and 40, 41) between its output 5 and Ground is provided. That capacitor network comprises a capacitor 35 between the output 13 of charge pump 24 of the tracking clock circuit 2 and Ground, as mentioned above. That capacitor network additionally comprises a capacitor 40 as a storage capacitor between the output 6 of charge pump 32 and the output 5 of charge pump 27, a capacitor 41 between the output 5 of charge pump 27 and the output 13 of charge pump 24 of the tracking clock circuit 2, and a capacitor 42 between the output 6 of charge pump 32 and the output 13 of charge pump 24 of the tracking clock circuit 2.

To fulfill the functionality of a first and second match detection unit for detecting the occurrence of a data pattern in the incoming digital data signal matching with a first and second pre-selected data pattern, and for outputting a first and second pattern matching information, a pattern detector 16 is shown. This pattern detector 16 is outputting an enable signal ENLEAD on a line 20 for enabling the phase comparator 26 in case the pattern detector 16 is detecting a preselected first pattern usually leading to an early data edge. Furthermore this pattern detector 16 is outputting an enable signal ENLAG on a line 19 for enabling the phase comparator 32 in case the pattern detector 16 is detecting a preselected second pattern usually leading to a late data edge.

Therefore DLL 22 will only create a control signal at the output 5 of charge pump 27 for detected lead jitter and DLL 21 will only create a control signal at the output 6 of charge pump 32 for detected lag jitter.

The output 5 of charge pump 27 and the output 6 of charge pump 32 both are coupled to an average circuit 37, which is part of the sampling clock generating circuit 7 together with a controlled delay element 38. The average circuit 37 is providing an average value of the signals 5 and 6 to this controlled delay element 38 of sampling clock generating circuit 7, which is generating the sampling clock signal 8 based on the tracking clock phase and the information of control signals 5 and 6.

In the embodiment example of Fig. 2 the phase information of the tracking clock 3 is by capacitive coupling via capacitors 41 and 42 respectively superposed to the phase information of the DLL 22 at output 5 and the phase information of the DLL 21 at output 6, respectively. Therefore at the output 12 of the average circuit 37 the phase information 13 of the tracking clock circuit 2 and the phase information 5 and 6 of the phase jitter analysing circuit 4 are provided to control the delay element 38 of sampling clock generating circuit 7. Thus the controlled delay element 38 of sampling clock generating circuit 7 is in the embodiment example of Figure 2 largely deriving its static offset from lead and lag signals 5 and 6, and its dynamic properties from tracking clock 3 while synthesizing the sampling clock 8 from the reference clock signal 11.

The phase comparators 23, 26 and 31, respectively, generate up and down pulses with a net duration proportional to the phase difference between clock and data. The phase comparator

23 and charge pump 24 of the phase tracking circuit 2 operate on all data transitions integrating phase difference pulses on the loop filter, which in case of a DLL is a simple capacitor 35, 42 and 41 respectively.

The resulting control voltage 13 outputted by the charge pump

24 of the phase tracking circuit 2 controls the phase of tracking clock 3, outputted by the delay element 25 of the phase tracking circuit 2. This tracking clock 3 tracks all jitter components of the input data signal that has a frequency lower than the loop filter cut off frequency of the phase tracking circuit 2. The phase of the tracking clock 3 is a weighted average of jitter components with higher frequencies. Because the adjustment of this tracking clock 3 operates on all edges, it has a high bandwidth. Charge pumps 32 and 27 of the phase jitter analyser 4 maintain estimates of the high frequency jitter component peak level offsets from the weighted low frequency average as represented by control voltage at the output 13 of charge pump 24 of the tracking clock circuit 2.

In the analog signal processing block built with capacitors 40, 41 and 42, shown in Figure 2 the jitter peak estimate voltages at the output 6 of charge pump 32 and at the output 5 of charge pump 27 track the voltage at the output 13 of charge pump 24 of the tracking clock circuit 2 by having the capacitors 41 and 42 referenced to that output 13. When the voltage at the output 13 of charge pump 24 of the tracking clock circuit 2 is adjusted to track any -low frequency jitter components, the output 5 of charge pump 27 of the DLL 22 for early pattern and the output 6 of charge pump 32 of the DLL 21 for late pattern get advantageously the same adjustments.

The high frequency jitter peak offset estimates can be calculated in several ways. Inter-symbol interference is an important component of the high frequency jitter that has an non-symmetric distribution and pattern dependent exposure. Other high frequency jitter components such as random jitter and bounded non-correlated jitter have more symmetric distributions and often lower amplitude. Therefore the high frequency j itter peak calculations can be based on data pattern correlation.

In such an embodiment example of the present invention (as shown in Fig. 2) phase comparators 26, 31 and charge pumps 27 and 32 are activated upon particular bit patterns of data only by enabling information/signals ENLEAD 20 and ENLAG 19 respectively. For example charge pump 32 maintains an estimate of the peak early high frequency jitter offset from the weighted average value at the output 13 of charge pump 24 of the tracking clock circuit 2 by being activated on data transitions following single equal symbol sequences only, while charge, pump 32 maintains an estimate of the peak late high frequency jitter offset by being active on data transitions following sequences of m or more equal symbols. The number m should be chosen with some connection to the line code used or lack thereof.

This means peak value updates may not be done simultaneously for the lead and lag estimate signals 5 and 6. Therefore, in an analog capacitor implementation 35, 40, 41 and 42 such as the one shown in figure 2 the peak-to-peak high frequency jitter amplitude estimate maintained by the capacitor 40 connected between the output 5 of charge pump 27 of the DLL 22 for early pattern and the output 6 of charge pump 32 of the DLL 21 for late pattern would never be updated. This voltage can be controlled by storing and delaying the charge pulses from charge pump 32 one cycle before being connected to the capacitor network 40, 41, 42. In that way the peak-to- peak high frequency jitter estimate will be set by bit sequences where several equal symbols are followed by a single symbol surrounded by opposite symbols.

For implementations where the pattern detection information is not available until after the corresponding phase comparison operation must be performed, the charge pumps may be equipped with elements for temporary storage, such that the phase comparator and charge pump could operate on all data edges and the output charge packets held until the decision on whether to discard or transfer the charge packet to the loop filter could be taken based on qualifying pattern detection.

If pattern independent size of the charge packets is used, the time constant for adjustments of high frequency jitter peak estimate voltages varies with pattern density. For optimum performance, the time constant occurring when one of the charge pumps 27 or 32 is activated frequently may be chosen to equal the time constant for the weighted average voltage at the output 13 of charge pump 24 of the tracking clock circuit 2. Then, the peak value voltage can be maintained without being pushed away while being approached by the voltage at the output 13 of charge pump 24 of the tracking clock circuit 2 as a result of its drift towards the peak level when subjected to a low jitter exposing data pattern.

The peak-to-peak jitter exposure time constant can be much longer. That time constant is determined by the capacitor 40 connected from output 5 of charge pump 27 of DLL 22 for early pattern to output 6 of charge pump 32 of DLL 21 for late pattern and the charge packets from charge pumps 27 and 32. The average of control voltages at output 5 of charge pump 27 and at output 6 of charge pump 32 is computed and used for entering the data sampling strobe point in the middle of the eye opening by the halfway between jitter peak values.

The requirements on phase relations between the input data signal A and the reference clock 11 depend on the properties of the delay elements 25, 28 and 33 used. If finite range delay lines are used, the maximum peak-to-peak relative jitter between reference clock and input data preferably should be less than the adjustment range of the dela lines. If phase rotator wrap around delay adjustment elements are used, the relationship can be unlimited jitter isochronous or plesiochronous .

FIG. 3 shows in a schematic block diagram as an example a second embodiment example of a data recovery circuit using a DLL circuit with a linear phase comparator and analog signal processing. In fact, the second embodiment example of Fig. 3 comprises the same elements as the first embodiment example shown in Fig. 2. The main difference between the first and second embodiment example is in the coupling of the phase information tracking clock 3 to the jitter analysing circuit 4 and the sampling clock generating circuit 7.

In the second embodiment example of Fig. 3 there is no capacitive coupling between the output 13 of the charge pump 24 and the jitter analysing circuit 4. Therefore the loop filter of DLL 22 in the embodiment example of Fig. 3 is the charge pump 27 with a capacitor 29 between its output 5 and Ground, and the loop filter of DLL 21 is the charge pump 32 with a capacitor 34 between its output 6 and Ground. Additionally, instead of superposing the delay element control signal 13 of the tracking clock circuit 2 to the delay element control signal of the DLL 21 and the DLL 22 respectively, controlling the delay from the reference clock 11 each, in the embodiment example of Fig. 3 the input clock signal to the DLL 21 and DLL 22 is the tracking clock signal 3.

Furthermore, since in the embodiment example of Fig. 3 the phase information of the tracking clock 3 is not included in the phase information of the DLL 22 at output 5 and the phase information of the DLL 21 at output 6, respectively, at the output 12 of the average circuit 37 only the phase information 5 and 6 of the phase jitter analysing circuit 4 is provided to control the delay element 38 of sampling clock generating circuit 7. Thus the controlled delay element 38 of sampling clock generating circuit 7 in the embodiment example of Figure 3 has the tracking clock signal 3 instead of the reference clock signal 11 as shown in Fig. 2 as input clock signal.

Apart from these differences, the second embodiment example is identical to the first embodiment example of the invention and the description relating to the first embodiment example according to Fig. 2 is applicable to the second embodiment example shown in Fig. 3. Now, reference is made to Fig. 4, which shows in a schematic block diagram a third example of the practical configuration of a data recovery circuit using an oscillator based PLL circuit for obtaining a tracking clock signal (instead of the DLL circuit as used in the first and second embodiment example) .

In fact, the third embodiment example shown in Fig. 4 is exactly the same as the second embodiment example shown in Fig. 3 except for the phase tracking circuit 2.

The phase tracking circuit 2 of the third embodiment example of a data recovery circuit 1 according to the present invention is a PLL comprising a linear phase comparator 23 as phase detector for comparing timing of the digital data A with the tracking clock signal 3. This tracking clock signal 3 is the output of a controlled oscillator 25 (VCO) controlled by a control signal 39. This control signal 39 is the result of a low-pass filtering procedure filtering the output of the phase comparator 23 using a loop filter 24 having low-pass characteristics.

Apart from this difference, the embodiment example is identical with the second embodiment example of the invention and the description relating to the second embodiment example according to Fig. 3 is applicable to the third embodiment example shown in Fig. 4.

The first, second and third embodiment examples shown in Fig. 2, 3 and 4 all are data recovery circuits using DLL and PLL circuits with linear phase comparators and analog signal processing. This have been useful simple types for explaining implementations to ease understanding the principles of the present invention. However, the present invention is not limited on such constructions but there are many of the possible embodiment examples within the spirit and scope as defined by the attached claims. To explain some of this variety of possible embodiment examples of the present invention the block diagram of FIG. 5 schematically shows a basic example of the data recovery circuit according to the present invention from an other general point of view useful for analogue implementations, digital implementations or mixed analogue/digital implementations .

Since in the block diagram of Fig. 5 dedicated instantiations (i.e. function blocks) are not always shown for functions that can time-share the same element, function blocks of Fig. 5 generally reference numbers that are different from those of function blocks in Fig. 1 to 4.

Fig. 5 shows a data recovery circuit 1 for recovering data from a digital data signal. A and providing such recovered data B. As in the first second and third embodiment example, the data recovery circuit 1 shown in Fig. 5 has two inputs, the data stream A to be recovered and a reference clock signal 11, delivered by an internal (as shown) or external reference clock circuit 10. In case, an oscillator based PLL function is implemented for obtaining the tracking clock information, the reference clock generator 10 will be part of that PLL and the reference clock signal 11 will be the tracking clock signal 3.

The data recovery circuit 1 of Fig. 5 comprises a cross coupled multi-loop filter circuit 104 for four inputs D, E, L and M and four outputs Dctrl, Ectrl, Lctrl and Mctrl. Here M and Mctrl stand for values or data representing the mean tracking phase as a particular tracking clock, E and Ectrl stand for values or data representing the early pattern dependent phase (i.e. the lead jitter component), and L and Lctrl stand for values or data representing the late pattern dependent phase (i.e. the lag jitter component) .

Inputs E, L and M are provided by timing analysers 100, 101 and 102 respectively. Three such control signals provide fairly rich information for strobe signal synthesis, but the data recovery circuit according to the present invention will work with a different number of inputs and timing analysers wherein at least input E and L are necessary. Depending on implementation preferences, the control signals E, L, and M can be generated from separate timing analysers or from a more complex timing analyser with multiple outputs.

The timing analysers 100, 101 and 102 can be implemented as two types of timing analysers, sampled types (median equilibrium in closed loop) and proportional types (mean equilibrium in closed loop) . Sampled type timing analysers can be for example Flip-flops or Sample and hold circuits. Proportional type timing analysers can be for example Hogge detectors or other phase detectors or phase comparators .

The Input D is provided by a data sampler 103, which can be a Flip-flop, a sample and hold circuit or the like. For best performance, preferably the same kind of circuitry should be used in the peak channel timing analysers 101 and 102 and the data sampler 103. The input data D is actually the recovered data B which is the output of the data recovering circuit 1. This data D enable the cross coupled multi-loop filter circuit 104 to know about the pattern of input digital data signal A of the data recovering circuit 1 and to enable control information Ectrl in case of an extremely early jitter producing pattern and to enable control information Lctrl in case of a late jitter producing pattern for example. The multi-loop filter circuit 104 also takes control information Ectrl and control information Lctrl in account by weighting the mean to create a control information Dctrl to create a sampling clock information 8.

The four control information outputs Dctrl, Ectrl, Lctrl and Mctrl each are provided to a clock synthesizer 108, 107, 106 and 105 respectively. As shown in Fig. 5, the clock synthesizer 105 is controlled by control information Mctrl to shift the phase of the reference clock signal 11 and provide the tracking clock signal 3, which is coupled back to one input of the timing analyzer 100 to build a mean loop. The other input of the timing analyzer 100 is the inputted digital data signal A as it is also for timing analyzers 101 and 102 as well as for the data sampler 103.

The clock synthesizer 106 is controlled by control information Lctrl to shift the phase of the reference clock signal 11 according to the additional phase shift to the mean according to the phase difference of an extremely late pattern depending jitter and provide this phase shifted reference clock signal 36 to one input of the timing analyzer

101 to build a late loop.

The clock synthesizer 107 is controlled by control information Ectrl to shift the phase of the reference clock signal 11 according to the additional phase shift to the mean according to the phase difference of an extremely early pattern depending jitter and provide this phase shifted reference clock signal 15 to one input of the timing analyzer

102 to build an early loop.

The clock synthesizer 108 is controlled by control information Dctrl to shift the phase of the reference clock signal 11 according to the phase shift of the mean and pattern dependent according to the phase difference of an extremely early and/or late pattern depending jitter and provide this phase shifted reference clock signal 8 as the sampling clock signal to the data sampler 103 to sample the digital data signal A and to provide a recovered data signal B.

For sampled timing analysers 100, 101, 102 the cross coupled multi-channel loop filter 104 at its front end side is operating as a phase relation deduction machine operating on multiple samples of the input data. A very natural choice is to use the output data E, L, and M from the timing analysers 100, 101, 102. That is the reason for showing three timing analysers in Fig. 5 since it allows to take in account additionally to the mean value (with low frequency jitter only) the phase difference of extremely early and extremely late pattern dependant jitter (of higher frequencies) . Practically timing analysers 100, 101, 102 can be the same physical unit, used for different purpose with the cross coupled multi-channel loop filter 104 having different characteristic .

One important distinction of such implementation to data recovering circuits according to the state of the art is that a data recovering circuit according to this invention operates with variable offsets between the sampling points. Preferably this offsets are individually phase locked. In the embodiment of Figure 5 shown as an example there are three sampled timing analysers 100, 101, 102 extracting phase information and the sampling instants of the fourth data sampler 103 are computed from these three phase samplers. In this example the pattern dependent decimation of sample data from the peak estimate samplers 101 and 102 leading to the desired phase lock equilibria offsets from the mean.

The outputs from this cross coupled multi-loop filter circuit 104, i.e. the control information outputs Dctrl, Ectrl, Lctrl and Mctrl are then formatted to fit the type of loop filters used. In case of analog loop filters with integration as voltage on capacitors the outputs are unit charge packets; and the outputs are digital up down signals for a digital loop filter with DSP integration, which would be an up/down counter in its simplest form. For proportional timing analyzers the pattern qualifier machine only needs to dump disqualified charge packets. The output signal is already in suitable form for an analog loop filter. Here the cross coupled multi-channel loop filter 104 acts as a variable charge transfer circuitry with an operation that for each processed data edge results in a net charge transfer that is proportional to the clock to data edge timing relation. When one or more of the mean, early and late loops are lacking adjustment information, bandwidth boost may be optionally provided by qualified ganged adjustments in the three loops. This will be described below more in detail.

A digital implementation of the Cross coupled multi-channel loop filter may be simple DSP machines, with bandwidth boosting ganging (or cross coupling) happening already while processing the input signals to the loop filters. That partitioning can be changed, such that the ganging/cross coupling is depicted as multiple inputs to the loop filters with pattern qualification on the multi input processing, thus becoming more similar to the analog partitioning that reflects a fairly simple structure due to the ability to perform weighted summing just by tying outputs together via suitable impedance elements .

Analog loop filters can be connected as shown in the Fig. 2 to 4 described above.

In this patent application, as far as there is no detailed explanation given in a particular case, the meaning of PLL shall be what "phase locked loop" says. This term is very general and could fit all kinds of feedback systems adjusting the timing of a signal in a closed loop to track another signal's phase (and such its jitter spectrum in a given frequency range) , as good as the gain of the closed loop allows. In other words, even if PLL often is commonly used with the implied restriction of applying to second order loops where the phase adjustment is accomplished by use of a frequency adjustable oscillator, the meaning should generally (if there is no distinction made relating to DLL) not be restricted to such kind of loops.

First order systems are often called delay locked loops DLL although other elements than adjustable delay circuits can be used for creating an output clock signal with adjustable phase from a set of input clock signals, e.g. phase mixers, phase rotators or phase blender.

The word "clock synthesizer" in Fig. 5 for the clock synthesizer 105, 106, 107 and 108 is used as a general term comprising for example adjustable delay circuits, phase mixers, phase rotators or phase blender. Especially for the mean loop, in case it is designed as a second order PLL, the clock synthesizer 105 together with the reference clock 10 can be a controlled oscillator also.

In case (as mentioned above for a particular embodiment of this example) timing analysers 100, 101, 102 are implemented as the same physical unit, clock synthesizer 105, 106, 107 can be also.

Analog input signal clock synthesizers can be implemented with DLLs or with a combination of oscillator based PLL and DLLs. The data strobe (sampling clock) 8 is in this embodiment example not synthesized in a closed loop. It is created from the early and late clocks in a replica DLL 103, 104, 108 equal to those of the "E" and "L" clocks 15, 36. Depending on the type of timing analyzer 102, 101 used, these clocks 15, 36 have one of their edge types aligned to either data transitions or such that the qualified data transitions fall half way between its aligned edges. In either case, the control signal Dctrl for the D clock 8 is created as a weighted sum of the Ectrl and Lctrl signals (e.g. 0.4Ectrl + O.δLctrl) plus an added 0 or 180-degree offset. With analog control clock synthesizers 105, 106, 107 this can be done by using the opposite edge type for data strobing 8. With differential logic circuits this can be simple. Single ended logic circuits always require careful attention in precision open loop replica systems. The reference clock signal 11 preferably should in this case be duty cycle corrected if it isn't already well controlled. Digitally controlled clock synthesizers can for example use the same method or have the conditional 180-degree offset added to its input vector. The tracking clock signal 3 of the mean (M) clock synthesizer 105 can be generated with a DLL 100, 104, 105 or a PLL 100, 104, 10, 105. In the latter case the reference clock signal 11 to the "E" and "L" DLLs 102, 104, 107; 101, 104, 106 is different from the drawing in Fig. 5 the M clock 3. Then, the ganged control from M to E and L is inherent by virtue of creating the "E" and "L" clocks 15, 36 by delay adjustment of the M clock 3. Preferably no qualified ganging from the M to E and L control signals should take place. The number of sample clocks doesn't have to be three. The minimum is two. The locked loops E and L are required for synthesis of the D strobe clock (8) . The E and L clocks track jitter components up to the full tracking bandwidth while maintaining a peak- to-peak jitter estimate that has an independent bandwidth. This can advantageously be expressed as positive and negative offsets from a tracking clock M (3) .

Digital input signal clock synthesizers 105, 106, 107 and/or 108 respectively are used in generally the same way as the abovementioned ones. Digital input phase mixers allow seamless wrap around the unit circle. Delay lines with bounded minimum and maximum delay often require fairly complex control logic to handle wrap around.

The core of a cross coupled multi-channel loop filter 104 can be designed in several varieties to fit the demands of the application. For a good performance, the choice should be governed depending on the type of line code used for the transmission. A main design parameter is the data pattern history length considered. The maximum phase drift of input data A relative to the reference clock signal 11; 3 used and in relation to the pattern density is also important for the choice of construction. For maximum phase drift handling, ganging of the loops 100, 104, 105, 3; 101, 104, 106, 36; 102, 104, 107, 15 should be tight, i.e. the phase relation of a data edge to the clock for which the edge is qualified by the pattern condition updates the other clock also. All clocks 3, 15, 36 can not be ganged at all times because that would not allow adapting to the line code plus transmission line jitter spectrum. The loops 100, 104, 105, 3; 101, 104, 106, 36; 102, 104, 107, 15 would be pushing each other back and forth. In an analog implementation with capacitive ganging this can be done by simultaneous updates on the ganged control lines. A simple and efficient means of accomplishing this is to delay the charge pump for the "Late" control line by one cycle at all times. This will provide an update of the "peak-to-peak" jitter estimate whenever a "Late" pattern is immediately followed by an "Early" pattern. The "M" control can have a simultaneous update either by delay or by overlapping pattern condition requirement.

The pattern qualifier logic is in a preferred embodiment example according to Fig. 5 at heart of the cross-coupled multi-channel loop filter. Based on the pattern history, it selects the timing analysers 100, 101, 102 that have the best interpretation of each data transition, and what clocks 3, 36, 15 that timing analyser(s) 100, 101, 102 should update.

The following table 1 is a truth table description of a simple triple loop qualifier with the minimum pattern length that can be used for a triple loop (plus strobe clock) system.

In table 1 D to D_Q is the pattern history. DQ is the present bit, EQ_5, MQ.5 and Lg.5 are the outputs from the E, M and L- clocked timing analyzers 102, 101, 100 that were taken sometimes during the period between data samples D^*j_ and D_Q • E_a{^-j , M_a£j and L_a(^-j are the output signals to the loop filters 104 for the E, M and L clocks. "A" means the loop filter should calculate a phase adjustment in the direction of advancing the phase of the corresponding clock. "R" means the loop filter should calculate a phase adjustment in the direction of retarding the phase of the corresponding clock. "=" means that no phase adjustment calculation should be done.

For implementations of this, several design choices have to be made, affecting power dissipation, computational complexity, the maximum operational speed in a given technology, etc. The nature of the task is basically well suited for high-speed operations. Pipe lined binary decision can be used for the decode since history data doesn't arrive as a surprise but bit by bit such that decoding can be done beforehand all the way to the second last bit, and even pre- computed on speculation if needed. The table shows one possible principle. It can be implemented in a variety of fashions. One obvious variation of the same principle is to use a common base value for all the loops and an offset register for each loop (one of which could be omitted) . The base value should then get an "A" update in all rows with an "A" and an "R" update in all rows with an "R" , and be on hold in all rows with only "=". The offset registers must then get a counter update in the rows, where "=" occurs in combination with "A" or "R" .

The rows where the ganging is not complete is where the offsets between the three E, M, and L loops 102, 104, 107, 15; 101, 104, 106, 36; 100, 104, 105, 3 are determined. These events should preferably be chosen such that an offset representative of the pattern sets served will be established. In this case adjustment bandwidth is given a high priority by tight ganging. The offset determining instants preferably will be chosen based on two criteria: A peak situation should have occurred and the loop released from the ganging should have had a recent command of an update .

Below, table 2 shows a truth table for pattern qualifier logic based on only two loops. This omission of the M-clock reduces power dissipation and complexity at the expense of more pattern related phase wander and less information available for fast frequency acquisition and/or detection of various error conditions .

Hereafter the functionality and possible design of the Data strobe (D) clock synthesis, i.e. the sampling clock generation will be described more in detail.

Putting the sampling clock generation into practice, some design problems can occur, for which a vast range of possible design solutions are available. The selection of solutions, which is generally linked to technology preferences and performance vs. cost priorities, involves decisions in areas ranging from choice of number systems and arithmetic to linearity and matching properties. All of them with the design goal of placing the data strobe point such that bit errors do not occur in spite of jitter and partially exposed jitter. A straight forward method for calculation of a control voltage for the D-clock can be illustrated using digital angular values "E", "L", "M" and "D" clocks with n discrete values per full turn and increasing values for "E", "L" and "D" with increasing phase delay: Dctrl = Ectrl Θ [Lctrl θ (-Ectrl)] / 2

where θ represents modulo n addition, and "/" integer divide

Weighting and or offset can be added in case the Ectrl and Lctrl are not equally representative of the peak pattern dependent jitter. One way of implementing that is to use a base control value Bctrl such that:

Lctrl = Bctrl θ L'ctrl and

Ectrl = Bctrl θ E ' Ctrl where E ' Ctrl is preferably chosen to be 0

The non-weighted or adjusted computation of Dctrl can then be done as :

Dctrl = Bctrl θ L'ctrl / 2

and an adjusted computation of Dctrl as:

Dctrl = Bctrl 0 C θ (A * L'ctrl) 0 < A < 1

where c is an offset term and A is a gain adjustment factor.

This form is chosen for computational simplicity. Bctrl is constantly updated to track high frequency jitter components, while L ' Ctrl gets fairly infrequent updates . The gain adjustment of the L'ctrl term can be computed serially.

Table 3 shows a truth table for pattern qualifier logic for Bctrl based calculation of the E, M, L, and D clock control values . This table shows only an example and can of course be extended or reduced to fit other numbers of strobe clocks.

If in the example of table 3 an M clock is available it can be used for some computational simplification. Analog control clock synthesizers also need the M clock for determining if the computed D clock control value must be 180 degree adjusted or not. With analog control clock synthesizers, this can be done using the opposite edge type for data strobing. As mentioned above, with differential logic this is simple. The reference clock signal 11 should in this case be duty cycle corrected if it isn't already well controlled. Digitally controlled clock synthesizers 108 have similar linearity demands for the D-clock synthesis. Phase angle dependent calibration adjustments are fairly easy to add. This can be done by calibration or choice of number system for the coordinate value pairs of the phase vector.

Claims

1. A data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising

a phase tracking circuit for generating a tracking clock signal which tracks phase variations in the data rate of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components reaching up to a tracking frequency limit;

a circuit for analysing phase jitter in the digital data signal relative to the phase of the tracking clock signal, and outputting a phase lag value and a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal,-

a sampling clock generating circuit for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and with a phase offset from the tracking clock signal which is adjustable in accordance with said phase lag value and said phase lead value; and

a data sampling circuit coupled to receive said digital data signal from said transmission medium, for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

. The data recovery circuit according to claim 1, wherein said phase tracking circuit is a delay locked loop circuit having

a reference clock signal circuit for providing a reference clock signal with a frequency corresponding to the data clock frequency of said digital data signal;

a signal delay circuit with controllable delay, for generating said tracking clock signal by receiving and delaying said reference clock signal in accordance with a delay control signal;

a tracking phase detector coupled to receive said digital data signal and said tracking clock signal;

a loop filter having an input coupled to receive an output from the tracking phase detector, and an output which is coupled to provide said delay control signal for the signal delay circuit;

wherein the loop filter has low pass filter characteristics and determines said tracking frequency limit.

3. The data recovery circuit according to claim 1 or 2 , wherein said phase jitter analysing circuit comprises

a first match detection unit for detecting the occurrence of a data pattern in the incoming digital data signal matching with a first pre-selected data pattern, and for outputting a first pattern matching information;

a second match detection unit for detecting the occurrence of a data pattern in the incoming digital data signal matching with a second pre-selected data pattern,* and for outputting a second pattern matching information; and said phase jitter analysing circuit being adapted

— for detecting in response to said first pattern matching information, a phase difference amount between an edge in said digital data signal and a corresponding edge in said tracking clock signal and outputting a signal indicative of said phase lag value, and for detecting in response to said second pattern matching information, a phase difference amount between an edge in said digital data signal and a corresponding edge in said tracking clock signal and outputting a signal indicative of said phase lead value.

4. The data recovery circuit according to claim 3, wherein said phase jitter analysing circuit comprises a first delay locked loop and a second delay locked loop, each of said first and second delay locked loops comprising

a controlled signal delay circuit coupled to receive and delay said tracking clock signal in accordance with a delay control signal, a phase detector and a loop filter circuit coupled to provide said delay control signal to said controlled signal delay circuit;

said first delay locked loop being adapted to perform phase tracking when enabled by said first pattern matching information, said second delay locked loop being adapted to perform phase tracking when enabled by said second pattern matching information;

said delay control signal of said first and second delay locked loop, respectively, being indicative of said phase lag amount and said phase lead amount, respectively.

. The data recovery circuit according to claim 3 , wherein said phase jitter analysing circuit comprises a first delay locked loop circuit and a second delay locked loop circuit;

each of said first and second delay locked loops comprising

a controlled signal delay circuit coupled to receive and delay said reference clock signal in accordance with a respective delay control signal, a phase detector and a loop filter circuit coupled to provide said delay control signal to said controlled signal delay circuit;

the output of said loop filter circuit being coupled with the output of said phase tracking circuit loop filter to generate said delay control signal with a reference to the delay control signal generated by said phase tracking circuit loop filter;

said first delay locked loop being adapted to perform phase tracking when enabled by said first pattern matching information, said second delay locked loop being adapted to perform phase tracking when enabled by said second pattern matching information.

6. The data recovery circuit according to claim 4 or 5, wherein each of said loop filter circuits of said phase jitter analysing circuit comprises a charge pump circuit.

7. The data recovery circuit according to claim 5 or 6, wherein at least one of said delay locked loop circuits of said phase jitter analysing circuit comprises a capacitive charge storage element having one terminal coupled with the output of loop filter circuit of said at least one delay locked loop circuit, and having another terminal coupled with said output of said loop filter of said phase tracking circuit.

8. The data recovery circuit according to any one of the claims 5 to 7 , wherein the output of said loop filter circuit of said first delay locked loop of said phase jitter analysing circuit and the output of said loop filter circuit of said second delay locked loop of said phase jitter analysing circuit are coupled by a capacitive charge storage element.

9. The data recovery circuit according to any one of the preceding claims, wherein said output of said loop filter circuit of said phase tracking circuit is coupled to a capacitive charge storage element.

10. The clock recovery circuit according to claim 1 or 2 , wherein said phase tracking circuit is a phase locked loop circuit having

a controlled oscillator circuit for generating said tracking clock signal with a frequency controlled by a frequency control signal;

a loop filter having an input coupled to receive an output from the tracking phase detector, and an output which is coupled to provide said frequency control signal for the controlled oscillator circuit;

11. The data recovery circuit according to claim 1, 2 or 10, wherein said phase jitter analysing circuit comprises

a jitter phase detector for detecting a phase difference between an edge occurring in said digital data signal and an associated edge occurring in said tracking clock signal, and outputting a signal indicative of the detected phase difference;

a circuit for clamping a first extreme level of said jitter phase detector output signal, in order to generate a signal indicative of said phase lag value; and

a circuit for clamping a second extreme level opposite to said first extreme level, of said jitter phase detector output signal, in order to generate a signal indicative of said phase lead value.

12. The data recovery circuit according to claim 11, wherein said phase jitter analysing circuit comprises first and second controllable delay circuits and first and second phase comparator circuits;

said first controllable delay circuit being coupled to delay said tracking clock signal, said second controllable delay circuit being coupled to delay said tracking clock signal;

said first phase comparator circuit being coupled to receive said delayed tracking clock signal and said digital data signal and adapted for decreasing the delay of said first controllable delay circuit whenever an edge occurring in said digital data signal leads the associated edge in said delayed tracking clock signal;

said second phase comparator circuit being coupled to receive said tracking clock signal and said delayed digital data signal and adapted for increasing the delay of said second controllable delay circuit whenever an edge occurring in said digital data signal lags behind the associated edge in said delayed tracking clock signal.

13. The data recovery circuit according to any one of the preceding claims, wherein said phase tracking circuit is adapted to adjust the phase of said tracking clock signal based on the median of phase variations in said digital data signal relative to said tracking clock signal.

14. The data recovery circuit according to any one of the claims 1 to 12 , wherein said phase tracking circuit is adapted to adjust the phase of said tracking clock signal based on an average of the phase variations in said digital data signal relative to said tracking clock signal .

15. The data recovery circuit according to any one of the preceding claims, wherein said sampling clock generating circuit is adapted to adjust the phase of said sampling clock signal based on a weighted average of the phase lag value and the phase lead value.

16. The data recovery circuit according to any one of the preceding claims, wherein said sampling clock generating circuit comprises a controllable signal delay circuit coupled to receive said tracking clock signal and output said sampling clock signal based on said phase delayed tracking clock signal.

17 The data recovery circuit according to any one of the preceding claims, wherein said sampling clock generating circuit comprises a controllable signal delay circuit coupled to receive said reference clock signal and output said sampling clock signal based on said phase delayed reference clock signal.

18. The data recovery circuit according to any one of the preceding claims, wherein said phase offset of said sampling clock signal from said tracking clock signal is adjustable in accordance with said phase lag value and said phase lead value only.

19. The data recovery circuit according to claim 1, comprising storing means for storing information depending of said phase lag value and said phase lead value.

20. The data recovery circuit according to claim 1 or 2 , wherein said phase jitter analysing circuit is processing edges of said digital data signal having pre-selected pattern, wherein the output of said phase jitter analysing circuit is a charge value, and wherein said phase jitter analysing circuit comprises a variable charge transfer circuit outputting for each processed edge of said digital data signal a net charge transfer proportional to the tracking clock signal to digital data signal edge timing relation.

21. A data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising

a pattern acknowledging means for acknowledging the data pattern of successively recovered digital data from the digital data signal;

a pattern comparator means for comparing acknowledged data pattern against pre-stored data pattern

a phase tracking / phase jitter analysing unit

for generating based on a first parameter set a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components reaching up to a tracking frequency limit; and/or

for generating based on a second parameter set a phase lag value or a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, the phase variations analysed by said jitter analysing circuit having frequency components reaching up to a jitter frequency limit, higher than the tracking frequency limit;

a sampling clock generating circuit for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and with a phase offset from the tracking clock signal which is adjustable in accordance with said phase lag value or said phase lead value; and

a data sampling circuit coupled to receive said digital data signal from said transmission medium, for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal;

wherein the parameter set used in the phase tracking / phase jitter analysing unit is depending on the comparison result of the pattern comparator means.

22. A data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising

a pattern comparator means for comparing acknowledged data pattern against pre-stored data pattern;

a phase tracking / phase jitter analysing unit

for generating based on a first parameter set a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking / phase jitter analysing unit with said first parameter set having frequency components reaching up to a tracking frequency limit; for generating based on a second parameter set a phase lag value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, the phase variations tracked by said phase tracking / phase jitter analysing unit with said second parameter set having frequency components reaching up to a jitter frequency limit, higher than the tracking frequency limit; and

for generating based on a third parameter set a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal, the phase variations tracked by said phase tracking / phase jitter analysing unit with said third parameter set having frequency components reaching up to a jitter frequency limit, higher than the tracking frequency limit;

a data sampling circuit coupled to receive said digital data signal from said transmission medium, for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal,

23. A data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising means for generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal in a first operating condition, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit;

means for generating an extreme pattern tracking signal which tracks phase variations in the data clock of said digital data signal relative to the phase of the tracking clock signal in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, the phase variations tracked to obtain said extreme pattern tracking signal having frequency components reaching up to an extreme pattern tracking frequency limit higher than the tracking frequency limit;

means for generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and for the second operating condition adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said extreme pattern tracking clock phase offset; and

means for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal .

24. A data recovery circuit for recovering data from a digital data signal received via a frequency limited transmission medium, comprising

means for generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal in a first operating condition, the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit; means for generating an extreme pattern tracking clock signal which tracks phase variations in the data clock of said digital data signal in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, the phase variations tracked to obtain said extreme pattern tracking clock signal having frequency components reaching up to an extreme pattern tracking frequency limit higher than the tracking frequency limit;

means for generating a sampling clock signal with a phase related to the phase of said tracking clock signal for the first operating condition, and generating a sampling clock signal with a phase related to the phase of said extreme pattern tracking clock signal for the second operating condition; and

means for sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal.

25. A line receiver circuit comprising a data recovery circuit according to any one of the preceding claims.

26. A method of recovering data from a digital data signal

(A) received via a frequency limited transmission medium, comprising

in a first operating condition generating a tracking clock signal (3) which tracks phase variations in the data clock of said digital data signal (A) , the phase variations tracked to obtain said tracking clock signal having frequency components reaching up to a tracking frequency limit;

in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, generating an extreme pattern characteristic signal characterizing phase variations in the data rate of said digital data signal (A) relative to the phase of the tracking clock signal (3), the phase variations characteristic to obtain said extreme pattern characteristic signal comprising frequency components higher than the tracking frequency limit;

generating a sampling clock signal (8) with a phase related to the phase of said tracking clock signal, and for the second operating condition adjusting a phase offset of said sampling clock signal (8) from the tracking clock signal based on said extreme pattern characteristic clock phase offset (5; 6); and

sampling the amplitude of said digital data signal (A) at time instants determined by said sampling clock signal (8) .

27. A method of recovering data from a digital data signal

(A) received via a frequency limited transmission medium, comprising

in a second operating condition, which is true for predetermined data pattern, given by the sequence of the current input data and a predetermined number of preceding input data, generating an extreme pattern characteristic signal characterizing phase variations in the data rate of said digital data signal (A) relative to the phase of the tracking clock signal (3) , the phase variations characteristic to obtain said extreme pattern characteristic signal comprising frequency components higher than the tracking frequency limit;

generating a sampling clock signal (8) with a phase related to the phase of said tracking clock signal for the first operating condition, and generating a sampling clock signal (8) with a phase related to the phase of said extreme pattern tracking clock signal for the second operating condition; and

28. A method of recovering data from a digital data signal received via a frequency limited transmission medium, comprising

acknowledging the data pattern of successively recovered digital data from the digital data signal;

comparing said acknowledged data pattern against prestored data pattern being associated with high probability of jitter having a jitter frequency higher than a first frequency limit;

generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components approximately reaching up to said first frequency limit;

depending on the comparison result of the pattern comparing, generating a phase shift value relative to said tracking clock signal, the phase variations of this phase shift value having frequency components higher than the first frequency limit; generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said phase shift value; and

sampling the amplitude of said digital data signal at time instants determined by said sampling clock signal .

29. A method of recovering data from a digital data signal received via a frequency limited transmission medium, comprising

generating a tracking clock signal which tracks phase variations in the data clock of said digital data signal, the phase variations tracked by said phase tracking circuit having frequency components reaching up to a tracking frequency limit;

analysing phase jitter in the digital data signal relative to the phase of the tracking clock signal, and providing a phase lag value and a phase lead value indicative of a phase range of jitter occurring in the digital data signal relative to said tracking clock signal;

generating a sampling clock signal with a phase related to the phase of said tracking clock signal, and adjusting a phase offset of said sampling clock signal from the tracking clock signal based on said phase lag value and based on said phase lead value; and

30. The method of recovering data according to claim 26, 27, 28 or 29, comprising comparing said sampled amplitude against a decision threshold; and

outputting the comparison result and said tracking clock or sampling clock signal.