CN114094949A - Universal amplifier initialization circuit, device and method - Google Patents
Universal amplifier initialization circuit, device and method Download PDFInfo
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- CN114094949A CN114094949A CN202111338875.9A CN202111338875A CN114094949A CN 114094949 A CN114094949 A CN 114094949A CN 202111338875 A CN202111338875 A CN 202111338875A CN 114094949 A CN114094949 A CN 114094949A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/462—Indexing scheme relating to amplifiers the current being sensed
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Abstract
The invention discloses a universal amplifier initialization circuit, a device and a method, wherein the initialization circuit comprises a current acquisition circuit, a signal processing circuit, a voltage generation circuit and a state reporting circuit; the current acquisition circuit samples the leakage current of the amplifier into a voltage signal through a resistor, amplifies the voltage signal and then transmits the amplified voltage signal to the rear stage of the amplifier; the signal processing circuit samples the voltage signal transmitted by the front stage into a digital signal through the comparator and then generates various signals required by the rear stage through the logic operation circuit; the voltage generating circuit controls the up-down counter to generate binary numbers through signals generated by the logic operation circuit, and controls the switch of the transmission gate array after being coded by the decoding circuit, so that voltage signals on the resistor array are transmitted to VG selectively; and the state reporting circuit performs level conversion on the signal transmitted from the preceding stage, and transmits the signal to the upper computer after driving. The invention ensures the consistency of the static working points of the amplifying circuit and can improve the manufacturable type and the robustness of the product.
Description
Technical Field
The invention relates to the field of application of amplifier industry, in particular to a universal amplifier initialization circuit, a universal amplifier initialization device and a universal amplifier initialization method.
Background
When the problem of static operating point offset caused by transistor process deviation in an amplifier occurs, a variable voltage source is generally used as a gate voltage of the amplifier in the prior art, the variable voltage source needs to be manually adjusted before use to obtain a proper static operating point, and the problem of static operating point offset caused by aging of devices, change of use environments and the like cannot be solved, so that the manufacturability and robustness of products are poor.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a universal amplifier initialization circuit, a universal amplifier initialization device and a universal amplifier initialization method, which can save the procedure of manually adjusting the static working point in the production process caused by the process deviation of an amplifier, reduce the manufacturing difficulty, avoid the process disturbance caused by manual adjustment, ensure the consistency of the static working point of an amplifying circuit, solve the problems of device aging and static working point deviation caused by the change of the use environment which cannot be processed by the traditional means, and improve the manufacturability, robustness and the like of a product.
The purpose of the invention is realized by the following scheme:
a universal amplifier initialization circuit comprises a current acquisition circuit, a signal processing circuit, a voltage generation circuit and a state reporting circuit; the current acquisition circuit is provided with a resistor and an amplifier and is used for sampling the leakage current of the amplifier into a voltage signal through the resistor, amplifying the voltage signal and then transmitting the voltage signal to the rear stage of the amplifier; the signal processing circuit at the rear stage is provided with a comparator and a logic operation circuit, and the comparator and the logic operation circuit are used for sampling the voltage signal transmitted by the front stage into a digital signal and then generating various signals required by the rear stage through the logic operation circuit; the voltage generating circuit is provided with a lifting counting circuit, a decoding circuit, a transmission gate array and a resistor array, and is used for controlling a lifting counter to generate binary numbers through signals generated by the logic operation circuit, and controlling the switch of the transmission gate array after the binary numbers are coded by the decoding circuit, so that voltage signals on the resistor array can be selectively transmitted to VG; the state reporting circuit is provided with a driving circuit and is used for carrying out level conversion on signals transmitted from a preceding stage of the state reporting circuit, and transmitting the signals to an upper computer after driving.
Further, the logic operation circuit generates signals required by the rear stage including a REPORT signal, a U/D signal, an INC signal, and an EN signal.
Furthermore, the voltage generating circuit controls a lifting counter to generate different 5-bit binary numbers through a U/D signal, an INC signal and an EN signal, and the binary numbers are coded into 32-bit one-hot codes by the decoding circuit to control the switching of the transmission gate array.
Further, in the status reporting circuit, the level shifting the signal transmitted from the previous stage includes level shifting the REPORT signal transmitted from the previous stage.
Further, the decoding circuit comprises a 5-32 decoder.
Furthermore, the signal processing circuit is provided with a register, and the register is connected with the logic operation circuit.
A general-purpose amplifier initializing device is provided with the general-purpose amplifier initializing circuit as described above.
A method for initializing a general-purpose amplifier, comprising the steps of: the initialization processing of the general-purpose amplifier is performed by using the general-purpose amplifier initialization circuit as described above.
The invention has the beneficial effects that:
the invention belongs to the field of application of amplifier industry, and provides an automatic initialization scheme of an amplifier, which comprises a corresponding circuit, a device and a method, and can solve the problem of static working point offset caused by process deviation of a transistor in the amplifier, aging of a device, change of a use environment and the like. In an embodiment, for example, an initialization circuit related to an amplifier is provided, which can automatically acquire an operating current of a transistor in the amplifier for controlling a gate voltage change of the transistor when the amplifier is powered on, provide a current acquisition interface and a gate voltage bias interface for the amplifier, provide an initialization state signal interface for an upper computer, and implement automatic initialization and state reporting of the amplifier.
The universal amplifier initialization circuit provided by the embodiment of the invention can be added into the design of an amplifying circuit, can save the procedure of manually adjusting the static working point in the production process caused by the process deviation of the amplifier, reduces the manufacturing difficulty, avoids the process disturbance caused by manual adjustment, ensures the consistency of the static working point of the amplifying circuit, can solve the problems of device aging and static working point offset caused by the change of the use environment which cannot be processed by the traditional means, and improves the manufacturability and the robustness of the product.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a system block diagram of the general amplifier initialization circuit.
Fig. 2 is a schematic diagram of a current acquisition circuit in an embodiment of the invention.
Fig. 3 is a schematic diagram of a signal processing circuit in an embodiment of the invention.
Fig. 4 is a schematic diagram of a voltage generation circuit in an embodiment of the invention.
Fig. 5 is a schematic diagram of a status reporting circuit according to an embodiment of the present invention.
FIG. 6 is a simulation diagram of the transfer characteristics of M2N7000 in the embodiment of the present invention.
FIG. 7 is a simulation diagram of the output characteristics of M2N7000 in the embodiment of the present invention.
FIG. 8 is a timing diagram of the initialization M2N7000-VG simulation result and the key signals in the embodiment of the present invention.
FIG. 9 is a timing diagram of the simulation results and key signals for initializing M2N7000-IDS in the embodiment of the present invention.
Detailed Description
All features disclosed in all embodiments in this specification, or all methods or process steps implicitly disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.
As shown in fig. 1, a general amplifier initialization circuit includes a current collection circuit, a signal processing circuit, a voltage generation circuit, and a state reporting circuit; the current acquisition circuit is provided with a resistor and an amplifier and is used for sampling the leakage current of the amplifier into a voltage signal through the resistor, amplifying the voltage signal and then transmitting the voltage signal to the rear stage of the amplifier; the signal processing circuit at the rear stage is provided with a comparator and a logic operation circuit, and the comparator and the logic operation circuit are used for sampling the voltage signal transmitted by the front stage into a digital signal and then generating various signals required by the rear stage through the logic operation circuit; the voltage generating circuit is provided with a lifting counting circuit, a decoding circuit, a transmission gate array and a resistor array, and is used for controlling a lifting counter to generate binary numbers through signals generated by the logic operation circuit, and controlling the switch of the transmission gate array after the binary numbers are coded by the decoding circuit, so that voltage signals on the resistor array can be selectively transmitted to VG; the state reporting circuit is provided with a driving circuit and is used for carrying out level conversion on signals transmitted from a preceding stage of the state reporting circuit, and transmitting the signals to an upper computer after driving.
In an alternative embodiment of the present invention, it should be noted that the signals required by the logic operation circuit to generate the back stage include a REPORT signal, a U/D signal, an INC signal, and an EN signal.
In an alternative embodiment of the present invention, it should be noted that the voltage generating circuit controls an up-down counter to generate different 5-bit binary numbers through the U/D signal, the INC signal, and the EN signal, and encodes the binary numbers into 32-bit unique codes through the decoding circuit to control the switching of the transmission gate array.
In an alternative embodiment of the present invention, it should be noted that, in the status REPORT circuit, performing level conversion on the signal transmitted from the previous stage includes performing level conversion on the REPORT signal transmitted from the previous stage.
In an alternative embodiment of the present invention, it should be noted that the decoding circuit includes a 5-32 decoder.
In an alternative embodiment of the present invention, it should be noted that the signal processing circuit is provided with a register, and the register is connected to the logic operation circuit.
In an alternative embodiment of the present invention, for example, a general-purpose amplifier initializing device is provided with the general-purpose amplifier initializing circuit as described above.
In an alternative embodiment of the present invention, for example, a general amplifier initialization method includes the steps of: the initialization processing of the general-purpose amplifier is performed by using the general-purpose amplifier initialization circuit as described above.
In the alternative embodiment of the invention, the technical scheme is explained in detail as follows:
as shown in fig. 1, the device comprises a current collecting circuit, a signal processing circuit, a voltage generating circuit, and a state reporting circuit.
As shown in fig. 2, the current collection circuit samples the leakage current of the amplifier into a voltage signal through a resistor, and the voltage signal is amplified and then transmitted to a subsequent stage.
As shown in fig. 3, the signal processing circuit samples the voltage signal transmitted from the previous stage into a digital signal through two comparators, and generates various signals required by the subsequent stage through a logic operation circuit, including REPORT (single bit state reporting), U/D (voltage up-down control), INC (voltage up-down clock), and EN (voltage up-down enable).
As shown in fig. 4, the voltage generation circuit controls an up-down counter to generate different 5-bit binary numbers through U/D, INC and EN, and encodes the binary numbers into 32-bit one-hot codes by the decoding circuit to control the switches of the transmission gate array, so that the voltage signal on the resistor array is selectively transmitted to VG.
As shown in fig. 5, the status reporting circuit performs level conversion on the REPORT signal transmitted from the previous stage, and transmits the REPORT signal to the upper computer after driving.
As shown in fig. 2, the current collection circuit samples Ids (drain current of the transistor in the amplifier) through a small resistor R1 to obtain Vref:
Vref＝R1*Ids
amplifying the Vref to obtain U0:
as shown in fig. 3, the signal processing circuit schematic diagram samples U0 as UH _ temp and UL _ temp by the comparator, and the ratio of R4 to R5 and R6 to R7 is changed to control the size of Ids:
TABLE 1UH _ temp and UL _ temp truth tables
After passing through the logic operation circuit, EN, U/D, INC, and REPORT truth tables are shown in Table 2.
Table 2 signal processing circuit output truth table
After Ids is stabilized in the setting interval for a period of time (128 CLK cycles), EN, U/D, INC, and REPORT truth tables are shown in Table 3, and at this time, the initialization of the circuit is completed, and the amplifier static bias is no longer controlled by Ids.
Table 3 truth table of signals after initialization is completed
As shown in fig. 4, in the voltage generating circuit, EN and U/D, INC are respectively an enable signal, an add-subtract control signal, and a clock signal of the 5-bit binary up-down counter, the output 5-bit binary is encoded into 32 as a one-hot code after passing through the 5-32 decoder, the connection point of the transmission gate matrix and the resistor matrix is controlled to change the value of VG (the gate voltage of the transistor in the amplifier), and the associated signal truth table is shown in table 4.
TABLE 4 truth table of related signals of voltage generation circuit
Fig. 6 shows a transfer characteristic curve of the power fet M2N7000 simulated in the PSPICE, fig. 7 shows an output characteristic curve thereof, and table 5 shows a typical static operating point of the MOS transistor for power amplification.
TABLE 5 typical quiescent operating point for M2N7000 for power amplification
Initializing M2N7000 by using a general amplifier initialization circuit, placing the initialization circuit in the amplifier position in the schematic diagram of the current acquisition circuit shown in FIG. two, and performing simulation by using PSPICE, as shown in FIG. 7, FIG. 8 and FIG. 9, when the CLK period is 10us, VG is stabilized at 3.167V within 0.4ms, Ids is stabilized at 65.696mA, and the REPORT signal is set to high level within 1.5ms, which indicates that the initialization of the MOS transistor is completed. The initialized static operating point parameters are shown in table 6.
TABLE 6 static operating points after initialization completion of M2N7000
The present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention are intended to be equivalent substitutions and should be included within the scope of the present invention.
The functionality of the present invention, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium, and all or part of the steps of the method according to the embodiments of the present invention are executed in a computer device (which may be a personal computer, a server, or a network device) and corresponding software. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, or an optical disk, exist in a read-only Memory (RAM), a Random Access Memory (RAM), and the like, for performing a test or actual data in a program implementation.
Claims (8)
1. A universal amplifier initialization circuit is characterized by comprising a current acquisition circuit, a signal processing circuit, a voltage generation circuit and a state reporting circuit; the current acquisition circuit is provided with a resistor and an amplifier and is used for sampling the leakage current of the amplifier into a voltage signal through the resistor, amplifying the voltage signal and then transmitting the voltage signal to the rear stage of the amplifier; the signal processing circuit at the rear stage is provided with a comparator and a logic operation circuit, and the comparator and the logic operation circuit are used for sampling the voltage signal transmitted by the front stage into a digital signal and then generating various signals required by the rear stage through the logic operation circuit; the voltage generating circuit is provided with a lifting counting circuit, a decoding circuit, a transmission gate array and a resistor array, and is used for controlling a lifting counter to generate binary numbers through signals generated by the logic operation circuit, and controlling the switch of the transmission gate array after the binary numbers are coded by the decoding circuit, so that voltage signals on the resistor array can be selectively transmitted to VG; the state reporting circuit is provided with a driving circuit and is used for carrying out level conversion on signals transmitted from a preceding stage of the state reporting circuit, and transmitting the signals to an upper computer after driving.
2. The universal amplifier initialization circuit of claim 1, wherein the logic operation circuit generates the signals required by the back stage including a REPORT signal, a U/D signal, an INC signal, and an EN signal.
3. The universal amplifier initialization circuit of claim 2, wherein the voltage generation circuit controls an up-down counter to generate different 5-bit binary numbers through the U/D signal, the INC signal, and the EN signal, and encodes the binary numbers into 32-bit unique hot codes through the decoding circuit to control the switching of the transmission gate array.
4. The universal amplifier initialization circuit of claim 2, wherein the level shifting the signal delivered from the previous stage of the status reporting circuit comprises level shifting a REPORT signal delivered from the previous stage of the status reporting circuit.
5. The universal amplifier initialization circuit of claim 3, wherein the decoding circuit comprises a 5-32 decoder.
6. The general amplifier initialization circuit according to any one of claims 1 to 5, wherein the signal processing circuit is provided with a register, and the register is connected to the logic operation circuit.
7. A general amplifier initialization apparatus characterized in that the general amplifier initialization circuit according to claim 6 is provided.
8. A method for initializing a general-purpose amplifier, comprising the steps of: the initialization process of the general-purpose amplifier is performed using the general-purpose amplifier initialization circuit as set forth in claim 6.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442292A (en) * | 2007-11-19 | 2009-05-27 | 华为技术有限公司 | Radio-frequency amplifier digital bias circuit, method and communication equipment |
| CN108572305A (en) * | 2017-03-14 | 2018-09-25 | 大唐移动通信设备有限公司 | A kind of method and device of automatic Amplifier quiescent point |
| CN109088606A (en) * | 2017-06-14 | 2018-12-25 | 中兴通讯股份有限公司 | A kind of power amplifier quiescent current method of adjustment, device, system and storage medium |
| CN109660219A (en) * | 2018-12-07 | 2019-04-19 | 顺丰科技有限公司 | Calibration circuit, method, apparatus, equipment and the storage medium of power amplifier |
| CN110661501A (en) * | 2019-08-29 | 2020-01-07 | 电子科技大学 | Automatic locking circuit for setting quiescent point of power amplifier |
-
2021
- 2021-11-12 CN CN202111338875.9A patent/CN114094949A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101442292A (en) * | 2007-11-19 | 2009-05-27 | 华为技术有限公司 | Radio-frequency amplifier digital bias circuit, method and communication equipment |
| CN108572305A (en) * | 2017-03-14 | 2018-09-25 | 大唐移动通信设备有限公司 | A kind of method and device of automatic Amplifier quiescent point |
| CN109088606A (en) * | 2017-06-14 | 2018-12-25 | 中兴通讯股份有限公司 | A kind of power amplifier quiescent current method of adjustment, device, system and storage medium |
| CN109660219A (en) * | 2018-12-07 | 2019-04-19 | 顺丰科技有限公司 | Calibration circuit, method, apparatus, equipment and the storage medium of power amplifier |
| CN110661501A (en) * | 2019-08-29 | 2020-01-07 | 电子科技大学 | Automatic locking circuit for setting quiescent point of power amplifier |
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