WO2016138706A1

WO2016138706A1 - Clock switching method and clock switching device

Info

Publication number: WO2016138706A1
Application number: PCT/CN2015/082234
Authority: WO
Inventors: 文显琼; 赵恒正
Original assignee: 中兴通讯股份有限公司
Priority date: 2015-03-03
Filing date: 2015-06-24
Publication date: 2016-09-09
Also published as: CN105991110A

Abstract

Disclosed is a clock switching method. The clock switching method comprises the following steps: receiving a selection instruction, and acquiring a selection signal value; if the selection signal value is a first preset value, then gating a first clock; receiving a switching signal transmitted by a second clock; determining a logic or operation result of the first clock and the second clock; and according to the logic or operation result, switching to gate the second clock or controlling the first clock to perform a complete clock cycle. Also disclosed is a clock switching device. The present invention reduces the probability of an output clock undergoing a narrow wave pulse phenomenon when the selection signal is randomly switched.

Description

Clock switching method and clock switching device

Technical field

The present invention relates to the field of communications technologies, and in particular, to a clock switching method and a clock switching device.

Background technique

In an integrated circuit, it is often necessary to adjust the operating clock frequency of the system according to different working scenarios. The existing solution usually uses a multi-selector to determine the strobed clock according to the number of the input selector, and It is entered into the system. However, this solution has at least the following disadvantages: in the case where the system needs to perform switching of more than two clocks, the selection signal may be unstable during the switching process, which may cause instability of the clock signal.

The above content is only used to assist in understanding the technical solutions of the present invention, and does not constitute an admission that the above is prior art.

Summary of the invention

Embodiments of the present invention provide a clock switching method and a clock switching apparatus, which are designed to reduce the probability of occurrence of a narrow-wave pulse phenomenon on an output clock when a selection signal is randomly switched.

To achieve the above objective, an embodiment of the present invention provides a method for clock switching, and the method for clock switching includes the following steps:

Receiving a selection instruction and obtaining a selection signal value;

When the selection signal value is the first preset value, the first clock is strobed;

Receiving a switching signal sent by the second clock;

Determining a logical OR operation result of the first clock and the second clock;

Switching the strobe second clock or controlling the first clock completes a complete clock cycle according to the logical OR operation result.

Preferably, the step of switching the strobe second clock or controlling the first clock to complete a complete clock cycle according to the logical OR operation result includes:

Switching the strobe second clock when the logical OR operation result of the first clock and the second clock is the second preset value;

When the logical OR operation result of the first clock and the second clock is a third preset value, the first clock is controlled to complete a complete clock cycle.

Preferably, the selection signal value is a single bit signal value.

Preferably, the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four first clocks, a second clock, a third clock, and a fourth clock pre-configured with corresponding one-hot codes. After the step of receiving the switching signal sent by the second clock, the method further includes:

Obtaining a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

Determining whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

The operating state of the first clock is maintained or the first clock is switched to a second clock depending on whether there is an intermediate state.

Preferably, the step of maintaining the working state of the first clock or switching the first clock to the second clock according to whether there is an intermediate state comprises:

If there is an intermediate state, maintaining an operating state of the first clock;

If there is no intermediate state, the first clock is switched to the second clock.

In addition, in order to achieve the above object, an embodiment of the present invention further provides a clock switching apparatus, where the clock switching apparatus includes:

a first acquiring module, configured to receive a selection instruction, and obtain a selection signal value;

The strobe module is configured to strobe the first clock when the selection signal value is the first preset value;

a receiving module, configured to receive a switching signal sent by the second clock;

a first determining module, configured to determine a logical OR operation result of the first clock and the second clock;

The first control module is configured to switch the strobe second clock or control the first clock to complete a complete clock cycle according to the logical OR operation result.

Preferably, the control module comprises:

The first switching unit is configured to switch the strobe second clock when the logical OR operation result of the first clock and the second clock is the second preset value;

The control unit is configured to control the first clock to complete a complete clock cycle when a logical OR operation result of the first clock and the second clock is a third preset value.

Preferably, the selection signal value is a single bit signal value.

Preferably, the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four first clocks, a second clock, a third clock, and a fourth clock pre-configured with corresponding one-hot codes. The clock switching device further includes:

a second acquiring module, configured to acquire a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

The second determining module is configured to determine whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

The second control module is configured to maintain an operating state of the first clock or switch the first clock to a second clock according to whether an intermediate state exists.

Preferably, the second control module comprises:

a working unit, configured to maintain an operating state of the first clock if an intermediate state exists;

The second switching unit is configured to switch the first clock to the second clock if there is no intermediate state.

The method for clock switching and the clock switching apparatus provided by the embodiment of the present invention determine the logical OR operation result of the first clock and the second clock when receiving the switching signal sent by the second clock, and according to the logical OR operation result, Switching the strobe second clock or controlling the first clock completes a complete clock cycle. In this way, the probability of a narrow-wave pulse phenomenon on the output clock when the selection signal is randomly switched can be reduced. In addition, by encoding the first clock, the second clock, the third clock, and the fourth clock having the corresponding unique heat codes by the unique heat, it is possible to prevent the plurality of clocks from being turned on to interfere with the working clock due to the instability of the selection signal itself. The phenomenon of the signal ensures a stable state of the clock switching device.

DRAWINGS

1 is a schematic flowchart of a first embodiment of a method for clock switching according to the present invention;

2 is a schematic diagram of a selection signal and a corresponding output clock signal according to an embodiment of a method for clock switching according to the present invention;

3 is a schematic flowchart of a second embodiment of a method for clock switching according to the present invention;

4 is a schematic flowchart diagram of a third embodiment of a method for clock switching according to the present invention;

FIG. 5 is a schematic flowchart diagram of a fourth embodiment of a method for clock switching according to the present invention; FIG.

6 is a schematic diagram of a selection signal and a corresponding output clock signal according to another embodiment of a method for clock switching according to the present invention;

7 is a schematic diagram of functional modules of a first embodiment of a clock switching apparatus according to the present invention;

8 is a schematic diagram of functional modules of an embodiment of the first control module of FIG. 7;

9 is a schematic diagram of functional modules of a second embodiment of a clock switching device according to the present invention;

FIG. 10 is a schematic diagram of functional modules of an embodiment of the second control module of FIG. 9. FIG.

The implementation, functional features, and advantages of the present invention will be further described in conjunction with the embodiments.

detailed description

It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The present invention provides a method for clock switching. Referring to FIG. 1, in an embodiment, the method for clock switching includes the following steps:

Step S101, receiving a selection instruction, and acquiring a selection signal value;

Step S102, when the selection signal value is the first preset value, stroking the first clock;

In the preferred embodiment, the clock switching device acquires the corresponding selection signal value when receiving the selection instruction. The first clock is clk_0 and the second clock is clk_1. The first preset value is 0, and the second preset value is 1. When the selection signal value Select is 0, the clk_0 is gated, and when the selection signal value Select is 1, the clk_1 is gated. of course, In other embodiments, clk_1 may be strobed when the selection signal value is 0, and clk_0 is strobed when the selection signal value Select is 1.

Step S103, receiving a switching signal sent by the second clock;

In this embodiment, referring to FIG. 2, A_state indicates that the first clock clk_0 is in an active state in the current clock switching device, B_state indicates that the second clock clk_1 in the current clock switching device is in an active state, and Clk_out indicates an output clock signal of the current clock switching device.

A_state is generated by using the first clock clk_0 to shoot the "non" of the select signal select, that is:

Always@(negedge clk_0)

A_state<=! Select

The way B_state is generated is to use clk_1 to shoot the selection signal select, that is:

Always@(posedge clk_1)

B_state<=select

The A_state generated by the above method has a state in which the integer multiple of clk_0 is used as the jump timing. That is, if the select changes immediately after a rising edge of clk_0, the A_state does not follow the select. The change immediately changes, but after the falling edge of the clock of clk_0 comes, the state of A_state reflects the change of select. This ensures that when the clock is switched, the full cycle of the previous clock is always used as the switching opportunity to avoid unexpected narrow-wave pulses.

B_state changes in a similar way to A_state.

That is, when the first clock needs to be switched to the second clock, the selection signal changes immediately after a rising edge of clk_0. Before the falling edge of clk_0 arrives, the working state A_state corresponding to clk_0 is still in the active state, indicating clk_0 The new clock is not turned off, the clock switch will continue to output a full pulse of clk_0, and wait until the falling edge of clk_0 arrives, A_state will be invalid.

Step S104, determining a logical OR operation result of the first clock and the second clock;

Step S105, according to the logical OR operation result, switching the strobe second clock or controlling the first clock to complete a complete clock cycle.

In this embodiment, the clock switching device performs a logical OR operation on the A_state and the B_state, and switches the strobe second clock or controls the first clock to complete a complete clock cycle according to the logical OR operation result. The logical OR operation result may be 0 or 1, and may be reasonably set according to actual needs.

The method for clock switching provided by the present invention determines the logical OR operation result of the first clock and the second clock when receiving the switching signal sent by the second clock, and switches the strobe second clock according to the logical OR operation result Or controlling the first clock to complete a complete clock cycle. In this way, the probability of a narrow-wave pulse phenomenon on the output clock when the selection signal is randomly switched can be reduced.

In an embodiment, as shown in FIG. 3, on the basis of the foregoing embodiment of FIG. 1, in the embodiment, the step S105 includes:

Step S1051, when the logical OR operation result of the first clock and the second clock is a second preset value, switching the strobe second clock;

In this embodiment, if the logical OR operation result is the second preset value, such as 0, it means that there is no clock in the current clock switching device, and a new clock such as the second clock can be turned on at this time, so that the clock can be prevented from being generated when the switch is switched. Narrow wave pulse.

Step S1052: Control the first clock to complete a complete clock cycle when a logical OR operation result of the first clock and the second clock is a third preset value.

In this embodiment, the clock switching device performs a logical OR operation on the A_state and the B_state. If the logical OR operation result is a third preset value, such as 1, it indicates that the first clock is still in the working state when the clk_0 is not closed. The clock switching device does not turn on the new clock and controls the first clock to continue outputting a complete pulse of clk_0 and waits until the falling edge of clk_0 arrives, invalidating A_state even if the first clock is off.

In an embodiment, on the basis of the foregoing embodiment of FIG. 1 or FIG. 3, the selection signal value is a single-bit signal value, that is, the selection signal value is 0 or 1, corresponding to the first clock clk_0 and the second clock, respectively. Clk_1.

In an embodiment, as shown in FIG. 4 and FIG. 6, on the basis of the foregoing embodiment of FIG. 1, in the embodiment, the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four. The first clock, the second clock, the third clock, and the fourth clock are provided with a corresponding one-hot code. The step S103 further includes:

Step S107, acquiring a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

In the preferred embodiment, the clock selection signal select is subjected to the unique thermal coding, and the unique thermal coding is the state corresponding to the number of bits of the selection signal, and only one bit is the fourth preset value such as 1, and the others are all 0. A code system. The biggest advantage of this unique thermal coding is that only one bit needs to be compared when making a judgment, which simplifies the decoding logic. After the four states of the selection signal select are encoded as the unique heat codes, the corresponding selected clocks are as shown in Table 1 below, wherein the unique heat code is 4 bits, and the corresponding clock is selected according to 1 on different bits. It can be understood that, in other embodiments, the number of bits of the unique heat code can be set reasonably, or only one bit can be set to 0, and all others are all 1, which is not limited to the embodiment.

Table I:

select[1:0]Select[1:0]	独热码Single heat code	选择时钟Select clock
select[1:0]Select[1:0]	独热码Single heat code	选择时钟Select clock	0000	00010001	clk_0Clk_0
0101	00100010	clk_1Clk_1	0000	00010001	clk_0Clk_0
0101	00100010	clk_1Clk_1	1010	01000100	clk_2Clk_2
1111	10001000	clk_3Clk_3	1010	01000100	clk_2Clk_2

In this embodiment, the bit number of 1 in the first clock clk_0 is obtained as the 0th bit, and the bit number of 2 in the second clock clk_1 is the 3rd bit.

Step S108, determining whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

In this embodiment, the clock switching device determines whether there is an intermediate state when the first clock clk_0 is switched to the second clock clk_1, and the corresponding unique heat code needs to be switched from 0001 to 0010, that is, the 0th bit of the unique heat code is changed from 1 to 1. 0, the second bit has to change from 0 to 1. It can be understood that there may be a problem that the conversion time is inconsistent at this time, resulting in an intermediate state of 0000 or 0011. When the heat code needs to be switched from 0001 to 0100, its possible intermediate state is 0000 or 0101. When the heat code needs to be switched from 0001 to 1000, its possible intermediate state is 1001 or 1001, and other switching states are no longer. Narration.

Step S109, maintaining an operating state of the first clock or switching the first clock to a second clock according to whether there is an intermediate state.

In this embodiment, if there is an intermediate state 0000 or 0011 when the first clock clk_0 is switched to the second clock clk_1, since it cannot correspond to any clock such as clk_0 to clk_3, the unexpected clock is not turned on, and the clock is switched. The device remains in the previous state, the operating state of the first clock, until the new state is stable. If there is no intermediate state 0000 or 0011 when the first clock clk_0 is switched to the second clock clk_1, the switching of converting the first clock to the second clock is completed.

In an embodiment, as shown in FIG. 5, on the basis of the foregoing embodiment of FIG. 4, in the embodiment, the step S109 includes:

Step S1091, if there is an intermediate state, maintaining an operating state of the first clock;

In this embodiment, if there is an intermediate state 0000 or 0011, since it cannot correspond to any clock such as clk_0 to clk_3, the clock switching device still maintains the previous state, that is, the working state of the first clock until the new state is stable, such that Does not cause an unexpected clock to turn on.

In step S1092, if there is no intermediate state, the first clock is switched to the second clock.

In this embodiment, if the intermediate state 0000 or 0011 is not present when the first clock is switched to the second clock, the 0th bit of the unique heat code of the first clock has changed from 1 to 0, and the second The bit has changed from 0 to 1, at which point the clock switching device enters the operating state of the second clock.

In this embodiment, by independently encoding the first clock, the second clock, the third clock, and the fourth clock having the corresponding heat-up codes, it is possible to prevent multiple clocks from being turned on due to instability of the selection signal itself. The phenomenon of disturbing the working clock signal ensures the steady state of the clock switching device.

The present invention further provides a clock switching device 1. Referring to FIG. 7, in an embodiment, the clock switching device 1 includes:

The first obtaining module 101 is configured to receive a selection instruction and acquire a selection signal value;

The strobe module 102 is configured to strobe the first clock when the selection signal value is the first preset value;

In the preferred embodiment, the clock switching device acquires the corresponding selection signal value when receiving the selection instruction. The first clock is clk_0 and the second clock is clk_1. The first preset value is 0, and the second preset value is 1. When the selection signal value is 0, strobe clk_0, and when the selection signal value is 1, strobe clk_1. Of course, in other embodiments, clk_1 may be strobed when the selection signal value is 0, and clk_0 is strobed when the selection signal value is 1.

The receiving module 103 is configured to receive a switching signal sent by the second clock;

In this embodiment, referring to FIG. 2, A_state indicates that the first clock clk_0 in the current clock switching device 1 is in an active state, B_state indicates that the second clock clk_1 in the current clock switching device 1 is in an active state, and Clk_out indicates an output clock of the current clock switching device. signal.

Always@(negedge clk_0)

A_state<=! Select

Always@(posedge clk_1)

B_state<=select

B_state changes in a similar way to A_state.

That is, when the first clock needs to be switched to the second clock, the selection signal changes immediately after a rising edge of clk_0. Before the falling edge of clk_0 arrives, the working state A_state corresponding to clk_0 is still in the active state, indicating clk_0 If the new clock is not turned off and the new clock cannot be turned on, the clock switching device 1 will continue to output a complete pulse of clk_0, and wait until the falling edge of clk_0 arrives, and A_state will be invalid.

The first determining module 104 is configured to determine a logical OR operation result of the first clock and the second clock;

The first control module 105 is configured to switch the strobe second clock or control the first clock to complete a complete clock cycle according to the logical OR operation result.

In this embodiment, the clock switching device 1 performs a logical OR operation on the A_state and the B_state, and switches the strobe second clock or controls the first clock to complete a complete clock cycle according to the logical OR operation result. The logical OR operation result may be 0 or 1, and may be reasonably set according to actual needs.

The clock switching device 1 provided by the present invention determines the logical OR operation result of the first clock and the second clock when receiving the switching signal transmitted by the second clock, and switches the strobe second clock according to the logical OR operation result. Or controlling the first clock to complete a complete clock cycle. In this way, the probability of a narrow-wave pulse phenomenon on the output clock when the selection signal is randomly switched can be reduced.

In an embodiment, as shown in FIG. 8, on the basis of the foregoing embodiment of FIG. 7, in the embodiment, the first control module 105 includes:

The first switching unit 1051 is configured to switch the strobe second clock when the logical OR operation result of the first clock and the second clock is the second preset value;

The control unit 1052 is configured to control the first clock to complete a complete clock cycle when a logical OR operation result of the first clock and the second clock is a third preset value.

In this embodiment, the clock switching device 1 performs a logical OR operation on the A_state and the B_state. If the logical OR operation result is a third preset value, such as 1, it indicates that the first clock is still in the working state when clk_0 is not closed. At this time, the clock switching device 1 does not turn on a new clock, and controls the first clock to continue outputting a complete pulse of clk_0, and waits until the falling edge of clk_0 comes, causing A_state to be disabled even if the first clock is in the off state.

In an embodiment, on the basis of the foregoing embodiment of FIG. 7 or FIG. 8, the selection signal value is a single-bit signal value, that is, the selection signal value is 0 or 1, corresponding to the first clock clk_0 and the second clock, respectively. Clk_1.

In an embodiment, referring to 9, on the basis of the foregoing embodiment of FIG. 7, the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four types of pre-configured corresponding unique heat codes. The clock switching device 1 further includes: a clock, a second clock, a third clock, and a fourth clock:

The second obtaining module 107 is configured to obtain a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

In the preferred embodiment, the clock selection signal select is subjected to the unique thermal coding, and the unique thermal coding is the state corresponding to the number of bits of the selection signal, and only one bit is the fourth preset value such as 1, and the others are all 0. A code system. The biggest advantage of this unique thermal coding is that only one bit needs to be compared when making a judgment, which simplifies the decoding logic. After the four states of the selection signal select are coded as the single heat code, the corresponding selected clock is as shown in Table 1, where the heat is unique. The code is 4 bits, and the corresponding clock is selected according to 1 on different bits. It can be understood that, in other embodiments, the number of bits of the unique heat code can be set reasonably, or only one bit can be set to 0, and all others are all 1, which is not limited to the embodiment.

Table II:

The second determining module 108 is configured to determine whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

In this embodiment, the clock switching device 1 determines whether there is an intermediate state when the first clock clk_0 is switched to the second clock clk_1, and the corresponding one-hot code needs to be switched from 0001 to 0010, that is, the 0th bit of the unique heat code is changed from 1 It is 0, and the 2nd bit is changed from 0 to 1. It can be understood that there may be a problem that the conversion time is inconsistent at this time, resulting in an intermediate state of 0000 or 0011. When the heat code needs to be switched from 0001 to 0100, its possible intermediate state is 0000 or 0101. When the heat code needs to be switched from 0001 to 1000, its possible intermediate state is 1001 or 1001, and other switching states are no longer. Narration.

The second control module 109 is configured to maintain an operating state of the first clock or switch the first clock to a second clock according to whether an intermediate state exists.

In this embodiment, referring to FIG. 6, if there is an intermediate state 0000 or 0011 when the first clock clk_0 is switched to the second clock clk_1, since it cannot correspond to any clock such as clk_0 to clk_3, it does not cause an unexpected clock. When turned on, the clock switching device 1 still maintains the previous state, that is, the operating state of the first clock, until the new state is stable. If there is no intermediate state 0000 or 0011 when the first clock clk_0 is switched to the second clock clk_1, the switching of converting the first clock to the second clock is completed.

In an embodiment, referring to 10, on the basis of the foregoing embodiment of FIG. 9, in the embodiment, the second control module 109 includes:

The working unit 1091 is configured to maintain an operating state of the first clock if an intermediate state exists;

The second switching unit 1092 is configured to switch the first clock to the second clock if there is no intermediate state.

In this embodiment, if the intermediate state 0000 or 0011 is not present when the first clock is switched to the second clock, the 0th bit of the unique heat code of the first clock has changed from 1 to 0, and the second The bit has changed from 0 to 1, at which time the clock switching device 1 enters the operating state of the second clock.

In this embodiment, by independently encoding the first clock, the second clock, the third clock, and the fourth clock having the corresponding heat-up codes, it is possible to prevent multiple clocks from being turned on due to instability of the selection signal itself. The phenomenon of disturbing the working clock signal ensures the steady state of the clock switching device 1.

The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the invention, and the equivalent structure or equivalent process transformations made by the description of the present invention and the drawings are directly or indirectly applied to other related technical fields. The same is included in the scope of patent protection of the present invention.

Industrial applicability

As described above, the clock switching method and the clock switching apparatus provided by the embodiments of the present invention have the following beneficial effects: it can prevent the phenomenon that multiple clocks are turned on and interfere with the working clock signal due to instability of the selection signal itself. Thereby ensuring a steady state of the clock switching device.

Claims

A method for clock switching, the method for clock switching includes the following steps:

Receiving a selection instruction and obtaining a selection signal value;

When the selection signal value is the first preset value, the first clock is strobed;

Receiving a switching signal sent by the second clock;

Determining a logical OR operation result of the first clock and the second clock;

Switching the strobe second clock or controlling the first clock completes a complete clock cycle according to the logical OR operation result.
The method of clock switching according to claim 1, wherein the step of switching the strobe second clock or controlling the first clock to complete a complete clock cycle according to the logical OR operation result comprises:

Switching the strobe second clock when the logical OR operation result of the first clock and the second clock is the second preset value;

When the logical OR operation result of the first clock and the second clock is a third preset value, the first clock is controlled to complete a complete clock cycle.
The method of clock switching according to any one of claims 1 to 2, wherein the selection signal value is a single bit signal value.
The method of clock switching according to any one of claims 1 to 2, wherein the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four types of pre-set corresponding one-hot codes. The step of receiving the switching signal sent by the second clock further includes: a clock, a second clock, a third clock, and a fourth clock,

Obtaining a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

Determining whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

The operating state of the first clock is maintained or the first clock is switched to a second clock depending on whether there is an intermediate state.
The method of clock switching according to claim 4, wherein the step of maintaining an operating state of the first clock or switching the first clock to a second clock according to whether there is an intermediate state comprises:

If there is an intermediate state, maintaining an operating state of the first clock;

If there is no intermediate state, the first clock is switched to the second clock.
A clock switching device, the clock switching device comprising:

a first acquiring module, configured to receive a selection instruction, and obtain a selection signal value;

The strobe module is configured to strobe the first clock when the selection signal value is the first preset value;

a receiving module, configured to receive a switching signal sent by the second clock;

a first determining module, configured to determine a logical OR operation result of the first clock and the second clock;

The first control module is configured to switch the strobe second clock or control the first clock to complete a complete clock cycle according to the logical OR operation result.
The clock switching device of claim 6, wherein the first control module comprises:

The first switching unit is configured to switch the strobe second clock when the logical OR operation result of the first clock and the second clock is the second preset value;

The control unit is configured to control the first clock to complete a complete clock cycle when a logical OR operation result of the first clock and the second clock is a third preset value.
The clock switching device according to claim 6 or 7, wherein said selection signal value is a single bit signal value.
The clock switching device according to claim 6 or 7, wherein the selection signal value is a two-bit signal value, and the two-bit signal value corresponds to four first clocks and second numbers pre-set with corresponding one-hot codes. The clock switching device further includes: a clock, a third clock, and a fourth clock

a second acquiring module, configured to acquire a first bit number of the fourth preset value in the unique heat code of the first clock and a second bit number of the fourth preset value in the unique heat code of the second clock;

The second determining module is configured to determine whether there is an intermediate state when the first bit number and the second bit number of the first clock are correspondingly switched to the second clock;

The second control module is configured to maintain an operating state of the first clock or switch the first clock to a second clock according to whether an intermediate state exists.
The clock switching device of claim 9, wherein the second control module comprises:

a working unit, configured to maintain an operating state of the first clock if an intermediate state exists;

The second switching unit is configured to switch the first clock to the second clock if there is no intermediate state.