CN114093933A - Preparation method of amorphous oxide floating gate transistor containing perovskite quantum dots - Google Patents

Preparation method of amorphous oxide floating gate transistor containing perovskite quantum dots Download PDF

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CN114093933A
CN114093933A CN202111148165.XA CN202111148165A CN114093933A CN 114093933 A CN114093933 A CN 114093933A CN 202111148165 A CN202111148165 A CN 202111148165A CN 114093933 A CN114093933 A CN 114093933A
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perovskite quantum
floating gate
amorphous oxide
quantum dots
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刘苏熤
万青
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Nanjing University
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate

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Abstract

The invention discloses a preparation method of an amorphous oxide floating gate transistor containing perovskite quantum dots. The indium gallium zinc oxide thin film transistor memory or the photoelectric detector sequentially comprises a source drain electrode, a channel layer, a tunneling insulating medium layer, a floating gate layer, a gate insulating layer, a gate electrode and a substrate from top to bottom. The channel layer is made of amorphous oxide, and the floating gate layer is made of perovskite quantum dot thin film. The invention can effectively improve the incident light collection efficiency of the device, enhance the photoelectric conversion efficiency, realize large current density and excellent storage characteristics, and has important potential application prospect in the aspects of photosensitive memories, intelligent photoelectric sensors and the like.

Description

Preparation method of amorphous oxide floating gate transistor containing perovskite quantum dots
Technical Field
The invention belongs to the field of memory technology and optical detection technology in the semiconductor industry, and relates to an amorphous oxide floating gate transistor containing perovskite quantum dots and a preparation method thereof.
Background
With the rapid development of flat panel display technology and the demand of the market for higher information content, high performance thin film transistors, which are key elements of system panels, have been widely researched and made great progress. Among them, metal oxide thin film transistors (motts) gradually replace conventional amorphous silicon (a-Si) TFTs and Low Temperature Polysilicon (LTPS) TFTs with their advantages of high electron mobility, simple process, low cost, good large area uniformity, etc., and become a new focus in the industry.
The working principle of the metal oxide thin film transistor memory is that under the condition of external grid voltage or light induction, a storage function layer of the device can capture charges generated by a channel layer or enable the material of the storage function layer to generate a polarization phenomenon, so that threshold voltage shifts, and the storage performance which is required by people is achieved.
Common memories can be classified into three types, namely ferroelectric type, floating gate type and electret type. Among these types, the floating gate memory has advantages of low power consumption, low cost, high flexibility, high storage density, and the like. Currently, common floating gate memory materials are: metal nanoparticles, two-dimensional nanosheets, metal oxides, and the like. But they also have the disadvantages of difficulty in scaling down the device size, higher operating voltage, narrow absorption spectrum, difficulty in integration, etc.
Disclosure of Invention
The purpose of the invention is as follows: the invention aims to provide a preparation method of an amorphous oxide floating gate transistor containing perovskite quantum dots; the technical problems of high operating voltage, narrow absorption spectrum, difficulty in integration and the like in the prior art are solved.
The technical scheme is as follows: the amorphous oxide floating gate transistor containing perovskite quantum dots comprises a substrate (7) at the bottom end, a gate electrode (6) is formed on the substrate (7), a gate insulating layer (5) is formed on the gate electrode (6), a floating gate layer (4) is formed on the gate insulating layer (5), a tunneling insulating layer (3) is formed on the floating gate layer (4), a channel layer (2) is formed on the tunneling insulating layer (3), and a source drain electrode (1) is formed on the channel layer (2).
Furthermore, the source and drain electrodes (1) are made of any one of Al, Cu and Ag, and the thickness of the source and drain electrodes is 20-200 nm.
Furthermore, the channel layer (2) is made of amorphous metal oxide indium gallium zinc oxide, and the thickness of the channel layer is 10-50 nm.
Furthermore, the tunneling insulating dielectric layer (3) is made of Al2O3、Si3N4、SiO2The thickness of the single-layer insulating film or the multi-layer insulating film composed of any two or more insulating films is 4 to 20 nm.
Furthermore, the floating gate layer (4) is made of a perovskite quantum dot thin film, and the thickness of the perovskite quantum dot thin film is 5-20 nm.
Furthermore, the gate insulating layer (5) is made of Al2O3、Si3N4、SiO2The single-layer insulating film or the multilayer insulating film comprising two or more kinds of insulating films has a thickness of 10 to 200 nm.
Further, the gate electrode (6) is an ITO transparent conductive film.
Further, the substrate (7) is a highly doped silicon wafer, a glass sheet or plastic PET.
Further, a preparation method of the amorphous oxide floating gate transistor containing perovskite quantum dots comprises the following specific operation steps:
(1) preparing a perovskite quantum dot solution;
(2) sequentially forming a gate electrode (6) and a gate insulating layer (5) on a substrate (7) to prepare a substrate, and then cleaning and drying the substrate;
(3) and spin-coating the prepared perovskite quantum dot solution on a gate insulating layer (5) of the substrate, wherein the spin-coating rotating speed is kept at 3000r/m, and the spin-coating time is 40s, so that the following steps are formed: a perovskite quantum dot thin film layer (4);
(4) annealing a sample formed by the substrate (7), the gate electrode (6), the gate insulating layer (5) and the perovskite quantum dot thin film layer (4);
(5) then, depositing a tunneling insulating medium layer (3) on the annealed perovskite quantum dot thin film layer (4);
(6) and sputtering an indium gallium zinc oxide film channel layer (2) on the tunneling insulating medium layer (3) by using a mask, and evaporating a source drain electrode (1) in vacuum, thereby finally preparing the amorphous oxide floating gate transistor containing perovskite quantum dots.
Has the advantages that: compared with the prior art, the invention has the characteristics that: 1. compared with other common channel materials used for nonvolatile thin film transistor memories, such as polycrystalline silicon and organic semiconductor materials (pentacene), the metal oxide indium gallium zinc oxide has larger forbidden bandwidth and higher carrier mobility; this enables the device to exhibit better electrical stability, i.e. high breakdown voltage, better temperature stability, lower operating voltage, etc.; the indium gallium zinc oxide material also has good bending stability and has great application prospect in the aspect of flexible TFT devices; 2. the perovskite quantum dot film is used as the floating gate layer of the transistor memory, so that the collection efficiency of the device on incident light and X-rays is effectively improved, the photoelectric conversion efficiency is enhanced, and the charge tunneling barrier is reduced, thereby reducing the dependence on operating voltage, improving the storage and detection performance of the device, and expanding the application field of the device.
Drawings
FIG. 1 is a schematic structural view of the present invention;
in the figure, 1 is a source electrode, 2 is a channel layer, 3 is a tunneling insulating medium layer, 4 is a floating gate layer, 5 is a gate insulating layer, 6 is a gate electrode, and 7 is a substrate.
Detailed Description
The invention is further described below with reference to the following figures and specific examples.
As shown in the figure, the amorphous oxide floating gate transistor containing perovskite quantum dots comprises a substrate (7) at the bottom end, a gate electrode (6) is formed on the substrate (7), a gate insulating layer (5) is formed on the gate electrode (6), a floating gate layer (4) is formed on the gate insulating layer (5), a tunneling insulating layer (3) is formed on the floating gate layer (4), a channel layer (2) is formed on the tunneling insulating layer (3), and a source-drain electrode (1) is formed on the channel layer (2).
Furthermore, the source and drain electrodes (1) are made of any one of Al, Cu and Ag, and the thickness of the source and drain electrodes is 20-200 nm.
Furthermore, the channel layer (2) is made of amorphous metal oxide Indium Gallium Zinc Oxide (IGZO) and has a thickness of 10-50 nm.
Furthermore, the tunneling insulating dielectric layer (3) is made of Al2O3、Si3N4、SiO2The thickness of the single-layer insulating film or the multi-layer insulating film composed of any two or more insulating films is 4 to 20 nm.
Furthermore, the floating gate layer (4) is made of a perovskite quantum dot thin film (CsPbX)3Etc.) of 5 to 20nm in thickness.
Furthermore, the gate insulating layer (5) is made of Al2O3、Si3N4、SiO2The single-layer insulating film or the multilayer insulating film comprising two or more kinds of insulating films has a thickness of 10 to 200 nm.
Further, the gate electrode (6) is an ITO transparent conductive film.
Further, the substrate (7) is a highly doped silicon wafer, a glass sheet or plastic PET.
The preparation method of the source-drain electrode (1) is a magnetron sputtering method, an ink-jet printing method or a vacuum evaporation method; the channel layer (2) is formed into a film by adopting a magnetron sputtering method; the tunneling insulating dielectric layer (3) is formed by adopting an atomic layer and PECVD deposition technology.
Further, a preparation method of the amorphous oxide floating gate transistor containing perovskite quantum dots comprises the following specific operation steps:
(1) preparing a perovskite quantum dot solution; the method comprises the following steps: selecting a proper organic solvent (preferably normal hexane), mixing perovskite quantum dots serving as solutes,
(2) sequentially forming a gate electrode (6) and a gate insulating layer (5) on a substrate (7) to prepare a substrate, and then cleaning and drying the substrate;
(3) the prepared perovskite quantum dot solution is spin-coated on a gate insulating layer (5) of a substrate, the spin-coating speed and time are controlled, the spin-coating speed is kept at 3000r/m, the spin-coating time is 40s, and the thickness of the perovskite quantum dot solution is kept at 5-20 nm, so that a perovskite quantum dot thin film layer (4) is formed;
(4) annealing a sample formed by the substrate (7), the gate electrode (6), the gate insulating layer (5) and the perovskite quantum dot thin film layer (4);
(5) then, depositing a tunneling insulating medium layer (3) on the annealed perovskite quantum dot thin film layer (4);
(6) and sputtering an indium gallium zinc oxide film channel layer (2) on the tunneling insulating medium layer (3) by using a mask, and evaporating a source drain electrode (1) in vacuum, thereby finally preparing the amorphous oxide floating gate transistor containing perovskite quantum dots.
Example 1
(1) Configuration CsPbBr3The preparation method comprises the following steps of (1) carrying out centrifugal purification on a quantum dot solution, wherein a solvent is n-hexane, and the concentration is 0.5mg/ml after the preparation is finished;
(2) preparing a 100-nanometer thick molybdenum (Mo) metal layer on a glass substrate by adopting a magnetron sputtering process, and preparing a patterned Mo bottom gate electrode by combining a photoetching process;
(3) then, a 30nm thick Si3N4 layer is deposited on the glass with the patterned Mo bottom electrode by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process as a gate insulating layer,
(4) and spin-coating CsPbBr configured in the step (1) on the insulated gate layer3And (3) maintaining the rotation speed of the quantum dot solution at 3000r/m, carrying out spin coating for 40s, and placing the spin-coated sample in a glove box for annealing at 120 ℃ for 40 min.
(5) Continuously depositing 10nm Al on the quantum dot thin film layer by using a PECVD method2O3As a tunneling insulating medium layer;
(6) and preparing an Indium Gallium Zinc Oxide (IGZO) channel layer on the tunneling insulating medium layer by combining magnetron sputtering and photoetching processes, wherein the target material is InGaZnO with In: Ga: Zn: 2:1:14The sputtering power is 100W, the plasma is Ar/O2The thickness is 15 nm;
(7) and preparing a patterned copper (Cu) source/drain electrode on the IGZO channel layer by combining magnetron sputtering and photoetching processes, wherein the thickness of the electrode is 120nm, the length of the channel of the floating gate IGZO transistor is 5 microns, and the width of the floating gate IGZO transistor is 20 microns.
Example 2
(1) Selecting conductive ITO glass as a substrate, wherein ITO is a gate electrode, depositing 30nm Si3N4 as a gate insulating layer on the ITO by using a PECVD method to prepare a substrate, sequentially ultrasonically cleaning the substrate for 10min by using acetone, ethanol and deionized water respectively, wherein the ultrasonic frequency is 100KHz, blowing off liquid on the surface of the substrate by using high-purity nitrogen, and then drying the substrate in a drying oven at 120 ℃;
(2) depositing a layer of perovskite Cs on the gate insulating layer of the substrate by adopting an electrostatic spraying technology2TeI6A quantum dot film;
(3) depositing 15nm Al2O3 on the quantum dot thin film layer by using an ALD method to serve as a tunneling insulating medium layer;
(4) sputtering an Indium Gallium Zinc Oxide (IGZO) thin film channel layer on the tunneling insulating medium layer by using a mask, wherein the target material is InGaZnO with In: Ga: Zn: 1:14Ceramic, sputtering power is 100W, plasma is Ar/O2The thickness is 25 nm;
(5) and depositing Al on the prepared IGZO channel layer as a source drain electrode by adopting magnetron sputtering and photoetching processes, and annealing for 30 minutes at 400 ℃. The floating gate IGZO transistor has a channel length of 10 microns and a width of 50 microns.
According to the invention, the perovskite quantum dot film is introduced into the memory, so that the incident light collection efficiency of the device is effectively improved, the photoelectric conversion efficiency is enhanced, the large current density and the excellent storage characteristic are realized, and the perovskite quantum dot film plays an important role in the aspects of nonvolatile memory, photosensitive memory, sensing and the like.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (9)

1. The amorphous oxide floating gate transistor containing perovskite quantum dots is characterized by comprising a substrate (7) at the bottom end, a gate electrode (6) is formed on the substrate (7), a gate insulating layer (5) is formed on the gate electrode (6), a floating gate layer (4) is formed on the gate insulating layer (5), a tunneling insulating layer (3) is formed on the floating gate layer (4), a channel layer (2) is formed on the tunneling insulating layer (3), and source and drain electrodes (1) are formed on the channel layer (2).
2. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the source and drain electrodes (1) are made of any one of Al, Cu and Ag, and the thickness of the source and drain electrodes is 20-200 nm.
3. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the channel layer (2) is made of an amorphous metal oxide indium gallium zinc oxide with a thickness of 10-50 nm.
4. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the tunneling insulating medium layer (3) is made of Al2O3、Si3N4、SiO2The thickness of the single-layer insulating film or the multi-layer insulating film composed of any two or more insulating films is 4 to 20 nm.
5. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the floating gate layer (4) is made of a perovskite quantum dot thin film, and the thickness of the perovskite quantum dot thin film is 5-20 nm.
6. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the gate insulating layer (5) is made of Al2O3、Si3N4、SiO2The single-layer insulating film or the multilayer insulating film comprising two or more kinds of insulating films has a thickness of 10 to 200 nm.
7. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, wherein the gate electrode (6) is an ITO transparent conductive film.
8. The amorphous oxide floating gate transistor containing perovskite quantum dots according to claim 1, characterized in that the substrate (7) is a highly doped silicon wafer, a glass sheet or a plastic PET.
9. The method for preparing an amorphous oxide floating gate transistor containing perovskite quantum dots according to claims 1 to 8, wherein the specific operation steps are as follows:
(1) preparing a perovskite quantum dot solution;
(2) sequentially forming a gate electrode (6) and a gate insulating layer (5) on a substrate (7) to prepare a substrate, and then cleaning and drying the substrate;
(3) the prepared perovskite quantum dot solution is spin-coated on a gate insulating layer (5) of the substrate, the spin-coating rotating speed is kept at 3000r/m, and the spin-coating time is 40s, so that a perovskite quantum dot thin film layer (4) is formed;
(4) annealing a sample formed by the substrate (7), the gate electrode (6), the gate insulating layer (5) and the perovskite quantum dot thin film layer (4);
(5) then, depositing a tunneling insulating medium layer (3) on the annealed perovskite quantum dot thin film layer (4);
(6) and sputtering an indium gallium zinc oxide film channel layer (2) on the tunneling insulating medium layer (3) by using a mask, and evaporating a source drain electrode (1) in vacuum, thereby finally preparing the amorphous oxide floating gate transistor containing perovskite quantum dots.
CN202111148165.XA 2021-09-29 2021-09-29 Preparation method of amorphous oxide floating gate transistor containing perovskite quantum dots Pending CN114093933A (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009582A (en) * 2019-12-22 2020-04-14 复旦大学 Photoelectric programming multi-state memory based on thin film transistor structure and preparation method thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111009582A (en) * 2019-12-22 2020-04-14 复旦大学 Photoelectric programming multi-state memory based on thin film transistor structure and preparation method thereof

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