CN114089150A - Semiconductor chip testing device and testing method - Google Patents
Semiconductor chip testing device and testing method Download PDFInfo
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- CN114089150A CN114089150A CN202110575844.9A CN202110575844A CN114089150A CN 114089150 A CN114089150 A CN 114089150A CN 202110575844 A CN202110575844 A CN 202110575844A CN 114089150 A CN114089150 A CN 114089150A
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- 238000012360 testing method Methods 0.000 title claims abstract description 192
- 239000004065 semiconductor Substances 0.000 title claims abstract description 106
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- 238000012937 correction Methods 0.000 claims description 30
- 238000004364 calculation method Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 238000012216 screening Methods 0.000 claims description 16
- 238000010998 test method Methods 0.000 claims description 2
- 238000012423 maintenance Methods 0.000 abstract description 9
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2601—Apparatus or methods therefor
Abstract
The invention provides a testing device and a testing method for a semiconductor chip, which can minimize the maintenance of a contact probe and a measuring table when the semiconductor chip is damaged. When the device under test is turned on, the drain-source voltage Vds decreases and the drain current Id increases. Next, if the device under test is turned off, the drain-source voltage Vds thereof sharply increases, and the drain current Id decreases. If there is a sharp change in the drain current Id while the drain current Id is decreasing, the device under test is determined to be defective. The energy applied to the damaged device under test is calculated. Only when the applied energy exceeds the set value, the test device is stopped and the contact probe or the measuring table, or both, are instructed to be replaced. This suppresses maintenance cost.
Description
Technical Field
The present invention relates to a semiconductor chip testing apparatus and a semiconductor chip testing method.
Background
Power devices such as MOSFETs (Metal Oxide Semiconductor Field Effect transistors) and/or IGBTs (Insulated Gate Bipolar transistors) are subjected to dynamic characteristic tests in the state of a Semiconductor wafer or a Semiconductor chip.
Fig. 12 is a diagram showing a measurement mechanism used in a conventional semiconductor chip test, and fig. 13 is a diagram showing a case where an adhering substance is generated in a contact probe by energy applied to a semiconductor chip after the semiconductor chip is broken by the test.
As shown in fig. 12, a test is performed on a device under test 100, which is a semiconductor chip, using a tester 101, a contact probe 102, a contact block 103 holding the contact probe 102, and a measurement stage 104. At this time, the device under test 100 is electrically connected to the tester 101 via the contact probes 102 and the measurement table 104, and is subjected to short-time electrical stress from the tester 101 to perform sorting of good products/defective products.
The tester 101 includes a semiconductor switch between a power supply and the device under test 100, and if the device under test 100 is broken during the test, the semiconductor switch is turned off to cut off the current flowing through the device under test 100. In this semiconductor switch, a discharge-blocking snubber circuit is used as a snubber circuit for absorbing a surge voltage generated at the time of turn-off (see, for example, patent document 1). Therefore, the current that continues to flow after the semiconductor switch is turned off can be reduced, and the damage of the device under measurement 100 and the damage of the contact probe 102 and the measurement table 104 can be suppressed, so that the maintenance cost can be reduced.
In the test of the device under test 100, as shown in fig. 13, the contact probe 102 is brought into contact with the electrode of the device under test 100 while applying a load to the electrode of the device under test 100, and a dynamic characteristic test is performed. Here, if a current that would damage the device under test 100 flows during the test, a foreign substance 105 that is a melted component of the device under test 100 (silicon in the case of a silicon device) may adhere to the contact probe 102. Such foreign matter 105 may adhere to not only the contact probe 102 but also the measurement table 104.
If a foreign object 105 adheres to the contact probe 102 and the measurement table 104, the foreign object 105 gives physical damage to the device under test 100 to be tested next, and a normal test cannot be performed because the foreign object 105 exists in the test circuit. Therefore, when the device under test 100 is damaged, the test of the tester 101 needs to be interrupted and the contact probes 102 and the measurement stage 104 need to be inspected.
In contrast, a technique for automating inspection when a device is broken has been proposed (for example, see patent document 2). According to the technique of patent document 2, when a semiconductor chip is damaged, first, a distance between a damage trace formed on an upper electrode of the semiconductor chip and a pressure contact trace of a contact probe is measured from image information of the semiconductor chip. Then, it is determined whether the distance is equal to or less than a determination reference distance (for example, 0.5 mm), and maintenance of the contact probe is performed only when the distance is equal to or less than the determination reference distance. Thus, the time for stopping the test apparatus can be shortened and the maintenance cost can be reduced, as compared with the case where the contact probe is maintained every time the semiconductor chip is damaged.
Documents of the prior art
Patent document
Patent document 1: japanese patent laid-open publication No. 2013-92534
Patent document 2: japanese patent laid-open publication No. 2010-276477
Disclosure of Invention
Technical problem
However, even in the case of using a discharge prevention type snubber circuit as a snubber circuit that absorbs a surge voltage generated when the semiconductor switch is turned off, damage due to a current that continues to flow after breakdown cannot be completely suppressed. In addition, in the technology of determining whether or not the contact probe needs to be maintained by image processing of the semiconductor chip, there is a problem that the system becomes complicated.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor chip testing apparatus and a semiconductor chip testing method which minimize maintenance of a contact probe and a measuring table when a damage of a semiconductor chip occurs.
Technical scheme
In the present invention, in order to solve the above-described problems, in one aspect, a semiconductor chip testing apparatus for a screening test of a semiconductor chip of a power device which may cause chip damage is provided. The semiconductor chip testing apparatus stops the testing apparatus when the applied energy applied to the semiconductor chip with chip damage caused by the screening test is more than a set value.
In addition, the present invention provides a test method of a semiconductor chip for a screening test of a semiconductor chip of a power device which may cause chip damage. The semiconductor chip testing method includes the steps of judging the semiconductor chip as bad when the chip damage occurs in the semiconductor chip due to screening test, and calculating the applied energy applied to the semiconductor chip; determining whether or not the value of the applied energy is equal to or greater than a set value; and instructing the test apparatus to stop when the value of the applied energy is determined to be equal to or greater than the set value.
Technical effects
The semiconductor chip testing apparatus and the semiconductor chip testing method having the above-described configuration have an advantage that the apparatus stop time for the maintenance can be shortened and the manufacturing cost associated with the apparatus stop time can be reduced because the maintenance after the chip breakage can be reduced.
Drawings
Fig. 1 is a diagram illustrating a test apparatus for an inductive load avalanche tolerance test according to an embodiment of the present invention.
Fig. 2 is a block diagram showing an example of the configuration of the tester.
Fig. 3 is a diagram illustrating a handler that transports semiconductor chips.
Fig. 4 is a flowchart illustrating the flow of the operation of the test apparatus.
Fig. 5 is a graph showing the time-dependent changes in the drain-source voltage and the drain current of the device under test measured during the test.
Fig. 6 is a graph showing a relationship between energy after damage and damage to the measurement stage and the contact probe.
Fig. 7 is a schematic diagram of a power device, where (a) is a plan view showing a main part of a semiconductor chip, (b) is a sectional view taken along the line a-a of (a), and (c) is a diagram showing a main part of a finished product in which a device to be measured is assembled.
Fig. 8 is a graph showing a change in temperature of a device under measurement with respect to energy applied for an avalanche test.
Fig. 9 is a diagram showing a relationship between the avalanche resistance inherent in the device and the temperature.
Fig. 10 is a diagram illustrating timings at which temperature sensing voltages of the temperature sensing diodes are sampled.
Fig. 11 is a diagram illustrating current correction due to a difference in thermal resistance of applied energy.
Fig. 12 is a diagram showing a measurement mechanism used in a conventional semiconductor chip test.
Fig. 13 is a diagram showing a case where an adhering substance is generated at the contact probe by energy applied to the semiconductor chip after the semiconductor chip is broken by the test.
Description of the symbols
1: a device under test; 2: a semiconductor chip; 2 a: a semiconductor substrate; 2 b: a drain electrode; 2 c: a source electrode; 2 g: a gate electrode; 2 h: an anode electrode; 2 i: a cathode electrode; 2 j: a protective film; 3: a temperature sensing diode; 5: an insulating substrate; 6: wiring; 7: welding flux; 8: a wire; 11: a gate driving unit; 12: an ammeter; 13: an inductor; 14: a power source; 15: a capacitor; 16: a voltmeter; 17: a current source; 18: a voltmeter; 19: a tester; 20: an input section; 20 a: an acquisition unit; 21: a storage unit; 22: a digitizer; 23: an output section; 24: a display unit; 25: a processor; 26: a conveying section; 27: a measurement section; 28: an adsorption chuck; 29: a chip tray; 30: a measuring table; 31: an adsorption chuck; 32. 33: a chip tray; 41: a calculation unit; 41 a: a damage determination section; 41 b: an energy calculation unit; 41 c: a judgment unit for judging whether replacement is required; 41 d: correction value calculating section
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example a case where the present invention is applied to an inductive load avalanche tolerance test as a screening test for a semiconductor chip of a power device which may cause chip damage. In the drawings, the same components are denoted by the same reference numerals.
Fig. 1 is a diagram illustrating a test apparatus for an inductive load avalanche tolerance test according to an embodiment of the present invention, fig. 2 is a block diagram showing an example of a configuration of a tester, and fig. 3 is a diagram illustrating a handler that transports a semiconductor chip.
The test apparatus shown in fig. 1 is an apparatus for performing an inductive load avalanche tolerance test of a power device as a device under test 1. The device under test 1 shown in the figure has a temperature sensing diode 3 for temperature detection built in a semiconductor chip 2 of a MOSFET, and has a gate terminal G, a drain terminal D, a source terminal S, an anode terminal a, and a cathode terminal K.
In the present embodiment, the temperature sensing diode 3 as a temperature detection element is incorporated in the semiconductor chip 2, but is not necessarily incorporated in the semiconductor chip 2. In addition, the temperature detection element may be disposed in the test apparatus without being disposed in the device under test 1.
As shown in fig. 2, the tester 19 includes a digitizer 22, a current meter 12, an inductor 13, a power supply 14, a capacitor 15, a voltmeter 16, a current source 17, a voltmeter 18, and a Gate Drive Unit (GDU) 11.
The gate terminal G of the device under test 1 is connected to the output terminal of the gate driving unit 11, and the low potential terminal of the gate driving unit 11 is connected to the source terminal S of the device under test 1. The device under measurement 1 has a drain terminal D connected to the negative terminal of the ammeter 12, a positive terminal of the ammeter 12 connected to one terminal of an inductor 13 as an inductive load, and the other terminal of the inductor 13 connected to the positive terminal of the variable voltage power supply 14 and the positive terminal of the capacitor 15. The drain terminal D of the device under measurement 1 is connected to the positive terminal of the voltmeter 16, and the negative terminal of the voltmeter 16 is connected to the source terminal S of the device under measurement 1. The anode terminal a of the device under test 1 is connected to the output terminal of the current source 17 and the positive terminal of the voltmeter 18, and the other terminal of the current source 17 and the negative terminal of the voltmeter 18 are connected to the cathode terminal K of the device under test 1.
The current meter 12 measures the drain current Id of the device under test 1, and the measurement result is sent to the digitizer 22. The voltmeter 16 measures the drain-source voltage Vds of the device under test 1, and the measurement result is transmitted to the digitizer 22. The voltmeter 18 measures a forward voltage of the temperature sensing diode 3, i.e., the temperature sensing voltage VF, which is constant-current driven by the current source 17, and the measurement result thereof is transmitted to the digitizer 22. The temperature sensing diode 3 has a temperature coefficient, and the measured temperature sensing voltage VF is temperature information of the device under measurement 1.
In the test apparatus, the drain terminal D of the device under test 1 and the ammeter 12 are electrically connected to each other through the measurement stage. The electrical connection between the gate terminal G of the device under test 1 and the gate driving unit 11, the electrical connection between the source terminal S of the device under test 1 and the power supply 14, and the electrical connection between the anode terminal a and the cathode terminal K of the device under test 1 and the current source 17 and the voltmeter 18 are performed by contact probes, respectively. The contact probes are the same as in fig. 12, the contact probes being held by the contact block.
As shown in fig. 2, the digitizer 22 includes an input unit 20, a storage unit 21, an arithmetic unit 41, an output unit 23, and a display unit 24. The input unit 20 includes an acquisition unit 20a, and the calculation unit 41 includes a damage determination unit 41a, an energy calculation unit 41b, a replacement necessity determination unit 41c, and a correction value calculation unit 41 d. The correction value calculation unit 41d is provided as necessary. In the case where the correction value calculation section 41d is not provided, in the case where the correction value is used, the correction value calculated outside the apparatus is input from the input section 20 and stored in the storage section 21.
In the input unit 20, the acquisition unit 20a acquires a current value (drain current Id) from the ammeter 12, a voltage value (drain-source voltage Vds) from the voltmeter 16, and a voltage value (temperature sensing voltage VF of the temperature sensing diode 3) from the voltmeter 18. The avalanche energy and the thermal resistance Rth obtained by analyzing the completed product in which the device under measurement 1 is assembled in advance are input to the acquisition unit 20a of the input unit 20. When the correction value calculation unit 41d is not provided, it may not be input.
The storage unit 21 stores each measured value, a set value used in the necessity/unnecessity replacement determination unit 22c, and a temperature and avalanche energy acquired in advance for calculating a correction value due to a difference in thermal resistance, as necessary.
The damage determination unit 41a of the calculation unit 41 determines that the device under measurement 1 is damaged when the acquired current value (drain current Id) changes rapidly. When it is determined that the device under test is broken, the energy calculation unit 41b calculates the energy applied to the device under test 1 after the test is completed. The replacement necessity determining unit 41c determines whether or not the energy calculated by the energy calculating unit 41b is a set value such that the measuring table and the contact probe need to be replaced. The correction value calculation unit 41d calculates a correction value to be passed through the device under measurement 1 so as to match the conditions of the measurement system with the conditions of the finished product.
The output unit 23 is connected to the processor 25, and instructs sorting of the device under measurement 1 or outputs an end of measurement or the like based on the determination result of the damage determination unit 41 a. The output unit 23 also corrects the value of the current or voltage applied to the device under measurement 1 by the gate driving unit 11 or the power supply 14 based on the calculation result of the correction value calculating unit 41 d. The display unit 24 displays the operation state of the digitizer 22 including an alarm notification when the device under test 1 is damaged.
As shown in fig. 3, the handler 25 includes a conveying section 26 and a measuring section 27, and an adsorption chuck 28 takes out the device under measurement 1 stored in a chip tray 29 in the conveying section 26 and conveys the device under measurement to a measuring table 30 of the measuring section 27. The transport unit 26 also picks up the device under measurement 1 after the measurement by the suction chuck 31, and transports the device under measurement 1 to the chip tray 32 for good products or the chip tray 33 for defective products based on the measurement result.
Next, a procedure for performing an inductive load avalanche tolerance test of the device under measurement 1 will be described with reference to a test apparatus shown in fig. 1.
Fig. 4 is a flowchart illustrating the flow of the operation of the test apparatus, fig. 5 is a graph showing the changes with time of the drain-source voltage and the drain current of the device under test measured at the time of the test, and fig. 6 is a graph showing the relationship between the energy after the damage and the damage to the measurement stage and the contact probe.
First, in the inductive load avalanche resistance test of the device under measurement 1, the device under measurement 1 is conveyed from the chip tray 29 to the measurement table 30 of the measurement unit 27 in the handler 25 (step S1), and the contact probe is brought into contact with the device under measurement 1 (step S2).
Next, the voltage of the power supply 14 is raised to a predetermined voltage and applied to the device under test 1 (step S3). At this time, as shown in fig. 5, the drain-source voltage Vds is applied to the drain terminal D and the source terminal S of the device under test 1, and the drain current Id becomes 0 ampere (a) because the device under test 1 is off.
Next, the gate driving unit 11 outputs a pulse signal to be applied to the gate terminal G of the device under test 1, thereby starting switching of the device under test 1 (step S4). When the device under test 1 is turned on, the drain-source voltage Vds decreases to a value close to 0 volt (V), and the drain current Id gradually increases due to the inductor 13. At this time, energy is accumulated in the inductor 13. Then, if the device under test 1 is turned off, the energy stored in the inductor 13 suddenly flows between the drain and the source of the device under test 1, so that the drain-source voltage Vds rises in a step manner, and the drain current Id gradually decreases.
Then, the drain current Id measured by the ammeter 12 and the drain-source voltage Vds measured by the voltmeter 16 are acquired by the digitizer 22 and stored in the storage unit 21 (step S5).
Next, the breakdown determination unit 41a of the calculation unit 41 analyzes the waveform of the drain current Id sampled after the device under test 1 is turned off, and determines whether or not the device under test 1 is broken (step S6). The damage determination unit 41a determines that the inductive load avalanche tolerance test of the device under test 1 is acceptable when the drain current Id gradually decreases to 0A after the device under test 1 is turned off. When the drain current Id that gradually decreases rapidly increases as shown in fig. 5 after the device under measurement 1 is turned off, the damage determination unit 41a determines that the device under measurement 1 is damaged.
Next, it is determined whether or not the measurement device 1 is defective as a result of the determination by the damage determination section 41a (step S7). The damaged determination unit 41a determines that the damaged device under measurement 1 is defective. If the device under test 1 is defective, the process proceeds to step S8, and if the device under test 1 is not defective, the process proceeds to step S12.
If the device under measurement 1 is determined to be defective, the energy calculation unit 41b of the calculation unit 41 performs the energy analysis after damage (step S8). As shown in fig. 5, the energy analysis is performed during a period from after the breakdown (hereinafter, also referred to as a time point at which the drain current Id instantaneously increases) until the drain current Id oscillates and decreases to substantially 0A, and the applied energy after the breakdown is calculated by time integration of the product of the drain-source voltage Vds and the drain current Id. Although it is desirable that the start time point of the application of energy is calculated from after the damage, it may be started not from after the damage but from a time point at which the pulse signal starts to be applied to the gate terminal G of the semiconductor chip 2.
Next, the replacement necessity determining unit 41c of the computing unit 41 determines whether or not the energy applied to the device under measurement 1 after the damage of the device under measurement 1 is equal to or greater than a set value (step S9). Here, the set value is determined using a case where there is a certain relationship between the post-damage energy and the device damage (damage track depth and damage track width) in the measurement system used as shown in fig. 6. That is, the relationship between the post-damage energy and the device damage is analyzed in advance, and the post-damage energy at the time when the device damage starts to occur is set as a set value. Therefore, if the energy after the damage is equal to or more than the set value, it is determined that there is damage to the measurement table 30 and the contact probe due to the damage of the device under test 1, and the process proceeds to step S10. If the energy after damage is less than the set value, it is determined that there is no damage to the measurement table 30 and the contact probe due to the damage even if the device under test 1 is damaged, and the process proceeds to step S12.
In fact, in many cases, the energy after damage is different between when the measurement table 30 and the contact probe are damaged due to damage of the device under measurement 1, and generally, the set value of the contact probe for determining whether replacement is necessary is smaller than the set value of the measurement table 30 for determining whether replacement is necessary. Therefore, the first set value for the contact probe and the second set value for the measurement stage 30 are prepared, and when the calculated energy after damage is equal to or more than the first set value and less than the second set value, it is possible to instruct to replace only the contact probe. When the calculated energy after damage is equal to or more than the second set value, the replacement of the measurement table 30 and the contact probe may be instructed. Rarely, depending on the type of damage, only the measurement table 30 may be replaced.
Next, when the digitizer 22 determines that the device under test 1 is damaged and damages are caused to the measurement table 30 and the contact probes, the processor 25 is instructed to transfer the damaged device under test 1 to the defective chip tray 33 (step S10). In this example, the defective chip tray 33 is used, but the chip tray may not be used.
Next, the digitizer 22 notifies the measurement table 30 and the contact probe to be replaced by the device alarm and instructs the processor 25 (step S11), and thereafter, the process returns to step S1.
When it is determined at step S7 that the device under test 1 is not defective or it is determined at step S9 that the energy applied to the device under test 1 is not equal to or greater than the set value, the device under test 1 having completed the test is transferred to the chip tray 32 or 33 (step S12), and the process returns to step S1.
The testing apparatus determines whether or not the measurement stage 30 and the contact probe need to be replaced, based on the amount of energy applied after the device under test 1 is damaged. Therefore, when damage to the device is small, the number of maintenance steps can be reduced, and thus the throughput of chip manufacturing can be increased, and the manufacturing cost associated therewith can be reduced.
Next, in a screening test for possible damage to the device under test 1, a test adapted to the actual use of the device under test 1 will be discussed. That is, in the case where the device under test 1 is tested in a chip state and the case where the device under test 1 is tested in an assembled finished product state, even if the tests are performed under the same temperature conditions, the test results may be different.
Fig. 7 is a schematic diagram of a power device, in which (a) is a plan view showing a main part of a semiconductor chip, (b) is a cross-sectional view taken along the line a-a of (a), and (c) is a diagram showing a main part of a finished product in which a device to be measured is assembled.
As shown in fig. 7 (a) and 7 (b), the semiconductor chip 2 has a drain electrode 2b disposed on one surface of a semiconductor substrate 2a and a source electrode 2c disposed on the other surface. On the other surface, a gate electrode 2g, an anode electrode 2h, and a cathode electrode 2i are arranged. The temperature sensing diode 3 is provided in an insulating film, not shown, below the protective film 2j and on the semiconductor substrate 2 a. As shown in fig. 7 (c), the wiring 6 provided on the insulating substrate 5 and the drain electrode 2b of the semiconductor chip 2 are electrically connected by solder 7. The source electrode 2c of the semiconductor chip 2 and the like are bonded to the wire 8 by wire bonding. The drain electrode 2b of the semiconductor chip 2 may have a laminated layer of a layer containing Ni as a main component and an Au layer disposed on the outermost surface in consideration of the bondability to the solder 7. The source electrode 2c of the semiconductor chip 2 may have a layer containing Al as a main component disposed on the outermost surface. The same layer as the drain electrode 2b may be disposed on the outermost surface. When a laminated layer of a layer containing Ni as a main component and an Au layer is disposed on the outermost surface of the source electrode 2c, the source electrode 2c and a lead frame or the like may be electrically connected by solder.
Fig. 8 is a diagram showing a change in temperature of a device under measurement with respect to energy applied for an avalanche test, and fig. 9 is a diagram showing a relationship between an avalanche resistance inherent to the device and temperature.
Fig. 8 shows that the temperature rise of the device under measurement 1 in the state where the completed product of the device under measurement 1 is assembled is lower than the temperature rise of the device under measurement 1 in the chip state in the temperature rise of the device under measurement 1 in the avalanche test. This is considered to be because, in the chip state, the contact resistance between the device under measurement 1 and the measurement stage 30 and the contact probe is large, and the heat dissipation through the measurement stage 30 and the contact probe is poor, resulting in large thermal resistance. On the other hand, in the state where the device under test 1 is completed, electrical connection between the device under test 1 and the bonding wire and the printed board is mainly made by solder, so that contact resistance is small, heat dissipation is also good, and thermal resistance is small.
As shown in fig. 9, the device under measurement 1 tends to have a higher avalanche resistance if the temperature is low and a lower avalanche resistance as the temperature becomes higher. This indicates that the avalanche resistance also changes if the temperature of the device under measurement 1 changes in the avalanche test.
Since the avalanche resistance test in the chip state is also affected by thermal resistance as described above, if the heat dissipation characteristics change due to the material of the measurement stage 30, the design of the suction holes, the material, layout, and/or load of the contact probes on the upper surface, the amount of target energy for the finished product varies. For example, as shown in fig. 8, it is intended to apply energy of 1.0 joule (J) as the measurement condition, but actually, the temperature rise in the chip state is large, and a test is performed under a condition corresponding to the energy applied of 1.0J or more. However, since the avalanche resistance to the temperature rise depends on the device under measurement 1, it is necessary to optimally adjust the conditions corresponding to the thermal resistance of the measurement system.
Therefore, the test apparatus includes a current source 17 and a voltmeter 18 for measuring the temperature of the device under measurement in the measurement unit. This can obtain the thermal resistance of the semiconductor chip 2 in the avalanche resistance test.
A specific method of calculating the thermal resistance will be described below.
First, using the device under measurement 1 assembled in a finished product, the temperature dependence of the avalanche capability corresponding to the device as shown in fig. 9 is analyzed in advance, an avalanche capability test is performed on a plurality of devices under measurement 1 based on the target avalanche capability of the finished product obtained thereby, the temperature of the device under measurement 1 at that time and the applied avalanche energy are acquired, and the thermal resistance is calculated.
Next, based on the thermal resistance of the measurement system, an avalanche resistance test is performed on the plurality of devices under measurement 1 in the chip state based on the same applied voltage and pulse signal as the avalanche energy applied by the avalanche resistance test of the completed product, the drain current Id measured by the ammeter 12, the drain-source voltage Vds measured by the voltmeter 16, and the temperature sensing voltage VF of the temperature sensing diode 3 measured by the voltmeter 18 are obtained, and the thermal resistance is calculated from the temperature and the applied avalanche energy.
Fig. 10 is a diagram illustrating timing at which a temperature sensing voltage of a temperature sensing diode is sampled, and fig. 11 is a diagram illustrating current correction due to a difference in thermal resistance of applied energy.
To determine the thermal resistance of the measurement system, as shown in fig. 10, the pre-measurement temperature sensing voltage VF 1V and the post-measurement temperature sensing voltage VF 2V of the avalanche test are first obtained, and the difference between them is calculated. Next, the product of the drain-source voltage Vds [ V ] and the drain current Id [ a ] is taken as P [ W ] to calculate the thermal resistance Rth [ ° c/W ] (VF1-VF2)/P, while obtaining the temperature sensing voltage VF2[ V ].
Next, calculation of a correction value for optimum adjustment based on a condition corresponding to the thermal resistance of the measurement system will be described. The relationship between the avalanche capability of the device under measurement 1 and the thermal resistance has a relationship shown by a broken line in fig. 11, and the avalanche capability can be made larger as the thermal resistance Rth is smaller. Here, since the avalanche resistance and the thermal resistance of the finished product are measured in advance, the avalanche resistance can be known when the finished product is under the same temperature condition as the finished product. From the relationship between the avalanche resistance and the thermal resistance of the device under measurement 1 at this time, the avalanche resistance corresponding to the thermal resistance calculated before is obtained as a chip condition, and a correction value for the test condition based on the measurement system in the chip state is obtained so as to correspond to the avalanche resistance at that time. The correction value may be stored in the storage section 21, for example. The correction value may be a current value or a voltage value.
The correction value can be calculated by the correction value calculation unit 41 d. In this case, for example, the applied avalanche energy and thermal resistance derived from the target avalanche resistance of the completed product are input to the digitizer 22. The avalanche energy may be set as test conditions of the voltage applied to the device under test 1 and the pulse signal width. Then, as described above, the thermal resistance in the chip state is calculated, and the correction value is calculated by the correction value calculation unit 41 d. In the case where the correction value is a current value, it is transmitted to the gate driving unit 11, shortening the width of the pulse signal. In the case where the correction value is a voltage value, it is transmitted to the power supply 14, and the power supply 14 reduces the voltage applied between the drain and the source. Thus, the device under test 1 performs the avalanche test under the chip condition of the low correction value corresponding to the target value of the finished product, and therefore, excessive energy is not applied.
When the correction value calculating unit 41d is not provided, the avalanche energy applied to the completed product is input to the digitizer 22, the thermal resistance in the measurement system is calculated and output, the correction value is calculated from the thermal resistance of the completed product and the thermal resistance of the measurement system, and the correction value or the avalanche energy applied to the measurement system is input to the digitizer 22.
Accordingly, since the applied energy can be reduced when the test is performed under the same temperature condition as the state of the completed product in which the device under test 1 is assembled, it is possible to reduce the occurrence of defective products without applying excessive energy as a screening test.
In the present embodiment, a case where a singulated semiconductor chip is used as the device under test 1 is described. However, the screening test of the semiconductor chips may be performed in a state of the semiconductor wafer before singulation.
Claims (17)
1. A test apparatus for a semiconductor chip is characterized in that,
in a test apparatus for screening tests on a semiconductor chip of a power device which may cause chip damage,
the testing apparatus is stopped when the energy applied to the semiconductor chip, which has been damaged by the screening test, is equal to or greater than a predetermined value.
2. A test apparatus for a semiconductor chip, which is used for a screening test for a semiconductor chip of a power device, which may cause chip damage, is characterized by comprising:
a damage determination unit that determines whether or not the chip damage occurs in the semiconductor chip due to the screening test;
an energy calculation unit that receives the information that the chip is determined to be damaged by the damage determination unit and calculates an application energy to be applied to the semiconductor chip; and
and a determination unit that determines whether or not the value of the applied energy calculated by the energy calculation unit is equal to or greater than a set value.
3. The semiconductor chip test apparatus according to claim 2,
the testing apparatus further includes a stop instruction unit that instructs the testing apparatus to stop in order to replace a contact probe that electrically contacts the semiconductor chip when the value of the applied energy is equal to or greater than the set value.
4. The semiconductor chip test apparatus according to claim 2,
the test apparatus further includes a stop instruction unit that instructs the test apparatus to stop in order to replace the measurement table in electrical contact with the semiconductor chip when the value of the applied energy is equal to or greater than the set value.
5. The semiconductor chip test apparatus according to claim 2,
the energy calculation unit calculates the value of the applied energy from a time integral of a product of a voltage and a current applied to the semiconductor chip.
6. The semiconductor chip testing apparatus according to any one of claims 2 to 5,
the applied energy is calculated by calculating the applied energy after the chip is damaged.
7. The semiconductor chip test apparatus according to claim 6,
the set value is determined based on a relationship between the damage to the semiconductor chip and the magnitude of the energy applied after the damage, which is analyzed in advance.
8. The semiconductor chip test apparatus according to claim 2,
the semiconductor chip testing device is provided with a processor, wherein the processor conveys the semiconductor chip to a measuring part during the screening test, and conveys the semiconductor chip in the measuring part to a good product tray according to the judgment result of the damage judging part after the screening test is finished.
9. The semiconductor chip test apparatus according to claim 2,
the semiconductor device further includes a correction value calculation unit that calculates a correction value for the avalanche energy in the measurement system, which is equivalent to the avalanche energy of the completed product, based on the thermal resistance of the completed product in the avalanche resistance test of the completed product in which the semiconductor chip is mounted and the thermal resistance in the measurement system when the semiconductor chip is tested with the avalanche energy in the avalanche resistance test of the completed product in the test apparatus.
10. A method for testing a semiconductor chip,
in a test method of a semiconductor chip for a screening test of a semiconductor chip of a power device which may cause chip damage, comprising:
determining that the semiconductor chip is defective and calculating an application energy applied to the semiconductor chip when the chip damage occurs in the semiconductor chip due to the screening test;
determining whether or not the value of the application energy is equal to or greater than a set value; and
and instructing the test apparatus to stop when it is determined that the value of the applied energy is equal to or greater than the set value.
11. The method for testing a semiconductor chip according to claim 10,
further comprising the step of replacing the contact probe and restarting the test after the test apparatus is stopped.
12. The method for testing a semiconductor chip according to claim 10,
further comprising the step of replacing the measuring table and restarting the test after the test apparatus is stopped.
13. The method for testing a semiconductor chip according to any one of claims 10 to 12,
the applied energy is calculated from a time integral of a product of a voltage and a current applied to the semiconductor chip.
14. The method for testing a semiconductor chip according to claim 10,
the applied energy is calculated by calculating the applied energy after the chip is damaged.
15. The method for testing a semiconductor chip according to claim 14,
the set value is determined based on a relationship between the damage to the semiconductor chip and the magnitude of the energy applied after the damage, which is analyzed in advance.
16. The method for testing a semiconductor chip according to claim 10,
the method further includes a step of calculating a correction value for the avalanche energy in the measurement system, which is equivalent to the avalanche energy of the completed product, from the thermal resistance of the completed product in the avalanche resistance test of the completed product in which the semiconductor chip is assembled and the thermal resistance in the measurement system when the semiconductor chip is tested with the avalanche energy in the avalanche resistance test of the completed product in the test apparatus.
17. The method for testing a semiconductor chip according to claim 10,
the method further includes a step of calculating avalanche energy in the measurement system corresponding to avalanche energy of the completed product, based on thermal resistance of the completed product in an avalanche resistance test of the completed product in which the semiconductor chip is assembled, and thermal resistance in the measurement system when the semiconductor chip is tested in the test apparatus at avalanche energy in the avalanche resistance test of the completed product.
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