CN114078746A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

Info

Publication number
CN114078746A
CN114078746A CN202010809812.6A CN202010809812A CN114078746A CN 114078746 A CN114078746 A CN 114078746A CN 202010809812 A CN202010809812 A CN 202010809812A CN 114078746 A CN114078746 A CN 114078746A
Authority
CN
China
Prior art keywords
forming
dielectric layer
semiconductor structure
trench
metal connecting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010809812.6A
Other languages
Chinese (zh)
Inventor
江涛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd
Original Assignee
Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd filed Critical Zhongxin Nanfang Integrated Circuit Manufacturing Co ltd
Priority to CN202010809812.6A priority Critical patent/CN114078746A/en
Publication of CN114078746A publication Critical patent/CN114078746A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The application provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein a first dielectric layer and a metal connecting structure penetrating through the first dielectric layer are formed on the substrate; forming a second dielectric layer on the surface of the first dielectric layer and the surface of the metal connecting structure; forming a groove in the second dielectric layer, wherein the groove exposes the surface of the metal connecting structure; cleaning the trench using an alkaline cleaning solution; and passivating the exposed surface of the metal connecting structure. According to the forming method of the semiconductor structure, the groove is cleaned by using an alkaline solution, and the metal connecting structure is not corroded or damaged; furthermore, after cleaning, the metal connecting structure is passivated to protect, so that the reliability of the device can be improved.

Description

Method for forming semiconductor structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor structure.
Background
As the fabrication of integrated circuits moves to ultra large scale integrated circuits (ULSI), the density of circuits inside the integrated circuits increases, and the number of devices included in the integrated circuits increases, so that the surface of the wafer cannot provide enough area to fabricate the required interconnections. In order to meet the demand of increased interconnection lines after the shrinking of elements, the design of a multilayer metal interconnection structure with more than two layers by using a metal connection structure and a through hole becomes a method which is necessary to be adopted by the ultra-large-scale integrated circuit technology.
In the back end of the semiconductor device fabrication process, a metal interconnection structure formation process is usually required. The metal interconnect structure formation process is typically performed on a semiconductor substrate, which typically has an active region on which semiconductor devices such as transistors and capacitors are formed. In a metal interconnect structure, there may be multiple layers of metal plugs and metal interconnect lines. When a next metal plug or metal interconnection line is formed on a previous metal plug or metal interconnection line, it is usually necessary to form an interlayer dielectric layer on the previous metal plug or metal interconnection line, then form a via (via) and a trench (trench) in the interlayer dielectric layer, and finally fill the via and the trench with metal to form the next metal plug or metal interconnection line.
However, in the cleaning process after the via and the trench are formed, the cleaning solution may corrode and damage the previous metal plug or metal interconnection line, which affects the reliability of the device. Therefore, there is a need to provide more efficient and reliable solutions.
Disclosure of Invention
The application provides a method for forming a semiconductor structure, which can avoid corroding or damaging a metal connecting structure when a groove is cleaned, and improve the reliability of a device.
The application provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate, wherein a first dielectric layer and a metal connecting structure penetrating through the first dielectric layer are formed on the substrate; forming a second dielectric layer on the surface of the first dielectric layer and the surface of the metal connecting structure; forming a groove in the second dielectric layer, wherein the groove exposes the surface of the metal connecting structure; cleaning the trench using an alkaline cleaning solution; and passivating the exposed surface of the metal connecting structure.
In some embodiments of the present application, the time for cleaning the trench using the alkaline cleaning solution is 1 minute to 2 minutes.
In some embodiments of the present application, the alkaline cleaning solution has a pH greater than 7 and less than 8.
In some embodiments of the present application, the alkaline solution comprises ammonia.
In some embodiments of the present application, the passivation process comprises: and passivating the exposed surface of the metal connecting structure by using a reducing gas.
In some embodiments of the present application, the passivation process comprises: the semiconductor structure is placed in a reaction apparatus filled with a mixed gas containing nitrogen and hydrogen to perform a passivation process.
In some embodiments of the present application, the mixed gas contains nitrogen in an amount of 40% to 60% and hydrogen in an amount of 40% to 60%.
In some embodiments of the present application, the method further comprises: the trench is cleaned using deionized water.
In some embodiments of the present application, the method further comprises: the trench was cleaned using EKC solution.
In some embodiments of the present application, the method further comprises: and forming an interlayer connection structure in the groove.
According to the forming method of the semiconductor structure, the groove is cleaned by using an alkaline solution, and the metal connecting structure is not corroded or damaged; furthermore, after cleaning, the metal connecting structure is passivated to protect, so that the reliability of the device can be improved.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present application, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
fig. 1 is a flow chart of a method of forming a semiconductor structure according to an embodiment of the present disclosure;
fig. 2 to 5 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
In some methods for forming a semiconductor structure, an acidic cleaning solution including hydrofluoric acid is usually used to clean a trench in a cleaning process after the trench is formed, however, the acidic solution may corrode and damage a previous metal connection structure to generate metal ions, which may further cause a galvanic reaction to damage the previous metal connection structure, thereby affecting device reliability.
In view of the above problems, the present application provides a method for forming a semiconductor structure, which uses an alkaline solution to clean the trench without corroding or damaging the metal connection structure; furthermore, after cleaning, the metal connecting structure is passivated to protect, so that the reliability of the device can be improved.
Fig. 1 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Referring to fig. 1, the present application provides a method of forming a semiconductor structure, the method comprising:
step S110: providing a substrate, wherein a first dielectric layer and a metal connecting structure penetrating through the first dielectric layer are formed on the substrate;
step S120: forming a second dielectric layer on the surface of the first dielectric layer and the surface of the metal connecting structure;
step S130: forming a groove in the second dielectric layer, wherein the groove exposes the surface of the metal connecting structure;
step S140: cleaning the trench using an alkaline cleaning solution;
step S150: and passivating the exposed surface of the metal connecting structure.
In the method for forming the semiconductor structure, the groove is cleaned by using an alkaline solution, so that the metal connecting structure is not corroded or damaged; furthermore, after cleaning, the metal connecting structure is passivated to protect, so that the reliability of the device can be improved.
Fig. 2 to 5 are schematic structural views of steps in a method for forming a semiconductor structure according to an embodiment of the present disclosure. The method for forming the semiconductor structure according to the present application is further described in detail below with reference to the accompanying drawings.
Referring to fig. 2, in step S110, a substrate 200 is provided, and a first dielectric layer 210 and a metal connection structure 220 penetrating through the first dielectric layer 210 are formed on the substrate 200.
In some embodiments of the present application, the substrate 200 includes, but is not limited to, a semiconductor substrate in which active devices (not shown) such as source, drain, or gate structures, etc. may be formed.
In some embodiments of the present application, the substrate 200 may also include a semiconductor substrate and a metal interconnection structure on the surface of the semiconductor substrate.
In some embodiments of the present disclosure, the method for forming the first dielectric layer 210 includes a chemical vapor deposition process or a physical vapor deposition process. The material of the first dielectric layer 210 includes silicon oxide, etc.
In some embodiments of the present application, the metal connection structure 220 is electrically connected to active devices (not shown) in the substrate 220, such as source, drain or gate structures. In other embodiments of the present application, the metal connection structure 220 may also be a metal interconnection structure electrically connecting the front layers.
In some embodiments of the present application, the metal connection structure 220 may be a first layer of metal interconnect structure on the substrate 200; in other embodiments of the present application, the metal connection structure 220 may also be a second layer or a third layer metal interconnection structure.
In some embodiments of the present application, the metal connection structure 220 is rectangular in cross-sectional view. In other embodiments of the present application, the cross-sectional view of the metal connection structure 220 may be in other patterns, such as a T-like shape.
In some embodiments of the present application, the material of the metal connection structure 220 includes copper.
Referring to fig. 3, in step S120, a second dielectric layer 230 is formed on the surface of the first dielectric layer 210 and the surface of the metal connection structure 220.
In some embodiments of the present disclosure, the second dielectric layer 230 is formed by a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the material of the second dielectric layer 230 includes silicon oxide, etc.
Referring to fig. 4, in step S130, a trench 240 is formed in the second dielectric layer 230, wherein the trench 240 exposes a surface of the metal connection structure 220.
In some embodiments of the present application, the method of forming the trench 240 in the second dielectric layer 230 includes: forming a patterned mask layer on the surface of the second dielectric layer 230, wherein the patterned mask layer defines the position of the trench 240; etching the second dielectric layer 230 by using the patterned mask layer as a mask to form the trench 240; and removing the patterned mask layer.
In some embodiments of the present application, the cross-sectional view of the trench 240 may be rectangular. In other embodiments of the present application, the cross-sectional view of the trench 240 may be other patterns, such as a T-like shape.
In some embodiments of the present application, the width of the bottom of the trench 240 may be equal to the width of the top of the metal connection structure 220. In some embodiments of the present application, the width of the bottom of the trench 240 may also be smaller than the width of the top of the metal connection structure 220.
With continued reference to fig. 4, at step S140, the trench 240 is cleaned using an alkaline cleaning solution. After the trench 240 is formed by etching, a cleaning process is required to remove residues in the trench 240.
In some embodiments of the present application, the cleaning process includes multiple cleaning steps. For example, the trench 240 is cleaned by deionized water, and the residual etching solution and the like in the trench 240 are removed preliminarily; cleaning the groove 240 by using an EKC solution, and removing etching residues, metal oxides and the like in the groove 240; the trench 240 is then cleaned using an alkaline solution to remove the residual chemical solution in the trench 240.
Wherein the EKC solution comprises the following main components: hydroxylamine (HDA); diglycolamine (DGA); catechol (cathechol); and (3) water. The EKC solution is able to clean away unwanted residues without compromising the insulating properties of the metal interconnect structure and dielectric layers, while helping to maintain device stability.
In some embodiments of the present application, the time for cleaning the trench 240 using deionized water is 7 minutes to 8 minutes; cleaning the trench 240 with an EKC solution for 3 to 6 minutes; the time for cleaning the trench 240 using the alkaline cleaning solution is 1 minute to 2 minutes. Unlike some methods of forming semiconductor structures in which an acidic solution is used to clean the trench 240, the embodiments of the present disclosure use an alkaline solution to clean the trench 240, and thus the cleaning time is different.
In some embodiments of the present application, the alkaline cleaning solution has a pH greater than 7 and less than 8. The pH value is more than 7, otherwise, the pH value is too close to neutrality, and the cleaning effect is poor; the pH must not be too great, otherwise the alkalinity is too strong and may also corrode the semiconductor structure.
In some embodiments of the present application, the alkaline solution comprises ammonia water or the like, the concentration of which is on the ppm level.
In some methods for forming semiconductor structures, an acidic cleaning solution including hydrofluoric acid is usually used to clean the trench 240, but the acidic solution may corrode and damage the metal connection structure 220 to generate metal ions, which may further induce galvanic reaction to destroy the metal connection structure 220, thereby affecting device reliability. In the method for forming the semiconductor structure provided by the present application, the trench 240 is cleaned by using an alkaline solution such as ammonia water, so that the metal connection structure 220 is not corroded or damaged, metal ions are not generated, a galvanic reaction is not caused, the metal connection structure 220 is not damaged, and the reliability of the device is not affected.
With continued reference to fig. 4, in step S150, the exposed surface of the metal connection structure 220 is passivated. The surface of the metal connection structure 220 is passivated to further protect the metal connection structure 220 from being damaged. The passivation process may form a protective film (not shown) on the surface of the metal connection structure 220 to protect the metal connection structure 220.
In some embodiments of the present application, the passivation process comprises: the exposed surface of the metal connection structure 220 is passivated using a reducing gas.
In some embodiments of the present application, the passivation process comprises: the semiconductor structure is placed in a reaction apparatus filled with a mixed gas containing nitrogen and hydrogen to perform a passivation process.
In some embodiments of the present application, the mixed gas contains nitrogen in an amount of 40% to 60% and hydrogen in an amount of 40% to 60%.
Referring to fig. 5, an interlayer connection structure 250 is formed in the trench 240. The interlayer connection structure 250 electrically connects the metal connection structures 220.
In some embodiments of the present application, the material of the interlayer connection structure 250 includes copper or aluminum.
In some embodiments of the present application, the method for forming the interlayer connection structure 250 includes a chemical vapor deposition process or a physical vapor deposition process.
In some embodiments of the present application, the cross-sectional view of the interlayer connection structure 250 may be a rectangle. In other embodiments of the present application, the cross-sectional view of the interlayer connection structure 250 may also be other figures, such as a T-like shape.
According to the forming method of the semiconductor structure, the groove is cleaned by using an alkaline solution, and the metal connecting structure is not corroded or damaged; furthermore, after cleaning, the metal connecting structure is passivated to protect, so that the reliability of the device can be improved.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein in this embodiment includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements.
It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a first dielectric layer and a metal connecting structure penetrating through the first dielectric layer are formed on the substrate;
forming a second dielectric layer on the surface of the first dielectric layer and the surface of the metal connecting structure;
forming a groove in the second dielectric layer, wherein the groove exposes the surface of the metal connecting structure;
cleaning the trench using an alkaline cleaning solution;
and passivating the exposed surface of the metal connecting structure.
2. The method of claim 1, wherein the trench is cleaned using an alkaline cleaning solution for a time period of 1 minute to 2 minutes.
3. The method of forming a semiconductor structure of claim 1, wherein the alkaline cleaning solution has a pH greater than 7 and less than 8.
4. The method of forming a semiconductor structure of claim 1, wherein the alkaline solution comprises ammonia.
5. The method of forming a semiconductor structure of claim 1, wherein the passivation process comprises: and passivating the exposed surface of the metal connecting structure by using a reducing gas.
6. The method of forming a semiconductor structure of claim 5, wherein the passivation process comprises: the semiconductor structure is placed in a reaction apparatus filled with a mixed gas containing nitrogen and hydrogen to perform a passivation process.
7. The method of forming a semiconductor structure according to claim 6, wherein the mixed gas contains nitrogen in an amount of 40% to 60% and hydrogen in an amount of 40% to 60%.
8. The method of forming a semiconductor structure of claim 1, further comprising: the trench is cleaned using deionized water.
9. The method of forming a semiconductor structure of claim 1, further comprising: the trench was cleaned using EKC solution.
10. The method of forming a semiconductor structure of claim 1, further comprising: and forming an interlayer connection structure in the groove.
CN202010809812.6A 2020-08-13 2020-08-13 Method for forming semiconductor structure Pending CN114078746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010809812.6A CN114078746A (en) 2020-08-13 2020-08-13 Method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010809812.6A CN114078746A (en) 2020-08-13 2020-08-13 Method for forming semiconductor structure

Publications (1)

Publication Number Publication Date
CN114078746A true CN114078746A (en) 2022-02-22

Family

ID=80280310

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010809812.6A Pending CN114078746A (en) 2020-08-13 2020-08-13 Method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN114078746A (en)

Similar Documents

Publication Publication Date Title
KR101608952B1 (en) Liquid composition for semiconductor element cleaning and method for cleaning semiconductor element
US7943562B2 (en) Semiconductor substrate cleaning methods, and methods of manufacture using same
KR100356528B1 (en) Process for production of semiconductor device
JP4252758B2 (en) Composition for removing photoresist residue
US20050245082A1 (en) Process for removing organic materials during formation of a metal interconnect
JP2005347587A (en) Cleaning liquid composition after dry etching, and manufacturing method of semiconductor device
JP3679216B2 (en) Semiconductor substrate cleaning liquid and cleaning method using the same
US20070207609A1 (en) Tungsten Plug Corrosion Prevention Method Using Water
US8329584B2 (en) Method of manufacturing semiconductor device
US20060048801A1 (en) Tungsten plug corrosion prevention method using gas sparged water
CN114078746A (en) Method for forming semiconductor structure
TW561538B (en) Method of preventing tungsten plugs from corrosion
CN103021930A (en) Metal interconnection layer etching method
US6720271B2 (en) Process for removing polymers during the fabrication of semiconductor devices
US20060175297A1 (en) Metallization method for a semiconductor device and post-CMP cleaning solution for the same
US7507664B2 (en) Tungsten plug corrosion prevention method using ionized air
JP3298628B2 (en) Method for manufacturing semiconductor device
US6495472B2 (en) Method for avoiding erosion of conductor structure during removing etching residues
JP2001107081A (en) Cleaning agent for semiconductor device and production of semiconductor device
KR100620188B1 (en) Method for forming a bonding pad in a semiconductor device
CN114322468A (en) Wafer drying method
TWI229382B (en) Method for preventing tungsten-plug corrosion
CN118006401A (en) Method for forming semiconductor device and cleaning liquid
KR100681687B1 (en) Wafer cleaning method
KR100979719B1 (en) Method of manufacturing a semiconductor device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination