CN114078436A - Display controller, display device, and control method of display controller - Google Patents
Display controller, display device, and control method of display controller Download PDFInfo
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- CN114078436A CN114078436A CN202111390363.7A CN202111390363A CN114078436A CN 114078436 A CN114078436 A CN 114078436A CN 202111390363 A CN202111390363 A CN 202111390363A CN 114078436 A CN114078436 A CN 114078436A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The present disclosure provides a display controller, a display apparatus, and a control method of the display controller. A display controller comprising: a rendering circuit configured to receive display data and perform rendering on the received display data, a refresh rate of the display data being K times a refresh rate of the display panel, where K is an integer greater than 1; a memory configured to store compensation data; the compensation circuit is connected with the rendering circuit and the memory and is configured to compensate the display data rendered by the rendering circuit based on the compensation data in the memory to obtain compensated display data; and the driving circuit is connected with the compensation circuit and is configured to generate a driving control signal based on the compensated display data provided by the compensation circuit, wherein the driving control signal is used for driving N/K rows of sub-pixels in N rows of sub-pixels included in the display panel in each period of K periods, N is an integer larger than 1, and N/K is an integer larger than or equal to 1.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display controller, a display device, and a control method of a display device.
Background
With the development of information science and technology, display technology has also been developed. The Display technology based on Organic Light Emitting Diode (OLED) has the characteristics of self-luminescence, wide viewing angle, fast response, flexibility and the like, is an important breakthrough in the field of Display technology, and improves the visual effect.
Disclosure of Invention
The embodiment of the disclosure provides a display controller, a display device and a control method of the display controller.
An embodiment of the present disclosure provides a display controller, including: a rendering circuit configured to receive display data and perform rendering on the received display data, a refresh rate of the display data being K times a refresh rate of a display panel, where K is an integer greater than 1; a memory configured to store compensation data; the compensation circuit is connected with the rendering circuit and the memory and is configured to compensate the display data rendered by the rendering circuit based on the compensation data in the memory to obtain compensated display data; and a driving circuit connected to the compensation circuit and configured to generate a driving control signal for driving N/K rows of sub-pixels of N rows of sub-pixels included in the display panel in each of K periods, where N is an integer greater than 1 and N/K is an integer greater than or equal to 1, based on the compensated display data provided by the compensation circuit.
For example, the compensation circuit includes a first compensation sub-circuit and a second compensation sub-circuit, the compensation data includes first compensation data and second compensation data, and the memory includes a first memory for storing the first compensation data and a second memory for storing the second compensation data, wherein the first compensation sub-circuit is connected to the rendering circuit and the first memory and configured to perform de-burn-in processing on the display data rendered by the rendering circuit based on the first compensation data stored in the first memory, resulting in de-burned-in processed display data; and the second compensation sub-circuit is connected with the first compensation sub-circuit, the second memory and the driving circuit, and is configured to perform moire removal processing on the display data after the screen burn-in processing provided by the first compensation sub-circuit based on second compensation data stored in the second memory to obtain moire removal processed display data, and provide the moire removal processed display data to the driving circuit as the compensated display data.
For example, K is 2, and the driving control signal is used to drive odd-row sub-pixels in the display panel in the first period and even-row sub-pixels in the display panel in the second period.
For example, the refresh rate of the display data received by the rendering circuit is 240Hz, and the refresh rate of the display panel is 120 Hz.
For example, the first memory and the second memory are both random access memories.
For example, a flash memory is further included, the flash memory being connected to the first memory and the second memory for providing the first storage data to the first memory and the second storage data to the second memory.
For example, the rendering circuit, the memory, the compensation circuit, and the driving circuit are integrated as a chip, and the flash memory is an external memory of the chip.
An embodiment of the present disclosure further provides a display device, including: a display controller as described above; and a display panel connected with the display controller and configured to perform display according to a driving control signal provided by the display controller.
For example, the display panel includes: n rows of sub-pixels, wherein N is an integer greater than 1; a gate driving circuit connected to a display controller and the N rows of sub-pixels and configured to provide gate driving signals to the N rows of sub-pixels based on driving control signals provided by the display controller; and the source electrode driving circuit is connected with a display controller and the N rows of sub-pixels and is configured to provide data signals to the N rows of sub-pixels based on driving control signals provided by the display controller.
For example, the gate driving circuit comprises N cascaded shift register units, wherein the nth shift register unit is connected with the nth row of sub-pixels, the output end of the nth shift register unit is connected with the input end of the (N + i) th shift register unit, N is an integer, N is more than or equal to 1 and less than N, and i is an integer more than 1.
For example, K ═ 2, i ═ 2.
The embodiment of the present disclosure provides a control method of the display controller, including: the rendering circuit receives display data and performs rendering on the received display data, wherein the refresh rate of the display data is K times of the refresh rate of the display panel, and K is an integer greater than 1; the compensation circuit performs compensation on the display data rendered by the rendering circuit based on the compensation data in the memory to obtain compensated display data; and the driving circuit generates driving control signals based on the compensated display data provided by the compensation circuit, wherein the driving control signals are used for driving N/K rows of sub-pixels in N rows of sub-pixels included in the display panel in each K periods, N is an integer larger than 1, and N/K is an integer larger than or equal to 1.
For example, the driving circuit drives the odd-numbered rows of sub-pixels in the display panel in the first period and drives the even-numbered rows of sub-pixels in the display panel in the second period.
Drawings
FIG. 1 schematically illustrates a block diagram of a display controller according to an embodiment of the disclosure;
FIG. 2 schematically illustrates a block diagram of a display controller according to another embodiment of the present disclosure;
FIG. 3 schematically illustrates a block diagram of a display controller according to another embodiment of the present disclosure;
FIG. 4 schematically shows a block diagram of a display device according to an embodiment of the disclosure;
fig. 5 schematically shows a block diagram of a display device according to another embodiment of the present disclosure;
fig. 6 schematically illustrates an example structure diagram of a gate driving circuit according to an embodiment of the present disclosure;
fig. 7 schematically shows a signal timing diagram of a display device according to an embodiment of the present disclosure; and
fig. 8 schematically shows a flowchart of a control method of a display controller according to an embodiment of the present disclosure.
Detailed Description
While the present disclosure will be fully described with reference to the accompanying drawings, which contain preferred embodiments of the disclosure, it should be understood before this description that one of ordinary skill in the art can modify the disclosure described herein while obtaining the technical effects of the present disclosure. Therefore, it should be understood that the foregoing description is a broad disclosure directed to persons of ordinary skill in the art, and that there is no intent to limit the exemplary embodiments described in this disclosure.
Furthermore, in the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in schematic form in order to simplify the drawing.
The OLED-based driving architecture may include an AP (Application Processor) terminal and an IC (Integrated Circuit) terminal. The AP terminal and the IC terminal can realize data interaction based on the interface so as to drive the display of the display panel. For example, if the AP is a Mobile application Processor, data interaction between the AP side and the IC side may be implemented based on MIPI (Mobile Industry Processor Interface). The transmission modes of the MIPI may include a Command Mode (i.e., Command Mode) and a Video Mode (i.e., Video Mode). If the AP end and the IC end realize data interaction based on the MIPI command mode, the IC end is required to have frame caching capability. The AP end firstly sends the display data to the encoder through the frame memory, and the encoder is utilized to encode the display data to obtain the encoded display data. Then, the AP end sends the encoded display data to a frame buffer of the IC end. The IC terminal firstly decodes the encoded display data stored in the frame buffer by using a decoder to obtain the decoded display data, and performs processing such as rendering and compensation based on the decoded display data so as to generate a driving control signal to control the display panel to display according to the driving control signal. However, in this manner, the IC terminal has a complicated structure and high power consumption.
Fig. 1 schematically shows a block diagram of a display controller according to an embodiment of the present disclosure.
As shown in fig. 1, the display controller 100 includes a rendering circuit 101, a memory 102, a compensation circuit 103, and a driving circuit 104.
The rendering circuit 101 may receive display data having a refresh rate K times a refresh rate of the display panel, K being an integer greater than 1, and perform rendering on the received display data.
The memory 102 may be for storing compensation data.
The compensation circuit 103 is connected to the rendering circuit 101 and the memory 102. The compensation circuit 103 may perform compensation on the display data rendered by the rendering circuit 101 based on the compensation data in the memory 102, resulting in compensated display data.
The driving circuit 104 is connected to the compensation circuit. The driving circuit 104 may generate driving control signals for driving N/K rows of sub-pixels included in the display panel in each of K periods based on the compensated display data provided by the compensation circuit 103, N being an integer greater than 1, and N/K being an integer greater than or equal to 1.
According to an embodiment of the present disclosure, the display data may refer to display data from the AP side. The compensation data may refer to data capable of improving a display effect of the display data. The compensation data may include one or more. The compensation data may be pre-stored in the display controller. For example, the compensation data may include at least one of: compensation data for compensating for defects in the display data caused by the burn-in problem and compensation data for compensating for defects in the display data caused by moire (i.e., Mura). The compensation data may be determined from the display data.
According to an embodiment of the present disclosure, the rendering circuit 101 may perform rendering on the display data from the AP end by using a rendering algorithm, so as to obtain rendered display data. For example, the Rendering algorithm may include a Sub Pixel Rendering (SPR) algorithm. The refresh rate of the display data may be K times the refresh rate of the display panel. K may be an integer greater than 1. The value of K may be configured according to actual service requirements, and is not limited herein. For example, the refresh rate of the display data is 240 Hz. In the case where K is 2, the refresh rate of the display panel is 120 Hz. In the case where K is 4, the refresh rate of the display panel is 60 Hz.
According to an embodiment of the disclosure, after obtaining the rendered display data, the compensation circuit 103 may perform rendering on the rendered display data based on the compensation data stored in the memory 102, resulting in compensated display data.
According to an embodiment of the present disclosure, the driving circuit 104 may generate the driving control signal based on the compensated display data. The drive control signal may enable driving of a part of the row sub-pixels included in the display panel corresponding to each of the K periods. Some of the rows of sub-pixels may comprise N/K rows of sub-pixels. The sub-pixels driven during different periods may be different, i.e. there is no repetition between the N/K rows of sub-pixels driven during different periods.
According to an embodiment of the present disclosure, the N/K rows of sub-pixels corresponding to each period may be N/K rows of sub-pixels obtained in an interval driving manner. For example, the N/K rows of sub-pixels corresponding to each period may be N/K rows of sub-pixels obtained every interval (K-1) rows of sub-pixels. That is, the driving control signal enables driving of N/K rows of sub-pixels included in the display panel corresponding to each period in such a manner that the sub-pixels are driven every interval (K-1) rows.
According to the embodiments of the present disclosure, the N/K rows of sub-pixels corresponding to each period may also be N/K rows of sub-pixels obtained in a hybrid driving manner. The hybrid driving may include interval driving and line-by-line driving, that is, the N/K lines of sub-pixels corresponding to each period may include T lines of sub-pixels obtained in a line-by-line driving manner and S lines of sub-pixels obtained in an interval driving manner. T and S are both integers greater than or equal to 1, and N/K ═ T + S.
For example, the N/K rows of sub-pixels corresponding to each period may be N/K rows of sub-pixels obtained every interval (K-1) rows of sub-pixels.
In the case where K is 2, the K period segments include a first period and a second period. The N/2 rows of sub-pixels corresponding to the first and second periods may be N/2 rows of sub-pixels obtained by one row of sub-pixels at intervals. That is, if N is an even number, N/2 rows of sub-pixels corresponding to the first period include a first row of sub-pixels, a third row of sub-pixels, … …, an N-3 th row of sub-pixels, and an N-1 th row of sub-pixels. The N/2 rows of sub-pixels corresponding to the second period include a second row of sub-pixels, a fourth row of sub-pixels, … …, an N-2 row of sub-pixels, and an nth row of sub-pixels. If N is an odd number, the N/2 rows of sub-pixels corresponding to the first period include a first row of sub-pixels, a third row of sub-pixels, … …, an N-2 row of sub-pixels, and an Nth row of sub-pixels. The N/2 rows of sub-pixels corresponding to the second period include a second row of sub-pixels, a fourth row of sub-pixels, … …, an N-3 th row of sub-pixels, and an N-1 th row of sub-pixels.
In the case where K is 3, the K periods include a first period, a second period, and a third period. The N/3 rows of sub-pixels corresponding to the first, second, and third periods may be N/3 rows of sub-pixels obtained by spacing two rows of sub-pixels. That is, the N/3 rows of sub-pixels corresponding to the first period include a first row of sub-pixels, a fourth row of sub-pixels, a seventh row of sub-pixels, and so on. The N/3 rows of sub-pixels corresponding to the second period include a second row of sub-pixels, a fifth row of sub-pixels, an eighth row of sub-pixels, and so on. The N/3 rows of sub-pixels corresponding to the third period may include a third row of sub-pixels, a sixth row of sub-pixels, a ninth row of sub-pixels, and so on.
The display controller of the embodiment of the disclosure receives display data with a refresh rate K times that of the display panel by using the rendering circuit, and generates sub-pixel rows driving the total row number 1/K by using the driving circuit, so that normal display can be realized without a buffer and a decoder. Since the buffer and decoder are omitted, the structure of the display controller is simplified, so that power consumption can be reduced.
Fig. 2 schematically illustrates a block diagram of a display controller according to another embodiment of the present disclosure. The display controller 200 of fig. 2 is similar to the display controller 100 described above, and the description above for the display controller 100 is equally applicable to this embodiment. For convenience of description, the following description will mainly explain the difference in detail.
As shown in fig. 2, the display controller 200 includes a rendering circuit 101, a memory, a compensation circuit, and a driving circuit 104. In fig. 2, the compensation circuit may include a first compensation sub-circuit 1030 and a second compensation sub-circuit 1031. The compensation data includes first compensation data and second compensation data. The memory 102 may include a first memory 1020 for storing first compensation data and a second memory 1021 for storing second compensation data. For example, the first Memory 1020 and the second Memory 1021 may be Random Access Memories (RAMs).
The first compensation sub-circuit 1030 is connected to the rendering circuit 101 and the first memory 1020. The first compensation sub-circuit 1030 may perform a burn-in (burn-in) process on the display data rendered by the rendering circuit 101 based on the first compensation data stored in the first memory 1020, so as to obtain the display data after the burn-in process.
The second compensation sub-circuit 1031 is connected to the first compensation sub-circuit 1030, the second memory 1021, and the driving circuit 104. The second compensation sub-circuit 1031 may perform moire (Demura) removal processing on the display data after the screen burn-in processing provided by the first compensation sub-circuit based on the second compensation data stored in the second memory 1021 to obtain display data after the moire removal processing, and provide the display data after the moire removal processing as the compensated display data to the driving circuit 104.
According to an embodiment of the present disclosure, the first compensation data may refer to compensation data for compensating for a defect of the display data caused by the burn-in problem. The second compensation data may be compensation data for compensating for a defect of the display data caused by the moire. Moire may refer to a phenomenon in which different film layers are not uniform in thickness during the manufacturing process of the display panel, resulting in poor electrical and optical uniformity, so that a user may exhibit color unevenness when viewing the display panel. Moire processing may refer to brightness compensation of the non-uniform color display of the display panel so that the color is relatively uniform.
In operation, the rendering circuitry 101 renders the received display data. The first compensation sub-circuit 1030 may perform the screen burn-in removal processing on the display data rendered by the rendering circuit 101 based on the first compensation data stored in the first memory 1020, so as to obtain the screen burn-in removed display data. The second compensation sub-circuit 1031 may perform moire processing on the display data subjected to the screen burn-in processing by the first compensation sub-circuit 1030, obtain moire processed display data, and provide the moire processed display data to the driving circuit. The driving circuit 104 may generate a driving control signal based on the compensated display data provided by the second compensation circuit 1031.
According to an embodiment of the present disclosure, K ═ 2. In this case, the refresh rate of the display data received by the rendering circuit 101 is 2 times the refresh rate of the display panel. For example, the rendering circuit 101 receives display data having a refresh rate of 240Hz and the display panel has a refresh rate of 120 Hz. The driving control signal generated by the driving circuit 104 can be used to drive the odd-numbered rows of sub-pixels in the display panel in the first period and drive the even-numbered rows of sub-pixels in the display panel in the second period. For example, the odd row sub-pixels of the display panel may be driven to emit light in the order of the 1 st row, the third row, and the fifth row … … for a first period, and then the even row sub-pixels may be driven to emit light in the order of the second row, the fourth row, and the sixth row for a second period. In this way, cross-driving of odd-row sub-pixels and even-row sub-pixels is achieved. It can be seen that, even if the refresh rate of the received display data is twice the refresh rate of the display panel, the display controller of the embodiment of the present disclosure can still control the display panel to implement display scanning with the refresh rate of the display panel itself, thereby ensuring the normal display effect of the display panel. In the case where the refresh rate of the display panel is 120Hz, the power consumption of the display controller may be reduced by about 37mW compared to the related art when the test is performed using the IC of the 40nm process.
Fig. 3 schematically illustrates a block diagram of a display controller according to another embodiment of the present disclosure. The display controller 300 of fig. 3 is similar to the display controller 200 described above, except at least that it further includes a flash memory 105. For convenience of description, the following description will mainly explain the difference in detail.
As shown in fig. 3, the display controller 300 may further include a flash memory 105. The flash memory 105 is connected to the first memory 1020 and the second memory 1021. The flash memory 105 may provide the first compensation data to the first memory 1020 and the second compensation data to the second memory 1021.
Since the first memory 1020 and the second memory 1021 are both random access memories, they have volatility. The flash memory 105 may not lose stored data in the event of a power failure. Therefore, after the first memory 1020 and the second memory 1021 are powered off to clear the data, if the compensation data needs to be used again, the compensation data can be reloaded from the flash memory 105, and normal execution of the operation is guaranteed. According to an embodiment of the present disclosure, the rendering circuit 101, the memory 102, the compensation circuit 103, and the driving circuit 104 may be integrated as a chip, and the flash memory 105 may be an external memory of the chip.
Fig. 4 schematically shows a block diagram of a display device according to an embodiment of the present disclosure.
As shown in fig. 4, the display device 400 may include a display controller 401 and a display panel 402.
The display controller 401 may be implemented as the display controller of any of the embodiments described above, such as the display controller 100, 200, or 300.
The display panel 402 is connected to the display controller 401. The display panel 402 may perform display according to a driving control signal provided by the display controller 401.
According to an embodiment of the present disclosure, the display controller 401 may perform rendering on the received display data to obtain rendered display data, perform compensation on the rendered display data based on the compensation data to obtain compensated display data, and generate a driving control signal based on the compensated display data. The display panel 402 may display N/K rows of sub-pixels of N rows of sub-pixels included in the display panel in each of K periods according to a driving control signal provided by the display controller 401.
Fig. 5 schematically shows a block diagram of a display device according to another embodiment of the present disclosure.
As shown in fig. 5, the display device 500 includes a display controller 501 and a display panel 502.
The display controller 501 may be implemented by the display controller of any of the embodiments described above. In the present embodiment, the display controller 501 is implemented to have the same structure as the display controller 300 described above, and the description thereof is omitted.
The display panel 502 may include a plurality of subpixels P, a gate driving circuit 202, and a source driving circuit 203.
The plurality of subpixels P may be arranged in N rows, N being an integer greater than 1. For example, the plurality of sub-pixels P may be arranged in an array form.
The gate driving circuit 202 is connected to the display controller 501 and the N rows of sub-pixels P. The gate driving circuit 202 may provide gate driving signals to the N rows of sub-pixels P based on driving control signals provided by the display controller 501.
The source driving circuit 203 is connected to the display controller 501 and the N rows of sub-pixels 201. The source driving circuit 203 may supply data signals to the N rows of sub-pixels P based on a driving control signal supplied from the display controller 501.
According to an embodiment of the present disclosure, the driving control signals provided by the display controller 501 may include gate driving signals and data signals. The N rows of sub-pixels 201 may include N × M sub-pixels P. The N × M sub-pixels P are arranged in an N × M array. M may be an integer greater than 1. The gate driving signals may include N, i.e., a first gate driving signal G1, second gate driving signals G2, … …, an N-1 th gate driving signal GN-1, and an nth gate determining signal GN. The data signals may include M, i.e., a first data signal D1, second data signals D2, … …, an M-1 th data signal DM-1, and an M-th data signal DM.
According to an embodiment of the present disclosure, the gate driving circuit 202 may be connected with the N × M subpixels P. The gate driving circuit 202 may be connected to the N rows of sub-pixels 201 through a plurality of gate signal lines extending in the first direction (x direction in fig. 5), respectively. The plurality of gate signal lines may include N, i.e., a first gate signal line, a second gate signal line, … …, an N-1 th gate signal line, and an nth gate signal line.
For example, the gate driving circuit 201 may be connected to the first row of subpixels P through a first gate signal line to provide a first gate driving signal G1 to the first row of subpixels P. The second row of sub-pixels P is connected by a second gate signal line to provide a second gate drive signal G2 to the second row of sub-pixels P, and so on. The first row of subpixels P is turned on in response to receiving the first gate driving signal G1, the second row of subpixels P is turned on in response to receiving the second gate driving signal G2, and so on.
According to the embodiment of the present disclosure, the gate driving circuit 202 may drive the N rows of sub-pixels 201 every at least one or more rows to sequentially turn on the sub-pixels P of a partial row. For example, the gate driving circuit 202 may drive the N rows of sub-pixels 201 to sequentially turn on the odd rows of sub-pixels P every other row, that is, may sequentially turn on the first row of sub-pixels P, the third row of sub-pixels P, the fifth row of sub-pixels P, and so on; then the second row of sub-pixels P, the fourth row of sub-pixels P, the sixth row of sub-pixels P may be turned on in sequence, and so on.
According to an embodiment of the present disclosure, the source driving circuit 203 may be connected with the N × M subpixels P. The source driving circuit 203 may be connected to the M columns of the subpixels P through a plurality of data lines extending in the second direction (y direction in fig. 5), respectively. The plurality of source signal lines may include M, that is, a first source signal line, a second source signal line, … …, an M-1 th source signal line, and an M-th source signal line.
For example, the source driving circuit 203 may be connected to the first column of sub-pixels P through a first data line to provide the first data signal D1 to the first column of sub-pixels P. The second column of sub-pixels P is connected by a second data line to provide a second data signal D2 to the second column of sub-pixels P and so on.
For example, in a case where the first row of subpixels P is turned on, the source driving circuit 203 may provide M data signals for the first row of subpixels through M data lines to M subpixels included in the first row of subpixels P, respectively. When the second row of sub-pixels P is turned on, the source driving circuit 203 may provide M data signals for the second row of sub-pixels P to the M sub-pixels included in the second row of sub-pixels P through the M data lines, and so on.
Fig. 6 schematically shows an example structure diagram of a gate driving circuit according to an embodiment of the present disclosure.
As shown in fig. 6, the gate driving circuit 202 may include N cascaded shift register units, i.e., a shift register unit GOA1, shift register units GOA2, … …, shift register units GOAn, … …, a shift register unit GOAn-1, and a shift register unit GOAn. For simplicity, only the first through fourth level one bit register units GOA1 through GOA4 are shown.
According to an embodiment of the present disclosure, each shift register cell may have an input IN and an output OUT. The output of the nth stage shift register unit is connected with the nth row of sub-pixels. For example, the output of the first stage GOA1 is connected with the first row of sub-pixels A/A1, the output of the second stage GOA2 is connected with the second row of sub-pixels A/A2, the output of the third stage GOA3 is connected with the third row of sub-pixels A/A3, and so on.
According to an embodiment of the present disclosure, an output terminal of the nth stage shift register unit is connected to an input terminal of the n + i th stage shift register unit. N is an integer, N is more than or equal to 1 and less than N, and i is an integer more than 1. IN fig. 6, K is 2, i is 2, the output terminal OUT of the first stage shift register unit GOAl is connected to the input terminal IN of the third stage shift register unit GOA3, the output terminal OUT of the second stage shift register unit GOA2 is connected to the input terminal of the fourth stage shift register unit GOA4, and so on. An input IN of the first stage shift register unit GOA1 may be connected to receive a first enable signal GSTV1, and an input IN of the second stage shift register unit GOA2 may be connected to receive a second enable signal GSTV 2.
Each shift register unit may also have a clock signal terminal CLK. According to the embodiments of the present disclosure, each stage of shift register unit may generate an output signal at the output terminal OUT as a gate driving signal under the control of the signals of the respective clock signal terminal CLK and the input terminal IN. For example, the shift register unit GOA1 generates a first gate driving signal G1, the shift register unit GOA2 generates a second gate driving signal G2, and so on. Through a cascade connection mode, the grid driving signal generated by the shift register unit at the next stage can be shifted relative to the grid driving signal generated by the shift register unit at the previous stage.
According to an embodiment of the present disclosure, the clock signals received by the gate driving circuit may include a first clock signal CLK1 and a second clock signal CLK 2. In fig. 6, the CLK terminals of the shift register cells of the odd-numbered stages are connected to receive the first clock signal CLK1, and the clock signal terminals CLK of the shift register cells of the even-numbered stages are connected to receive the second clock signal CLK 2.
According to an embodiment of the present disclosure, each shift register cell may also be connected to receive a power supply signal VGH and a reference signal VGL.
According to an embodiment of the present disclosure, the driving control signal provided to the gate driving circuit of the display panel by the display controller may include at least one of the above-described start signals GSTV1, GSTV2, clock signals CLK1, CLK 2.
Although the above description has been made taking K ═ 2 and i ═ 2 as an example, embodiments of the present disclosure are not limited thereto. According to the embodiment of the disclosure, the value of i may be determined according to the value of K, and the value of K may be configured according to requirements, which is not limited herein.
The above is merely an example illustration of the display device of the embodiments of the present disclosure, and the structure of the display device of the embodiments of the present disclosure is not limited thereto, and may have other structures as needed. For example, the display device may be a display device based on organic light emitting diode display technology. The gate driving circuit of the display device may employ a different cascade manner from that shown in fig. 6.
Fig. 7 schematically shows a signal timing diagram of a display apparatus according to an embodiment of the present disclosure. The signal sequence of fig. 7 will be described below by taking the display device of fig. 5 as an example in the case where N is 1080 and K is 2.
In the first period, the gate driving circuit 202 may generate the gate driving signals G1, G3, G5 … … G1079 sequentially shifted at preset time intervals to sequentially turn on the first, third, and fifth rows of sub-pixels … …, 1079.
In the second period, the gate driving circuit 202 may generate the gate driving signals G2, G4, G6 … … G1080 sequentially shifted at preset time intervals, thereby sequentially turning on the second row sub-pixels and the fourth row sub-pixels … … and 1080.
Fig. 8 schematically shows a flowchart of a control method of a display controller according to an embodiment of the present disclosure.
As shown in fig. 8, the method includes operations S810 to S830.
In operation S810, the rendering circuit receives display data and performs rendering on the received display data, where a refresh rate of the display data is K times a refresh rate of the display panel, and K is an integer greater than 1.
In operation S820, the compensation circuit performs compensation on the display data rendered by the rendering circuit based on the compensation data in the memory, so as to obtain compensated display data.
In operation S830, the driving circuit generates driving control signals based on the compensated display data provided by the compensation circuit, the driving control signals being used to drive N/K rows of sub-pixels included in the display panel in each of K periods, N being an integer greater than 1, and N/K being an integer greater than or equal to 1.
According to the embodiment of the present disclosure, K is 2, and the driving circuit drives the odd-row sub-pixels in the display panel in the first period and drives the even-row sub-pixels in the display panel in the second period.
It will be appreciated by those skilled in the art that the embodiments described above are exemplary and can be modified by those skilled in the art, and that the structures described in the various embodiments can be freely combined without conflict in structure or principle.
Having described preferred embodiments of the present disclosure in detail, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope and spirit of the appended claims, and the disclosure is not limited to the exemplary embodiments set forth herein.
Claims (13)
1. A display controller comprising:
a rendering circuit configured to receive display data and perform rendering on the received display data, a refresh rate of the display data being K times a refresh rate of a display panel, where K is an integer greater than 1;
a memory configured to store compensation data;
the compensation circuit is connected with the rendering circuit and the memory and is configured to compensate the display data rendered by the rendering circuit based on the compensation data in the memory to obtain compensated display data; and
a driving circuit connected to the compensation circuit and configured to generate a driving control signal for driving N/K rows of sub-pixels of N rows of sub-pixels included in a display panel in each of K periods based on the compensated display data provided by the compensation circuit, wherein N is an integer greater than 1 and N/K is an integer greater than or equal to 1.
2. The display controller of claim 1, wherein the compensation circuit comprises a first compensation sub-circuit and a second compensation sub-circuit, the compensation data comprises first compensation data and second compensation data, the memory comprises a first memory for storing the first compensation data and a second memory for storing the second compensation data, wherein,
the first compensation sub-circuit is connected with the rendering circuit and the first memory and is configured to execute screen burn-in removing processing on the display data rendered by the rendering circuit based on first compensation data stored in the first memory to obtain the display data after screen burn-in removing processing; and
the second compensation sub-circuit is connected to the first compensation sub-circuit, the second memory, and the driving circuit, and is configured to perform moire removal processing on the display data after the screen burn-in removal processing provided by the first compensation sub-circuit based on second compensation data stored in the second memory to obtain moire removal processed display data, and to provide the moire removal processed display data to the driving circuit as the compensated display data.
3. The display controller of claim 1, wherein K-2, and the driving control signal is used to drive odd-row sub-pixels in the display panel in a first period and even-row sub-pixels in the display panel in a second period.
4. The display controller of claim 3, wherein the refresh rate of the display data received by the rendering circuitry is 240Hz and the refresh rate of the display panel is 120 Hz.
5. The display controller of claim 2, wherein the first and second memories are both random access memories.
6. The display controller of claim 5, further comprising a flash memory coupled to the first memory and the second memory, configured to provide the first compensation data to the first memory and the second compensation data to the second memory.
7. The display controller of claim 6, wherein the rendering circuit, the memory, the compensation circuit, and the driving circuit are integrated as a chip, and the flash memory is an external memory to the chip.
8. A display device, comprising:
the display controller of any one of claims 1 to 7; and
a display panel connected with the display controller and configured to perform display according to a driving control signal provided by the display controller.
9. The display device according to claim 8, wherein the display panel comprises:
n rows of sub-pixels, wherein N is an integer greater than 1;
a gate driving circuit connected to a display controller and the N rows of sub-pixels and configured to provide gate driving signals to the N rows of sub-pixels based on driving control signals provided by the display controller; and
and the source electrode driving circuit is connected with a display controller and the N rows of sub-pixels and is configured to provide data signals to the N rows of sub-pixels based on driving control signals provided by the display controller.
10. The display device according to claim 9, wherein the gate driving circuit includes N stages of cascaded shift register cells, wherein the nth stage of shift register cells is connected to the nth row of sub-pixels, and an output terminal of the nth stage of shift register cells is connected to an input terminal of the N + i th stage of shift register cells, wherein N is an integer and 1 ≦ N < N, and i is an integer greater than 1.
11. The display device according to claim 10, wherein K-2, i-2.
12. A control method of a display controller as claimed in any one of claims 1 to 7, comprising:
the rendering circuit receives display data and performs rendering on the received display data, wherein the refresh rate of the display data is K times of the refresh rate of the display panel, and K is an integer greater than 1;
the compensation circuit performs compensation on the display data rendered by the rendering circuit based on the compensation data in the memory to obtain compensated display data; and
the driving circuit generates driving control signals based on the compensated display data provided by the compensation circuit, wherein the driving control signals are used for driving N/K rows of sub-pixels in N rows of sub-pixels included in the display panel in each K periods, N is an integer larger than 1, and N/K is an integer larger than or equal to 1.
13. The method of claim 12, wherein K-2, the driving circuit drives the odd-row subpixels of the display panel in the first period and drives the even-row subpixels of the display panel in the second period.
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