CN114078417B

CN114078417B - GOA circuit, driving method thereof, display panel and display device

Info

Publication number: CN114078417B
Application number: CN202111402673.6A
Authority: CN
Inventors: 林允植; 刘立伟; 张舜航; 李昌峰; 李付强; 王洪润; 胡合合; 雷利平
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-11-19
Filing date: 2021-11-19
Publication date: 2024-01-09
Anticipated expiration: 2041-11-19
Also published as: CN114078417A

Abstract

The invention discloses a GOA circuit and a driving method thereof, a display panel and a display device, wherein the GOA circuit comprises a first input sub-circuit, a second input sub-circuit and a driving output sub-circuit; the first input sub-circuit is electrically connected with the first input signal end, the first voltage signal end and the control end of the driving output sub-circuit respectively; the second input sub-circuit is electrically connected with the second input signal end, the second voltage signal end and the control end of the driving output sub-circuit respectively; the driving output sub-circuit is respectively and electrically connected with the clock signal end and the driving signal output end; the second input sub-circuit is conducted under the control of the second input signal end in at least part of the conduction time period of the driving output sub-circuit, and the voltage of the control end of the driving output sub-circuit is compensated and charged, so that the charging time of the control end of the driving output sub-circuit is prolonged, the leakage time of the control end of the driving output sub-circuit is reduced, the negative offset of the threshold voltage is increased, and the phenomenon of poor screen flashing is reduced.

Description

GOA circuit, driving method thereof, display panel and display device

Technical Field

The invention belongs to the technical field of display, and particularly relates to a GOA circuit, a driving method thereof, a display panel and a display device.

Background

In the conventional display device, when a noise reduction transistor in an array substrate row driving (Gate Driver on Array, GOA) circuit included in a shift register unit is abnormal in characteristics and leaks, the potential of the GOA circuit, which is a pull-up node, cannot be maintained in an input stage. For GOA circuits with different mobilities, the larger the mobility is, the more serious the electric leakage is, so that the GOA circuit is abnormal in output, and the GOA circuit is insufficient in output capacity at the moment, so that a phenomenon of poor screen flashing is caused.

Disclosure of Invention

The invention mainly aims to provide a GOA circuit, a driving method thereof, a display panel and a display device, so as to solve the problem of poor display screen flash caused by insufficient output capability of the GOA circuit in the prior art.

In view of the above problems, the present invention provides a GOA circuit, including a first input sub-circuit, a second input sub-circuit, and a driving output sub-circuit;

the control end of the first input sub-circuit is electrically connected with a first input signal end, the first end of the first input sub-circuit is electrically connected with a first voltage signal end, and the second end of the first input sub-circuit is electrically connected with the control end of the driving output sub-circuit;

The control end of the second input sub-circuit is electrically connected with a second input signal end, the first end of the second input sub-circuit is electrically connected with a second voltage signal end, and the second end of the second input sub-circuit is electrically connected with the control end of the driving output sub-circuit;

the first end of the driving output sub-circuit is electrically connected with the clock signal end, and the second end of the driving output sub-circuit is electrically connected with the driving signal output end;

the second input sub-circuit is used for conducting under the control of the second input signal end in at least part of conducting time period of the driving output sub-circuit, and compensating and charging the voltage of the control end of the driving output sub-circuit.

The invention also provides a driving method of the GOA circuit, which is applied to the GOA circuit, and comprises the following steps:

in a first time period of an output stage, the second input sub-circuit is controlled to be conducted through the second input signal end, the voltage of the control end of the driving output sub-circuit is subjected to compensation charging, so that the driving output sub-circuit is conducted, and the scanning signal of the clock signal end is output through the driving signal output end;

In a second time period of the output stage, the second input signal end is used for controlling the second input sub-circuit to be disconnected, the compensation charging of the voltage of the control end of the driving output sub-circuit is stopped, the conduction of the driving output sub-circuit is maintained, and the scanning signal of the clock signal end is output through the driving signal output end;

wherein the total duration of the first time period and the second time period is equal to the duration of the output phase.

The invention also provides a display panel comprising a GOA circuit as claimed in any one of the preceding claims.

The invention also provides a display device comprising the display panel.

One or more embodiments of the above-described solution may have the following advantages or benefits compared to the prior art:

according to the GOA circuit, the driving method thereof, the display panel and the display device, the second input sub-circuit is additionally arranged, and in at least part of the conduction time period of the driving output sub-circuit, the second input sub-circuit is controlled to be conducted through the second input signal end, the voltage of the control end of the driving output sub-circuit is subjected to compensation charging, so that the total charging time of the control end of the driving output sub-circuit is the sum of the time of the first input sub-circuit and the time of the second input sub-circuit, the charging time of the control end of the driving output sub-circuit is prolonged, the leakage time of the control end of the driving output sub-circuit is further reduced, and meanwhile, the threshold voltage negative offset is increased. By adopting the technical scheme of the invention, the output capability of the GOA circuit can be ensured, and the phenomenon of poor screen flashing can be reduced.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, serve to explain the invention, without limitation to the invention. In the drawings:

FIG. 1 is a schematic diagram of a topology of a related art GOA circuit;

FIG. 2 is a schematic diagram illustrating a connection of the odd-even row interleaved driving scheme of FIG. 1;

FIG. 3 is an I-V plot of two transistors for GOA with electron mobilities of 10 and 30 for the drive mode shown in FIG. 2;

FIG. 4 is a schematic diagram showing the potential of the pull-up node PU at electron mobilities of 10 and 30;

FIG. 5 is a schematic diagram of a GOA circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a topology of another embodiment of the GOA circuit of the present invention;

FIG. 7 is a schematic diagram showing a specific structure of the GOA circuit shown in FIG. 6;

FIG. 8 is a schematic diagram illustrating a connection of the odd-even row interleaved driving scheme of FIG. 7;

FIG. 9 is a timing diagram of the clock signals corresponding to FIG. 8;

FIG. 10 is a timing diagram of Gn-4, gn-3, gn-2, gn-1, gn (PU) and Gn (out);

FIG. 11 is a schematic diagram showing another embodiment of the GOA circuit shown in FIG. 6;

fig. 12 is a schematic diagram of another specific structure of the GOA circuit shown in fig. 6.

Detailed Description

The following will describe embodiments of the present invention in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present invention, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that, as long as no conflict is formed, each embodiment of the present invention and each feature of each embodiment may be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.

The transistors used in all embodiments of the present invention may be transistors, thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

Fig. 1 is a schematic topology diagram of a GOA circuit of the related art, as shown in fig. 1, the GOA circuit may include a first transistor M1 to an eighteenth transistor M18 and a first capacitor C1, and specific connection relationships are not described herein with reference to fig. 1.

For transistors with different electron Mobility, the difference of 0V drain current Id is different for each transistor, although the threshold voltage negative offset is the same, for example, a transistor with electron Mobility (Mobility) of 30 has a 0V drain current Id about 100 times that of a transistor with electron Mobility of 10. When the sixth transistor M6 and the eighth transistor M8 leak electricity, the voltage of the pull-up node PU of the GOA circuit is insufficient, the mobility is larger, the leakage electricity is more serious, so that the GOA circuit outputs abnormally, and the GOA circuit has insufficient output capability at the moment, so that a bad phenomenon of screen flashing is caused.

In general, the GOA circuit shown in fig. 1 may be driven by a parity row interlaced driving method, and fig. 2 is a schematic connection diagram of the parity row interlaced driving method corresponding to fig. 1. As shown in fig. 2, the left GOA circuit corresponds to the gate odd-numbered rows in the panel and the right GOA circuit corresponds to the gate even-numbered rows in the panel. As shown in fig. 2, gn+6 rows are used for Gn row rest, and the GOA output signal G7 is connected to the circuit of Gate1 in fig. 2, and G11 is connected to Gate5 in the same way. As shown in FIG. 2, the Input signal is provided to Gn-4, and the top Input signal is provided by the STV signal, as in the G1 access Gate5 circuit of the Gate1 output in FIG. 2, and the rest is the same. The same principle of the left-right GOA is not described in detail here.

Fig. 3 is an I-V plot of two transistors for GOA with electron mobilities of 10 and 30 in the drive mode shown in fig. 2. Although the threshold voltage negative offsets of the two transistors are the same, the currents at the same voltage are different because of the different electron mobilities. As shown in FIG. 3, when the electron mobility was 10, the current was 4X 10-9A at 0V, and when the electron mobility was 30, the current was 4X 10-6A at 0V. This results in that the potential of the pull-up node PU is less likely to be maintained the greater the electron mobility, due to the difference in leakage condition of the pull-up node PU in the same time.

Fig. 4 is a schematic diagram of the potential of the pull-up node PU when the electron mobility is 10 and 30, as shown in fig. 4, the gates of the sixth transistor M6 and the eighth transistor M8 are connected to the pull-down node, the drain is connected to the pull-up node, the source is connected to the low-level signal terminal, and when the potential of the pull-down node is low (-11V), the low-level signal terminal is-11V, and the vgs voltage is-11- (-11) =0v. When the negative offset of the threshold voltage is-1V, vgs is larger than Vth, and leakage exists in the sixth transistor M6 and the eighth transistor M8 which cannot be completely turned off, so that the leakage of the pull-up node is caused, and the normal output of the GOA circuit cannot be ensured. As shown in fig. 4, from the waveform diagrams of the pull-up junction in both cases of the electron mobility of 10 and 30, it is seen that the case of the electron mobility of 30 is more serious.

In the related art, vgs can be controlled, the electric leakage phenomenon of the pull-up node can be improved, and the discharge time of the pull-up node can be reduced, namely, the charging time of the pull-up node is increased, and the electric leakage phenomenon of the pull-up node is improved.

For example, by taking the example of reducing the drain time of the pull-up node PU for the existing GOA circuit, the drain time adjustment of the pull-up node can be performed by adjusting the timing. (the timing of a conventional GOA circuit is designed with a precharge time, taking into account that the high level of the clock signal CLK at the parity interleaved clock signal terminal C is effectively 4H, the duty cycle of the clock signal CLK is 50%, and the clock signals CLK overlap by 25%. Where 1h=time is occupied per Gate line, such as resolution UD (3840 x 2160), 60Hz,1sec/60Hz/Gate line number=1/60/2160=7.5 us).

The existing GOA circuit is controlled by the reference timing as follows: input=gn-4, and the charging of the pull-up node PU ends 4H after Gn-4 rows of the clock signal CLK is high, during which the leakage of PU is enabled by either the sixth transistor M6 or the eighth transistor M8, and the PU leakage time is substantially the same as Gn rows of the clock signal CLK being on, i.e., 4H time. Threshold voltage negative offset > -1.5V.

The first scheme of the pull-up node PU leakage time in the related art is as follows:

Input=gn-2, and the charging of the pull-up node PU ends after 2H passes after Gn-2 clock signal CLK is Input, and simultaneously, the discharging of the pull-up node PU is started by the third transistor M3 or the fourth transistor M4, and the drain time of the pull-up node PU is 1/2 (Gn-2 overlaps Gn by 50%) of the high level of the clock signal CLK, that is, 2H time. Threshold voltage negative offset > -2V.

The second scheme of the pull-up node PU leakage time in the related art is as follows:

input=gn-1, and the charging of the pull-up node PU ends after 1H after the Input of Gn-1 clock signal CLK, and PU leakage time is 1H. Threshold voltage negative offset > -2.7V.

In the related art, the second scheme can improve the negative offset of the threshold voltage, but the charging time of the pull-up node PU is reduced, so that the pull-up node PU is insufficiently charged and has poor output when the threshold voltage is positively offset, and particularly when the 1H time is less than 15us, the phenomenon of poor output is more obvious.

Therefore, in order to solve the technical problems, the present invention provides the following technical solutions.

Fig. 5 is a schematic diagram of a topology of an embodiment of the GOA circuit of the present invention, as shown in fig. 5, the GOA circuit of the present embodiment may include a first input sub-circuit 10, a second input sub-circuit 11, and a driving output sub-circuit 12.

The control terminal of the first Input sub-circuit 10 is electrically connected to a first Input signal terminal Input1, the first terminal of the first Input sub-circuit 10 is electrically connected to a first voltage signal terminal V1, and the second terminal of the first Input sub-circuit 10 is electrically connected to a control terminal (hereinafter, may be referred to as a pull-up node PU) of the driving output sub-circuit 12. The control end of the second Input sub-circuit 11 is electrically connected with the second Input signal end Input2, the first end of the second Input sub-circuit 11 is electrically connected with the second voltage signal end V2, and the second end of the second Input sub-circuit 11 is electrically connected with the pull-up node PU. The first terminal of the driving output sub-circuit 12 is electrically connected to the clock signal terminal C, and the second terminal of the driving output sub-circuit 12 is electrically connected to the driving signal output terminal Gout. The first voltage signal terminal V1 and the second voltage signal terminal V2 may be the same voltage signal terminal, both output VDDi signals, and the VDDi signals are high level signals. The clock signal terminal C may output the clock signal CLK.

In a specific implementation process, the first Input sub-circuit 10 is configured to control the first Input sub-circuit 10 to be turned on through the first Input signal terminal Input1, so that the first voltage signal terminal V1 charges the first voltage signal terminal V1. The second Input sub-circuit 11 is configured to conduct under the control of the second Input signal terminal Input2 during at least a part of the on period of the driving output sub-circuit 12, and perform compensation charging on the voltage of the pull-up node PU. In this way, the total charging time of the control end of the driving output sub-circuit 12 is the sum of the time of the first input sub-circuit 10 and the time of the second input sub-circuit 11, that is to say, the charging time of the control end of the driving output sub-circuit 12 is prolonged, so that the leakage time of the control end of the driving output sub-circuit 12 is reduced, and meanwhile, the negative offset of the threshold voltage is increased, and even if the sixth transistor M6 and the eighth transistor M8 cannot be completely turned off and have leakage, the pull-up node PU can still be ensured to have high enough voltage, thereby ensuring the output capability of the GOA circuit and reducing the occurrence of the bad phenomenon of the flash screen.

In a specific implementation process, the signal Input by the first Input signal end Input1 leads the signal Input by the second Input signal end Input2, and a partial overlapping waveform exists between the signal Input by the first Input signal end Input1 and the signal Input by the second Input signal end Input 2. Specifically, the signal Input by the first Input signal terminal Input1 leads the 3/4 waveform of the signal Input by the second Input signal terminal Input 2. I.e. the first Input signal terminal Input1 adopts a signal with input=gn-4 and the second Input signal terminal Input2 adopts a signal with input=gn-1.

In the GOA circuit, in a first Input stage t1, the first Input sub-circuit 10 is controlled to be turned on by the first Input signal terminal Input1, so that the first voltage signal terminal V1 charges the pull-up node PU;

in the second Input stage t2, the first Input sub-circuit 10 is controlled to be turned on by the second Input signal terminal Input2, so that the first voltage signal terminal V1 and the second voltage signal terminal V2 charge the pull-up node PU together.

In a first period of the output phase, which may be defined as a first output phase t3, the second Input signal terminal Input2 controls the second Input sub-circuit 11 to be turned on, and the voltage of the pull-up node PU is compensated for charging, so that the driving output sub-circuit 12 is turned on, and the scan signal of the clock signal terminal C is output via the driving signal output terminal Gout.

In the second period of the output phase, which may be defined as the second output phase t4, the second Input signal terminal Input2 controls the second Input sub-circuit 11 to be turned off, stops the compensation charging of the voltage of the pull-up node PU, and maintains the driving output sub-circuit 12 to be turned on, and the scan signal of the clock signal terminal C is output via the driving signal output terminal Gout. Wherein the total duration of the first time period and the second time period is equal to the duration of the output phase.

Fig. 6 is a schematic diagram of a topology of another embodiment of the GOA circuit of the present invention, as shown in fig. 6, the GOA circuit of the present embodiment may further include a reset sub-circuit 13, a pull-down sub-circuit 14, a pull-down control sub-circuit 15, a carry-out sub-circuit 16, a tank sub-circuit 17, and a discharge sub-circuit 18.

A first end of the reset sub-circuit 13 is electrically connected with a second end of the first input sub-circuit 10, a second end of the reset sub-circuit 13 is electrically connected with a third voltage signal end V3, and a first control end of the reset sub-circuit 13 is electrically connected with a first reset end R1; the second control terminal of the reset sub-circuit 13 is electrically connected to the second reset terminal R2.

The node connection end of the pull-down sub-circuit 14 is electrically connected to the pull-down node PD of the pull-down control sub-circuit 15, the pull-down end of the pull-down sub-circuit 14 is electrically connected to the third voltage signal end V3, and the control end of the pull-down sub-circuit 14 is electrically connected to the pull-up node PU.

The first end of the pull-down control sub-circuit 15 is electrically connected to the pull-up node PU, the second end of the pull-down control sub-circuit 15 is electrically connected to the third voltage signal end V3, the voltage Input end of the pull-down control sub-circuit 15 is electrically connected to the control voltage signal end V4, and the control end of the pull-down control sub-circuit 15 is electrically connected to the first Input signal end Input 1.

The first end of the carry-out sub-circuit 16 is electrically connected to the first end of the driving output sub-circuit 12, the second end of the carry-out sub-circuit 16 is electrically connected to the third voltage signal end V3, the third end of the carry-out sub-circuit 16 is electrically connected to the carry signal output end gout_c, the pull-up node control end of the carry-out sub-circuit 16 is electrically connected to the pull-up node PU, and the pull-down node control end of the carry-out sub-circuit 16 is electrically connected to the pull-down node PD of the pull-down control sub-circuit 15.

A first end of the tank sub-circuit 17 is electrically connected to the pull-up node PU, and a first end of the tank sub-circuit 17 is electrically connected to the driving signal output terminal Gout.

The first end of the discharging sub-circuit 18 is electrically connected to the driving signal output terminal Gout, the second end of the discharging sub-circuit 18 is electrically connected to the fourth voltage signal terminal V5, the discharging control end of the discharging sub-circuit 18 is electrically connected to the first reset end R1, and the pull-down node control end of the discharging sub-circuit 18 is electrically connected to the pull-down node PD of the pull-down control sub-circuit 15. The fourth voltage signal terminal V5 outputs the VGL signal.

Fig. 7 is a schematic diagram of a specific structure of the GOA circuit shown in fig. 6, and in this embodiment, the reset sub-circuit 13 includes a first transistor M1 and a second transistor M2 as shown in fig. 7.

The first pole of the first transistor M1 and the first pole of the second transistor M2 are commonly used as a first terminal of the reset sub-circuit 13, the second pole of the first transistor M1 and the second pole of the second transistor M2 are commonly used as a second terminal of the reset sub-circuit 13, the control pole of the first transistor M1 is used as a first control terminal of the reset sub-circuit 13, and the control pole of the second transistor M2 is used as a second control terminal of the reset sub-circuit 13.

A first pole of the first transistor M1 and a first pole of the second transistor M2 are electrically connected to the second terminal of the first input sub-circuit 10, a second pole of the first transistor M1 and a second pole of the second transistor M2 are electrically connected to the third voltage signal terminal V3, and a control pole of the first transistor M1 is electrically connected to the first reset terminal R1; the control electrode of the second transistor M2 is electrically connected to the second reset terminal R2. The third voltage signal terminal V3 outputs the LVGL signal. The first Reset terminal R1 outputs a Reset signal, and the second Reset terminal R2 outputs a T-RST signal.

In a specific implementation, the pull-down node PD of the pull-down control sub-circuit 15 includes a first sub-pull-down node PD1 and a second sub-pull-down node PD2, the voltage input terminal of the pull-down control sub-circuit 15 includes a first sub-voltage input terminal and a second sub-voltage input terminal, the control voltage signal terminal V4 includes a first sub-control voltage signal terminal V41 (which outputs a VDDA signal) and a second sub-control voltage signal terminal V42 (which outputs a VDDB signal, where the VDDB signal and the VDDA signal are two signals with opposite levels, i.e., when the VDDA signal is high, the VDDB signal is low, and when the VDDB signal is low, the node connection terminal of the pull-down sub-circuit 14 includes a first sub-node connection terminal and a second sub-node connection terminal. The pull-down node control end of the carry-out sub-circuit 16 comprises a first sub-pull-down node control end and a second sub-pull-down node control end; the pull-down node control terminals of the discharging sub-circuit 18 include a third sub-pull-down node control terminal and a fourth sub-pull-down node control terminal.

In one specific implementation, as shown in fig. 7, the pull-down subcircuit 14 includes a third transistor M3 and a fourth transistor M4.

The first pole of the third transistor M3 is used as the first sub-node connection terminal, the first pole of the fourth transistor M4 is used as the second sub-node connection terminal, the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are used as the pull-down terminal of the pull-down sub-circuit 14, and the control pole of the third transistor M3 and the control pole of the fourth transistor M4 are used as the control terminal of the pull-down sub-circuit 14.

A first pole of the third transistor M3 is electrically connected to the first sub-pull-down node PD1, and a first pole of the fourth transistor M4 is electrically connected to the second sub-pull-down node PD2; the second pole of the third transistor M3 and the second pole of the fourth transistor M4 are electrically connected to the third voltage signal terminal V3, and the control pole of the third transistor M3 and the control pole of the fourth transistor M4 are electrically connected to the pull-up node PU.

In one specific implementation, as shown in fig. 7, the pull-down control sub-circuit 15 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10;

the first pole of the fifth transistor M5, the control pole of the sixth transistor M6, and the second pole of the ninth transistor M9 are used together as the first sub-pull-down node PD1; the first pole of the seventh transistor M7, the control pole of the eighth transistor M8, and the second pole of the tenth transistor M10 are used together as the second sub-pull-down node PD2;

The first pole of the sixth transistor M6 and the first pole of the eighth transistor M8 together serve as the first terminal of the pull-down control sub-circuit 15; the second pole of the fifth transistor M5, the second pole of the sixth transistor M6, the second pole of the seventh transistor M7, and the second pole of the eighth transistor M8 are used together as the second terminal of the pull-down control sub-circuit 15; a first pole of the ninth transistor M9 and a control pole of the ninth transistor M9 are commonly used as the first voltage sub-input terminal; a first pole of the tenth transistor M10 and a control pole of the tenth transistor M10 are commonly used as the second voltage sub-input terminal; the control electrode of the fifth transistor M5 and the control electrode of the seventh transistor M7 are commonly used as the control terminal of the pull-down control sub-circuit 15;

the first pole of the fifth transistor M5, the control pole of the sixth transistor M6, and the second pole of the ninth transistor M9 are electrically connected to the first sub-node connection terminal of the pull-down sub-circuit 14;

the first pole of the seventh transistor M7, the control pole of the eighth transistor M8, and the second pole of the tenth transistor M10 are electrically connected to the second sub-node connection terminal of the pull-down sub-circuit 14;

The first pole of the sixth transistor M6 and the first pole of the eighth transistor M8 are electrically connected together to the pull-up node PU;

the second pole of the fifth transistor M5, the second pole of the sixth transistor M6, the second pole of the seventh transistor M7, and the second pole of the eighth transistor M8 are electrically connected to the third voltage signal terminal V3;

the control electrode of the fifth transistor M5 and the control electrode of the seventh transistor M7 are electrically connected to the first Input signal terminal Input1 in common;

the first voltage sub-input terminal is electrically connected to the first sub-control voltage signal terminal V41, and the second voltage sub-input terminal is electrically connected to the second sub-control voltage signal terminal V42.

In one implementation, as shown in fig. 7, the carry-out sub-circuit 16 includes an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13; the discharging sub-circuit 18 includes a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16;

a first pole of the eleventh transistor M11 serves as a first terminal of the carry-out sub-circuit 16; the second pole of the twelfth transistor M12 and the second pole of the thirteenth transistor M13 are commonly used as the second terminal of the carry-out sub-circuit 16; the second pole of the eleventh transistor M11, the first pole of the twelfth transistor M12, and the first pole of the thirteenth transistor M13 are commonly used as the third terminal of the carry-out sub-circuit 16; the control electrode of the eleventh transistor M11 is used as a control end of a pull-up node of the carry output sub-circuit 16; the control electrode of the twelfth transistor M12 is used as the control end of the first sub-pull-down node, and the control electrode of the thirteenth transistor M13 is used as the control end of the second sub-pull-down node;

The first pole of the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 together serve as a first terminal of the discharging sub-circuit 18; the second pole of the fourteenth transistor M14, the second pole of the fifteenth transistor M15, and the second pole of the sixteenth transistor M16 are used together as the second terminal of the discharging sub-circuit 18; the control electrode of the fourteenth transistor M14 serves as a discharge control terminal of the discharge sub-circuit 18; a control electrode of the fifteenth transistor M15 is used as the third sub-pull-down node control terminal, and a control electrode of the sixteenth transistor M16 is used as the fourth sub-pull-down node control terminal;

a first pole of the eleventh transistor M11 is electrically connected to the first terminal of the drive output sub-circuit 12;

the second pole of the twelfth transistor M12 and the second pole of the thirteenth transistor M13 are electrically connected to the third voltage signal terminal V3 in common;

the second pole of the eleventh transistor M11, the first pole of the twelfth transistor M12, and the first pole of the thirteenth transistor M13 are electrically connected to the carry signal output terminal gout_c in common;

a control electrode of the eleventh transistor M11 is electrically connected to the pull-up node PU, a control electrode of the twelfth transistor M12 is electrically connected to the first sub-pull-down node PD1, and a control electrode of the thirteenth transistor M13 is electrically connected to the second sub-pull-down node PD 2;

The first pole of the fourteenth transistor M14, the first pole of the fifteenth transistor M15, and the first pole of the sixteenth transistor M16 are electrically connected in common to the driving signal output terminal Gout;

the second pole of the fourteenth transistor M14, the second pole of the fifteenth transistor M15, and the second pole of the sixteenth transistor M16 are electrically connected to the fourth voltage signal terminal V5 in common;

the control electrode of the fourteenth transistor M14 is electrically connected with the first reset terminal R1;

the control electrode of the fifteenth transistor M15 is electrically connected to the control terminal of the third sub-pull-down node, and the control electrode of the sixteenth transistor M16 is electrically connected to the control terminal of the fourth sub-pull-down node.

In one implementation, as shown in fig. 7, the first input sub-circuit 10 includes a seventeenth transistor M17, the second input sub-circuit 11 includes a nineteenth transistor M19, and the driving output sub-circuit 12 includes an eighteenth transistor.

A first pole of the seventeenth transistor M17 is used as a first terminal of the first input sub-circuit 10, a second pole of the seventeenth transistor M17 is used as a second terminal of the first input sub-circuit 10, and a control pole of the seventeenth transistor M17 is used as a control terminal of the first input sub-circuit 10.

A first pole of the nineteenth transistor M19 is used as the first terminal of the second input sub-circuit 11, a second pole of the nineteenth transistor M19 is used as the second terminal of the second input sub-circuit 11, and a control pole of the nineteenth transistor M19 is used as the first control terminal of the second input sub-circuit 11.

A first pole of the eighteenth transistor is used as a first terminal of the driving output sub-circuit 12, a second pole of the eighteenth transistor is used as a second terminal of the driving output sub-circuit 12, and a control pole of the eighteenth transistor is used as a first control terminal of the driving output sub-circuit 12.

The control electrode of the seventeenth transistor M17 is electrically connected to the first Input signal terminal Input1, the first electrode of the seventeenth transistor M17 is electrically connected to the first voltage signal terminal V1, and the second electrode of the seventeenth transistor M17 is electrically connected to the control electrode of the eighteenth transistor.

The control electrode of the nineteenth transistor M19 is electrically connected to the second Input signal terminal Input2, the first terminal of the nineteenth transistor M19 is electrically connected to the second voltage signal terminal V2, and the second terminal of the nineteenth transistor M19 is electrically connected to the control electrode of the eighteenth transistor.

The first terminal of the eighteenth transistor is electrically connected to the clock signal terminal C, and the second terminal of the eighteenth transistor is electrically connected to the driving signal output terminal Gout.

FIG. 8 is a schematic diagram illustrating a connection of the odd-even row interleaved driving scheme of FIG. 7, wherein the Input1 signal is provided by Gn-4 and the Input2 signal is provided by Gn-1 as shown in FIG. 2.

FIG. 9 is a timing diagram of the clock signals corresponding to FIG. 8. STV represents the initial signal, CLK1-CLK8 being the signal from clock signal terminal C.

FIG. 10 is a timing diagram of Gn-4, gn-3, gn-2, gn-1, gn (PU) and Gn (out).

The working principle of the GOA circuit of this embodiment is as follows:

in the first Input stage t1, input1 (Gn-4) is high, seventeenth transistor M17 is turned on, pull-up node PU is charged, and pull-down node PD is pulled low;

in the second Input phase t2, input2 (Gn-1) is high and there is a quarter overlap with Input1 (Gn-4), seventeenth transistor M17 is turned on simultaneously with nineteenth transistor M19, pull-up node PU is charged, and pull-down node PD is pulled low;

in the first output stage t3, input1 (Gn-4) is low, input2 (Gn-1) is high, the clock signal CLK is high, the seventeenth transistor M17 is turned off, the nineteenth transistor M19 is turned on, the eighteenth transistor M18 is turned on, the pull-up node PU is continuously charged, and the pull-down node PD is continuously pulled low;

In the second output stage t4, input2 (Gn-1) is low, the clock signal CLK is high, the nineteenth transistor M19 is turned off, the eighteenth transistor M18 is turned on, and the pull-up node PU is pulled up again by bootstrap of the first capacitor in the tank sub-circuit 17;

in the reset phase, the clock signal CLK is at a low level, the eighteenth transistor M18 is turned off, the pull-up node PU is turned on when the potential of the pull-up node PU falls back and gn+6 (REST) is high, the pull-up node PU is pulled down, the pull-down node PD is turned on by turns the ninth transistor M9 and the tenth transistor M10, the pull-down node PD is raised, and the carry signal output terminal gout_c and the driving signal output terminal Gout are pulled down.

Fig. 11 is a schematic diagram of another specific structure of the GOA circuit shown in fig. 6, and as shown in fig. 11, the difference between the GOA circuit shown in fig. 7 and the embodiment is that: the pull-down node PD of the pull-down control sub-circuit 15 includes a first sub-pull-down node PD1, the voltage input terminal of the pull-down control sub-circuit 15 includes a first sub-voltage input terminal, the control voltage signal terminal V4 includes a first sub-control voltage signal terminal V41, and the node connection terminal of the pull-down sub-circuit 14 includes a first sub-node connection terminal. The control end of the pull-down node of the carry-out sub-circuit 16 comprises a first sub-pull-down node control end; the pull-down node control terminal of the discharge sub-circuit 18 includes a third sub-pull-down node control terminal.

As shown in fig. 11, the pull-down subcircuit 14 includes a third transistor M3. A first pole of the third transistor M3 is used as the first sub-node connection terminal; a second pole of the third transistor M3 serves as a second terminal of the pull-down sub-circuit 14; the control electrode of the third transistor M3 serves as the control terminal of the pull-down subcircuit 14.

A first pole of the third transistor M3 is electrically connected to the first sub-pull-down node PD1, a second pole of the third transistor M3 is electrically connected to the third voltage signal terminal V3, and a control pole of the third transistor M3 is electrically connected to the pull-up node PU.

As shown in fig. 11, the pull-down control sub-circuit 15 includes a fifth transistor M5, a sixth transistor M6, and a ninth transistor M9.

The first pole of the fifth transistor M5, the control pole of the sixth transistor M6, and the second pole of the ninth transistor M9 are used together as the first sub-pull-down node PD1;

a first pole of the sixth transistor M6 serves as a first terminal of the pull-down control sub-circuit 15; the second pole of the fifth transistor M5 and the second pole of the sixth transistor M6 are commonly used as the second terminal of the pull-down control sub-circuit 15; a first pole of the ninth transistor M9 and a control pole of the ninth transistor M9 are commonly used as the first voltage sub-input terminal; a control electrode of the fifth transistor M5 is used as a control terminal of the pull-down control sub-circuit 15;

a first pole of the sixth transistor M6 is electrically connected to the pull-up node PU;

the second pole of the fifth transistor M5 and the second pole of the sixth transistor M6 are electrically connected to the third voltage signal terminal V3 together;

the control electrode of the fifth transistor M5 is electrically connected to the first Input signal terminal Input 1;

the first voltage sub-input terminal is electrically connected to the first sub-control voltage signal terminal V41.

As shown in fig. 11, the carry out sub-circuit 16 includes an eleventh transistor M11 and a twelfth transistor M12; the discharging sub-circuit 18 includes a fourteenth transistor M14 and a fifteenth transistor M15;

a first pole of the eleventh transistor M11 serves as a first terminal of the carry-out sub-circuit 16; a second pole of the twelfth transistor M12 serves as a second terminal of the carry-out sub-circuit 16; the second pole of the eleventh transistor M11 and the first pole of the twelfth transistor M12 are commonly used as the third terminal of the carry-out sub-circuit 16; the control electrode of the eleventh transistor M11 is used as a control end of a pull-up node of the carry output sub-circuit 16; the control electrode of the twelfth transistor M12 is used as the control end of the first sub pull-down node;

The first pole of the fourteenth transistor M14 and the first pole of the fifteenth transistor M15 together serve as a first terminal of the discharging sub-circuit 18; the second pole of the fourteenth transistor M14 and the second pole of the fifteenth transistor M15 are commonly used as the second terminal of the discharging electronic circuit 18; the control electrode of the fourteenth transistor M14 serves as a discharge control terminal of the discharge sub-circuit 18; the control electrode of the fifteenth transistor M15 is used as the control end of the third sub pull-down node;

a second pole of the twelfth transistor M12 is electrically connected to the third voltage signal terminal V3;

the second pole of the eleventh transistor M11 and the first pole of the twelfth transistor M12 are electrically connected to the carry signal output terminal gout_c in common;

a control electrode of the eleventh transistor M11 is electrically connected to the pull-up node PU, and a control electrode of the twelfth transistor M12 is electrically connected to the first sub-pull-down node PD 1;

the first pole of the fourteenth transistor M14 and the first pole of the fifteenth transistor M15 are electrically connected in common to the driving signal output terminal Gout;

The second pole of the fourteenth transistor M14 and the second pole of the fifteenth transistor M15 are electrically connected to the fourth voltage signal terminal V5 in common;

the control electrode of the fifteenth transistor M15 is electrically connected to the control terminal of the third sub-pull-down node.

The difference in this embodiment with respect to the GOA circuit shown in fig. 7 is that part of the transistors are reduced, thereby saving volume and cost.

Fig. 12 is a schematic diagram of another specific structure of the GOA circuit shown in fig. 6, and as shown in fig. 12, the difference between the GOA circuit shown in fig. 7 and the present embodiment is that: the first Input signal terminal Input1 and the first voltage signal terminal V1 are the same signal terminal, and/or the second Input signal terminal Input2 and the second voltage signal terminal V2 are the same signal terminal. Please refer to the description of the GOA circuit related to fig. 7 for other structures and connection relationships, and the description thereof is omitted herein.

The invention also provides a driving method of the GOA circuit, which is applied to the GOA circuit of the embodiment, and the driving method of the GOA circuit specifically comprises the following steps:

in a first period of the output stage, the second Input signal terminal Input2 controls the second Input sub-circuit 11 to be turned on, and the voltage of the pull-up node PU is compensated and charged, so that the driving output sub-circuit 12 is turned on, and the scan signal of the clock signal terminal C is output via the driving signal output terminal Gout;

In a second period of the output stage, the second Input signal terminal Input2 controls the second Input sub-circuit 11 to be turned off, stops compensating the voltage of the pull-up node PU, and maintains the driving output sub-circuit 12 to be turned on, and the scan signal of the clock signal terminal C is output via the driving signal output terminal Gout;

In a specific implementation process, the signal Input by the first Input signal terminal Input1 leads the signal Input by the second Input signal terminal Input2, and there is a partial overlapping waveform between the signal Input by the first Input signal terminal Input1 and the signal Input by the second Input signal terminal Input2, before the output stage, the method further includes:

in a first Input stage t1, the first Input sub-circuit 10 is controlled to be turned on through the first Input signal terminal Input1, so that the first voltage signal terminal V1 charges the pull-up node PU;

The method of the foregoing embodiment is used to implement the corresponding GOA circuit in the foregoing embodiment, and specific implementation schemes thereof may be referred to the GOA circuit described in the foregoing embodiment and related descriptions in the GOA circuit embodiment, and have the beneficial effects of the corresponding method embodiment, which are not described herein.

The invention also provides a display panel which comprises the GOA circuit described in the embodiment.

The invention also provides a display device which comprises the display panel disclosed by the embodiment.

It is to be understood that the same or similar parts in the above embodiments may be referred to each other, and that in some embodiments, the same or similar parts in other embodiments may be referred to.

It should be noted that in the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. Furthermore, in the description of the present invention, unless otherwise indicated, the meaning of "plurality" means at least two.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention are disclosed above, the embodiments are only used for the convenience of understanding the present invention, and are not intended to limit the present invention. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is still subject to the scope of the present disclosure as defined by the appended claims.

Claims

1. A GOA circuit comprising a first input sub-circuit, a second input sub-circuit, and a drive output sub-circuit;

2. The GOA circuit of claim 1, wherein the signal input by the first input signal terminal leads the signal input by the second input signal terminal, and wherein a partially overlapping waveform exists between the signal input by the first input signal terminal and the signal input by the second input signal terminal.

3. The GOA circuit of claim 1, wherein the first voltage signal terminal and the second voltage signal terminal are the same voltage signal terminal.

4. The GOA circuit of claim 1, wherein the first input signal terminal and the first voltage signal terminal are the same signal terminal and/or the second input signal terminal and the second voltage signal terminal are the same signal terminal.

5. The GOA circuit of claim 1, further comprising a reset sub-circuit, a pull-down control sub-circuit, a carry-out sub-circuit, a power storage sub-circuit, and a discharge sub-circuit;

The first end of the reset sub-circuit is electrically connected with the second end of the first input sub-circuit, the second end of the reset sub-circuit is electrically connected with the third voltage signal end, and the first control end of the reset sub-circuit is electrically connected with the first reset end; the second control end of the reset sub-circuit is electrically connected with the second reset end;

the node connection end of the pull-down sub-circuit is electrically connected with the pull-down node of the pull-down control sub-circuit, the pull-down end of the pull-down sub-circuit is electrically connected with the third voltage signal end, and the control end of the pull-down sub-circuit is electrically connected with the control end of the drive output sub-circuit;

the first end of the pull-down control sub-circuit is electrically connected with the control end of the driving output sub-circuit, the second end of the pull-down control sub-circuit is electrically connected with the third voltage signal end, the voltage input end of the pull-down control sub-circuit is electrically connected with the control voltage signal end, and the control end of the pull-down control sub-circuit is electrically connected with the first input signal end;

the first end of the carry output sub-circuit is electrically connected with the first end of the driving output sub-circuit, the second end of the carry output sub-circuit is electrically connected with the third voltage signal end, the third end of the carry output sub-circuit is electrically connected with the carry signal output end, the control end of the pull-up node of the carry output sub-circuit is electrically connected with the control end of the driving output sub-circuit, and the control end of the pull-down node of the carry output sub-circuit is electrically connected with the pull-down node of the pull-down control sub-circuit;

The first end of the energy storage sub-circuit is electrically connected with the control end of the driving output sub-circuit, and the first end of the energy storage sub-circuit is electrically connected with the driving signal output end;

the first end of the discharging sub-circuit is electrically connected with the driving signal output end, the second end of the discharging sub-circuit is electrically connected with the fourth voltage signal end, the discharging control end of the discharging sub-circuit is electrically connected with the first reset end, and the pull-down node control end of the discharging sub-circuit is electrically connected with the pull-down node of the pull-down control sub-circuit.

6. The GOA circuit of claim 5, wherein the reset sub-circuit comprises a first transistor and a second transistor;

the first pole of the first transistor and the first pole of the second transistor are used as the first end of a reset sub-circuit, the second pole of the first transistor and the second pole of the second transistor are used as the second end of the reset sub-circuit, the control pole of the first transistor is used as the first control end of the reset sub-circuit, and the control pole of the second transistor is used as the second control end of the reset sub-circuit;

the first electrode of the first transistor and the first electrode of the second transistor are electrically connected with the second end of the first input sub-circuit in common, the second electrode of the first transistor and the second electrode of the second transistor are electrically connected with a third voltage signal end in common, and the control electrode of the first transistor is electrically connected with a first reset end; the control electrode of the second transistor is electrically connected with the second reset end.

7. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node and a second sub-pull-down node, the node connection of the pull-down sub-circuit comprising a first sub-node connection and a second sub-node connection;

the pull-down subcircuit includes a third transistor and a fourth transistor;

a first pole of the third transistor is used as the first sub-node connecting end, a first pole of the fourth transistor is used as the second sub-node connecting end, a second pole of the third transistor and a second pole of the fourth transistor are used as the pull-down end of the pull-down sub-circuit together, and a control pole of the third transistor and a control pole of the fourth transistor are used as the control end of the pull-down sub-circuit together;

a first pole of the third transistor is electrically connected with the first sub-pull-down node, and a first pole of the fourth transistor is electrically connected with the second sub-pull-down node; the second pole of the third transistor and the second pole of the fourth transistor are electrically connected with the third voltage signal end in common, and the control pole of the third transistor and the control pole of the fourth transistor are electrically connected with the control end of the driving output sub-circuit in common.

8. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node, the node connection of the pull-down sub-circuit comprising a first sub-node connection;

the pull-down subcircuit includes a third transistor;

a first pole of the third transistor is used as the first sub-node connecting end; a second pole of the third transistor serves as a second end of the pull-down sub-circuit; the control electrode of the third transistor is used as the control end of the pull-down subcircuit;

the first pole of the third transistor is electrically connected with the first sub-pull-down node, the second pole of the third transistor is electrically connected with the third voltage signal end, and the control pole of the third transistor is electrically connected with the control end of the driving output sub-circuit.

9. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node and a second sub-pull-down node, the voltage input of the pull-down control sub-circuit comprises a first sub-voltage input and a second sub-voltage input, the control voltage signal terminal comprises a first sub-control voltage signal terminal and a second sub-control voltage signal terminal; the node connecting end of the pull-down sub-circuit comprises a first sub-node connecting end and a second sub-node connecting end;

The pull-down control sub-circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

a first pole of the fifth transistor, a control pole of the sixth transistor, and a second pole of the ninth transistor collectively function as the first sub-pull-down node; a first pole of the seventh transistor, a control pole of the eighth transistor, and a second pole of the tenth transistor collectively serve as the second sub-pull-down node;

a first pole of the sixth transistor and a first pole of the eighth transistor together serve as a first terminal of the pull-down control subcircuit; the second pole of the fifth transistor, the second pole of the sixth transistor, the second pole of the seventh transistor, and the second pole of the eighth transistor are commonly used as the second terminal of the pull-down control subcircuit; a first pole of the ninth transistor and a control pole of the ninth transistor are commonly used as a first voltage sub input terminal; a first pole of the tenth transistor and a control pole of the tenth transistor are commonly used as a second voltage sub input terminal; the control electrode of the fifth transistor and the control electrode of the seventh transistor are used as the control end of the pull-down control sub-circuit together;

The first pole of the fifth transistor, the control pole of the sixth transistor and the second pole of the ninth transistor are electrically connected with the first sub-node connection end of the pull-down sub-circuit together;

the first pole of the seventh transistor, the control pole of the eighth transistor and the second pole of the tenth transistor are electrically connected with the second sub-node connection end of the pull-down sub-circuit together;

the first pole of the sixth transistor and the first pole of the eighth transistor are electrically connected with the control end of the driving output sub-circuit together;

the second pole of the fifth transistor, the second pole of the sixth transistor, the second pole of the seventh transistor and the second pole of the eighth transistor are electrically connected with the third voltage signal terminal in common;

the control electrode of the fifth transistor and the control electrode of the seventh transistor are electrically connected with the first input signal end together;

the first voltage sub-input end is electrically connected with the first sub-control voltage signal end, and the second voltage sub-input end is electrically connected with the second sub-control voltage signal end.

10. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node, the voltage input of the pull-down control sub-circuit comprises a first sub-voltage input, and the control voltage signal terminal comprises a first sub-control voltage signal terminal; the node connection end of the pull-down sub-circuit comprises a first sub-node connection end;

The pull-down control subcircuit includes a fifth transistor, a sixth transistor, and a ninth transistor;

a first pole of the fifth transistor, a control pole of the sixth transistor, and a second pole of the ninth transistor collectively function as the first sub-pull-down node;

a first pole of the sixth transistor is used as a first end of the pull-down control subcircuit; the second pole of the fifth transistor and the second pole of the sixth transistor are commonly used as the second end of the pull-down control subcircuit; a first pole of the ninth transistor and a control pole of the ninth transistor are commonly used as a first voltage sub input terminal; a control electrode of the fifth transistor is used as a control end of the pull-down control sub-circuit;

a first pole of the sixth transistor is electrically connected with the control end of the driving output subcircuit;

the second pole of the fifth transistor and the second pole of the sixth transistor are electrically connected with the third voltage signal terminal together;

The control electrode of the fifth transistor is electrically connected with the first input signal end;

the first voltage sub-input terminal is electrically connected with the first sub-control voltage signal terminal.

11. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node and a second sub-pull-down node, and the pull-down node control terminal of the carry-out sub-circuit comprises a first sub-pull-down node control terminal and a second sub-pull-down node control terminal; the pull-down node control end of the discharging sub-circuit comprises a third sub-pull-down node control end and a fourth sub-pull-down node control end;

the carry out sub-circuit includes an eleventh transistor, a twelfth transistor, and a thirteenth transistor; the discharging sub-circuit includes a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

a first pole of the eleventh transistor is used as a first end of the carry output subcircuit; the second pole of the twelfth transistor is commonly used as the second end of the carry output subcircuit; the second pole of the eleventh transistor, the first pole of the twelfth transistor, and the first pole of the thirteenth transistor are commonly used as the third terminal of the carry-out sub-circuit; the control electrode of the eleventh transistor is used as a control end of a pull-up node of the carry output subcircuit; the control electrode of the twelfth transistor is used as the control end of the first sub-pull-down node, and the control electrode of the thirteenth transistor is used as the control end of the second sub-pull-down node;

A first pole of the fourteenth transistor, a first pole of the fifteenth transistor, and a first pole of the sixteenth transistor collectively serve as a first terminal of the discharging sub-circuit; the second pole of the fourteenth transistor, the second pole of the fifteenth transistor, and the second pole of the sixteenth transistor are used together as the second terminal of the discharging sub-circuit; a control electrode of the fourteenth transistor is used as a discharge control end of the discharge sub-circuit; a control electrode of the fifteenth transistor is used as the control end of the third sub-pull-down node, and a control electrode of the sixteenth transistor is used as the control end of the fourth sub-pull-down node;

a first pole of the eleventh transistor is electrically connected to the first terminal of the drive output subcircuit;

the second pole of the twelfth transistor is electrically connected with the third voltage signal end in common;

the second pole of the eleventh transistor, the first pole of the twelfth transistor, and the first pole of the thirteenth transistor are electrically connected in common to the carry signal output terminal;

a control electrode of the eleventh transistor is electrically connected with the control end of the driving output subcircuit, a control electrode of the twelfth transistor is electrically connected with the first sub-pull-down node, and a control electrode of the thirteenth transistor is electrically connected with the second sub-pull-down node;

The first pole of the fourteenth transistor, the first pole of the fifteenth transistor, and the first pole of the sixteenth transistor are electrically connected in common to the driving signal output terminal;

the second pole of the fourteenth transistor, the second pole of the fifteenth transistor and the second pole of the sixteenth transistor are electrically connected with the fourth voltage signal terminal in common;

the control electrode of the fourteenth transistor is electrically connected with the first reset end;

the control electrode of the fifteenth transistor is electrically connected with the control end of the third sub-pull-down node, and the control electrode of the sixteenth transistor is electrically connected with the control end of the fourth sub-pull-down node.

12. The GOA circuit of claim 5, wherein the pull-down node of the pull-down control sub-circuit comprises a first sub-pull-down node, and the pull-down node control terminal of the carry-out sub-circuit comprises a first sub-pull-down node control terminal; the pull-down node control end of the discharging sub-circuit comprises a third sub-pull-down node control end;

the carry out sub-circuit includes an eleventh transistor and a twelfth transistor; the discharging sub-circuit includes a fourteenth transistor and a fifteenth transistor;

A first pole of the eleventh transistor is used as a first end of the carry output subcircuit; a second pole of the twelfth transistor serves as a second end of the carry-out sub-circuit; the second pole of the eleventh transistor and the first pole of the twelfth transistor are commonly used as the third terminal of the carry output subcircuit; the control electrode of the eleventh transistor is used as a control end of a pull-up node of the carry output subcircuit; the control electrode of the twelfth transistor is used as the control end of the first sub pull-down node;

a first pole of the fourteenth transistor and a first pole of the fifteenth transistor are commonly used as a first terminal of the discharging sub-circuit; the second pole of the fourteenth transistor and the second pole of the fifteenth transistor are commonly used as the second end of the discharging sub-circuit; a control electrode of the fourteenth transistor is used as a discharge control end of the discharge sub-circuit; the control electrode of the fifteenth transistor is used as the control end of the third sub pull-down node;

a second pole of the twelfth transistor is electrically connected with the third voltage signal terminal;

The second pole of the eleventh transistor and the first pole of the twelfth transistor are electrically connected with the carry signal output end in common;

a control electrode of the eleventh transistor is electrically connected with the control end of the driving output subcircuit, and a control electrode of the twelfth transistor is electrically connected with the first sub-pull-down node;

a first electrode of the fourteenth transistor and a first electrode of the fifteenth transistor are electrically connected in common to the driving signal output terminal;

the second pole of the fourteenth transistor and the second pole of the fifteenth transistor are electrically connected with the fourth voltage signal terminal in common;

and the control electrode of the fifteenth transistor is electrically connected with the control end of the third sub pull-down node.

13. The GOA circuit of claim 1, wherein the first input sub-circuit comprises a seventeenth transistor, the second input sub-circuit comprises a nineteenth transistor, and the drive output sub-circuit comprises an eighteenth transistor;

a first pole of the seventeenth transistor is used as a first end of the first input sub-circuit, a second pole of the seventeenth transistor is used as a second end of the first input sub-circuit, and a control pole of the seventeenth transistor is used as a control end of the first input sub-circuit;

A first pole of the nineteenth transistor is used as a first end of the second input subcircuit, a second pole of the nineteenth transistor is used as a second end of the second input subcircuit, and a control pole of the nineteenth transistor is used as a first control end of the second input subcircuit;

a first pole of the eighteenth transistor is used as a first end of the driving output sub-circuit, a second pole of the eighteenth transistor is used as a second end of the driving output sub-circuit, and a control pole of the eighteenth transistor is used as a first control end of the driving output sub-circuit;

a control electrode of the seventeenth transistor is electrically connected with the first input signal end, a first electrode of the seventeenth transistor is electrically connected with the first voltage signal end, and a second electrode of the seventeenth transistor is electrically connected with the control electrode of the eighteenth transistor;

a control electrode of the nineteenth transistor is electrically connected with the second input signal terminal, a first end of the nineteenth transistor is electrically connected with the second voltage signal terminal, and a second end of the nineteenth transistor is electrically connected with the control electrode of the eighteenth transistor;

the first end of the eighteenth transistor is electrically connected with the clock signal end, and the second end of the eighteenth transistor is electrically connected with the driving signal output end.

14. A driving method of a GOA circuit, applied to a GOA circuit as claimed in any one of claims 1 to 13, comprising:

15. The method of driving a GOA circuit of claim 14, wherein the signal input from the first input signal terminal leads the signal input from the second input signal terminal, and wherein there is a partial overlap waveform between the signal input from the first input signal terminal and the signal input from the second input signal terminal, the method further comprising, prior to the output phase:

In a first input stage, the first input sub-circuit is controlled to be conducted through the first input signal end, so that the first voltage signal end charges a control end of the driving output sub-circuit;

in the second input stage, the first input sub-circuit is controlled to be conducted through the second input signal end, so that the first voltage signal end and the second voltage signal end charge the control end of the driving output sub-circuit together.

16. A display panel comprising the GOA circuit of any one of claims 1-13.

17. A display device comprising the display panel of claim 16.