CN114069583A - Electrostatic surge protection integrated circuit with bidirectional embedded MOS (Metal oxide semiconductor) tube and method - Google Patents

Electrostatic surge protection integrated circuit with bidirectional embedded MOS (Metal oxide semiconductor) tube and method Download PDF

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CN114069583A
CN114069583A CN202111472592.3A CN202111472592A CN114069583A CN 114069583 A CN114069583 A CN 114069583A CN 202111472592 A CN202111472592 A CN 202111472592A CN 114069583 A CN114069583 A CN 114069583A
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circuit
voltage
tube
nmos
resistor
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CN114069583B (en
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梁海莲
马琴玲
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Jiangnan University
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Jiangnan University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

The invention discloses an electrostatic surge protection integrated circuit with a bidirectional embedded MOS (metal oxide semiconductor) tube and a method, belonging to the field of electrostatic discharge and surge protection of integrated circuits. The integrated circuit includes: the device comprises a voltage stabilizing clamping circuit, an NMOS switch control circuit and a main current discharge circuit. The invention utilizes two voltage-stabilizing diodes to form a voltage-stabilizing clamping circuit, provides continuous and stable voltage for an NMOS switch control circuit in the integrated circuit, and avoids the problem of low area utilization rate caused by using an external power supply to provide control voltage; meanwhile, a large-current discharging path is provided by using the main current discharging circuit, so that the robustness of the circuit is enhanced. The integrated circuit has the advantages of high area efficiency, high starting speed, strong robustness to static electricity or surge, bidirectional static electricity or surge protection and the like, can be applied to a bidirectional data transceiving port and a communication port of the integrated circuit, and can also be applied to a power supply port or a plug-pull interface of electronic equipment with working voltage of 3-6V for forward and reverse power supply.

Description

Electrostatic surge protection integrated circuit with bidirectional embedded MOS (Metal oxide semiconductor) tube and method
Technical Field
The invention relates to an electrostatic surge protection integrated circuit with a bidirectional embedded MOS (metal oxide semiconductor) tube and a method, belonging to the field of electrostatic discharge and surge protection of integrated circuits.
Background
Electrostatic discharge (ESD) refers to the phenomenon of electrostatic charge transfer between objects at different potentials, typically occurring in a very short time, on the order of hundreds of nanoseconds; electrical Overstress (EOS) refers to an electrical damage phenomenon exceeding a normal operating voltage or current of a product, such as a long-time discharge or a large current surge (a lightning surge phenomenon). At present, ESD or EOS phenomena are a main cause of internal damage of integrated circuits and functional failure of electronic products.
With the rapid development of science and technology, the demands of people on the functions and performances of high-density Integrated Circuit (IC) chips such as handheld mobile devices, automotive electronics, personal PCs and mobile phones are increasingly raised, and the market demand of electronic products which are stable in system, excellent in performance and not easy to damage is increasingly prominent. Therefore, designing a high-performance electrostatic or surge protection integrated circuit chip with high performance, low parasitic, strong robustness and suitable for the requirements of portability or miniaturization of electronic products is an important research direction for improving the reliability of electronic products.
Since ESD is a bi-directional event, any arbitrary positive and negative polarity combination may occur between the two pins. At present, the one-way electrostatic or surge protection chip can only be used for interfaces in a forward voltage range, such as USB, HDMI and other forward voltage interfaces with digital signal input. The bidirectional electrostatic or surge protection chip can be used for any interface with a positive and negative voltage range due to the symmetrical positive and negative breakdown voltage, and for the single-channel bidirectional electrostatic or surge, the I/O and the ground can be flexibly connected to any pin. However, in the conventional bidirectional electrostatic or surge protection chip, two identical unidirectional electrostatic or surge protection chips are usually placed on one pipeline as a complementary circuit, and the load capacitance is doubled accordingly, so that it is necessary to design a bidirectional electrostatic or surge protection chip with bidirectional complementary characteristics without adding an additional load.
Common electrostatic or surge protection networks mainly include Diode (Diode), Bipolar Junction Transistor (BJT), Metal Oxide Semiconductor Field Effect Transistor (MOSFET), laterally and vertically diffused MOSFET (LDMOS/VDMOS), Silicon Controlled Rectifier (SCR), and other circuit units. The grounded-gate nmos (GGNMOS) mainly utilizes a parasitic triode circuit to dump the ESD current of a drain when ESD occurs, and although the grounded-gate nmos (GGNMOS) has the advantage of good process compatibility, the grounded-gate nmos (GGNMOS) may have the problems that the GGNMOS is not turned on, the gate oxide of an internal protected circuit is broken down first, or the grounded-gate nmos (GGNMOS) has higher ESD on-resistance and poor robustness. Similar to GGNMOS, gate-to-high pmos (gdpmos) also has the problems of higher on-resistance and poorer robustness. In the bi-directional case, the NMOS and PMOS usually add complementary circuits to implement bi-directional symmetrical function, which results in additional area, and if only a single NMOS or a single PMOS is used, an additional power port is needed to provide gate voltage, which is not suitable for single-channel bi-directional protection.
Disclosure of Invention
The invention provides an electrostatic surge protection integrated circuit with a bidirectional embedded MOS tube and a method thereof, aiming at solving the problems that the grid potential of the MOS tube is difficult to regulate and control, the robustness is poor, the protection efficiency is lower, the area efficiency is low and the like in the conventional bidirectional electrostatic surge protection integrated circuit.
The invention provides an electrostatic surge protection integrated circuit with a bidirectional embedded MOS tube, which comprises: the device comprises a voltage stabilizing clamping circuit, an NMOS switch control circuit and a main current discharge circuit;
the voltage stabilizing clamping circuit is used for controlling an NMOS tube M in the NMOS switch control circuitnA gate voltage, the NMOS transistor M being operated when a forward electrostatic discharge or surge transient pulse occurs at the first and second terminalsnThe upper grid voltage is equal to the first voltage-stabilizing tube D in the voltage-stabilizing clamping circuit1Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started can push the unit structure in the main current bleeder circuit, thereby forming a first PNP triode Tp1And NPN triode TnThe main current discharge path is formed;
when negative static discharge or surge transient pulse occurs at the first terminal and the second terminal, the NMOS tube MnThe upper grid voltage is equal to a second voltage-stabilizing tube D in the voltage-stabilizing clamping circuit2Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started can push the unit structure in the main current bleeder circuit, thereby forming a second PNP triode Tp2And the NPN triode TnThe main current discharge path is formed.
The voltage stabilizing clamp circuit comprises: first voltage regulator tube D1And a second voltage regulator tube D2The first voltage regulator tube D1Is connected to a second terminal of the circuit, the first voltage regulator tube D1And the second voltage-regulator tube D2Is connected with the cathode of the second voltage regulator tube D2Is connected to a first terminal of the circuit for clamping a port voltage of the circuit to avoid latch-up and for pushing the NMOS switch control circuit inside the circuit to start up.
The NMOS switch circuit comprises a first resistor R1And the NMOS tube MnThe NMOS tube MnAnd the first resistor R1Is connected to one end of the first resistor R1And the other end of the first voltage regulator tube D1And the second stabilivolt D2Is connected to the cathode of the first resistor R1Upper for limiting the NMOS transistor MnAnd is coupled to the NMOS transistor MnThe gate voltage of (1); the NMOS tube MnThe body electrode is connected with an internal structure unit in the main current discharge circuit and used for driving the main current discharge circuit to work;
the main current leakage circuit comprises the first PNP triode Tp1The NPN triode TnThe second PNP triode Tp2A second resistor R2And a third resistor R3Said second resistance R2And the first PNP triode Tp1Are all connected to a first terminal of said circuit, said second resistor R2And the first PNP triode Tp1Base electrode of (1), the NPN tube TnCollector electrodes of the NMOS transistors MnIs connected with the drain electrode of the first PNP triode Tp1The collector electrode of the second PNP triode Tp2Collector electrode of (1), the NPN tube TnBase electrodes of the NMOS transistors MnThe second PNP triode Tp2Base electrode of (1), the NPN tube TnEmitter of, said NMOS tube MnAnd the source electrode of the first resistor R and the third resistor R3Is connected to the second PNP transistor Tp2And said third resistor R3Are connected to a second terminal of the circuit for enhancing the robustness of the circuit.
The second objective of the present invention is to provide a method for electrostatic surge protection, which is implemented by using the electrostatic surge protection IC with the bidirectional embedded MOS transistor, and includes:
firstly, a voltage stabilizing clamping circuit is utilized to provide continuous and stable grid voltage for an NMOS tube in an NMOS switch control circuit in an IC; then, the current in the NMOS switch control circuit is used for pushing the SCR structure in the main current discharge circuit to be started, and the first PNP triode T in the main current discharge pathp1NPN triode TnAnd a second resistor R2A second PNP transistor T in the main current bleeder circuit for discharging forward electrostatic discharge or surge transient pulse between the first terminal and the second terminal of the circuitp2NPN triode TnAnd a second resistor R3The main current bleeder circuit is used for realizing the bidirectional electrostatic surge protection function of the circuit.
The invention has the beneficial effects that:
(1) in the embodiment of the invention, a first voltage regulator tube D1And a second voltage regulator tube D2A bidirectional voltage-stabilizing clamping circuit is formed, and when positive electrostatic discharge or surge transient pulse occurs between the first terminal and the second terminal, a second voltage-stabilizing tube D2Forward biased, first voltage regulator tube D1The circuit is used for clamping the port voltage of the example circuit of the invention, avoiding latch-up effect and pushing the NMOS switch control circuit inside the example circuit of the invention to start working; when negative electrostatic discharge or surge transient pulse occurs between the first terminal and the second terminal, the first voltage regulator tube D1Forward biased, second voltage regulator tube D2Port voltages for clamping the example circuit of the present invention; first voltage regulator tube D1And a firstTwo stabilivolt D2The bidirectional voltage-stabilizing clamping circuit is used for providing a bidirectional symmetrical first-stage protection circuit for a protected circuit and can effectively protect surge events with pulse time of at least 50 mu s.
(2) In the embodiment of the invention, the voltage stabilizing clamping circuit is an NMOS tube M in an NMOS switch control circuit after being startednThe gate electrode of (1) provides a continuous and stable potential to make the NMOS tube MnStarting and rapidly releasing current to improve surface current uniformity, and simultaneously, an NMOS transistor M in an NMOS switch control circuitnThe NMOS switch control circuit in the embodiment of the invention provides a bidirectional symmetrical second-stage protection circuit with controllable grid voltage for a protected circuit, and can effectively prevent an electrostatic discharge event with pulse time of 0.2ns-200 ns.
(3) In the embodiment of the invention, the first resistor R in the NMOS switch control circuit1The NMOS transistor can be adjusted or removed according to the characteristic requirements of an application circuit, and can also be arranged into a P-type MOS structure according to the manufacturing process of an integrated circuit.
(4) In the embodiment of the invention, after the NMOS switch circuit is started, the main current discharge circuit with bidirectional symmetry is pushed to be started, main static or surge pulse in the discharge circuit effectively enhances the robustness of the circuit, and the bidirectional static surge protection function is realized in a smaller area.
(5) The invention can be applied to a bidirectional data transceiving port and a communication port of an integrated circuit, and can also be applied to a power supply port or a plug-in interface of electronic equipment with forward and reverse power supply of working voltage between 3V and 6V.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a circuit diagram of an electrostatic surge protection IC with bidirectional embedded MOS transistors according to an embodiment of the present invention;
fig. 2 is a circuit diagram for the case of embedded PMOS in the example of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
the embodiment provides an electrostatic surge protection integrated circuit with a bidirectional embedded MOS tube, aiming at the problems that the grid potential of an MOS tube is difficult to regulate and control, the robustness is poor, the protection efficiency is lower, the area efficiency is low and the like in the conventional bidirectional electrostatic surge protection integrated circuit; the method comprises the following steps: the equivalent circuit diagram of the voltage stabilizing clamping circuit, the NMOS switch control circuit and the main current discharge circuit is shown in figure 1;
wherein steady voltage clamp circuit includes: first voltage regulator tube D1And a second voltage regulator tube D2The first voltage regulator tube D1Is connected to a second terminal of the circuit, the first voltage regulator tube D1And the second voltage-regulator tube D2Is connected with the cathode of the second voltage regulator tube D2Is connected to a first terminal of the circuit for clamping a port voltage of the circuit to avoid latch-up and for pushing the NMOS switch control circuit inside the circuit to start up.
The NMOS switch circuit includes a first resistor R1And the NMOS tube MnThe NMOS tube MnAnd the first resistor R1Is connected to one end of the first resistor R1And the other end of the first voltage regulator tube D1And the second stabilivolt D2Is connected to the cathode of the first resistor R1Upper for limiting the NMOS transistor MnAnd is coupled to the NMOS transistor MnThe gate voltage of (1); the NMOS tube MnThe body electrode is connected with an internal structure unit in the main current discharge circuit and used for driving the main current discharge circuit to work;
the main current discharge circuit comprises the firstPNP triode Tp1The NPN triode TnThe second PNP triode Tp2A second resistor R2And a third resistor R3Said second resistance R2And the first PNP triode Tp1Are all connected to a first terminal of said circuit, said second resistor R2And the first PNP triode Tp1Base electrode of (1), the NPN tube TnCollector electrodes of the NMOS transistors MnIs connected with the drain electrode of the first PNP triode Tp1The collector electrode of the second PNP triode Tp2Collector electrode of (1), the NPN tube TnBase electrodes of the NMOS transistors MnThe second PNP triode Tp2Base electrode of (1), the NPN tube TnEmitter of, said NMOS tube MnAnd the source electrode of the first resistor R and the third resistor R3Is connected to the second PNP transistor Tp2And said third resistor R3Are connected to a second terminal of the circuit for enhancing the robustness of the circuit.
Example two
This embodiment provides a static surge protection integrated circuit of two-way embedded MOS pipe, when positive electrostatic discharge or surge transient pulse take place for first terminal and second terminal, steady voltage clamp circuit opens, releases the static or surge current at first step, second regulator tube D2Forward biased, first voltage regulator tube D1The circuit is used for clamping the port voltage of the circuit of the embodiment of the invention and avoiding latch-up effect;
in this embodiment, the integrated circuit is a bidirectional symmetric electrostatic surge protection integrated circuit, and when a negative electrostatic discharge or surge transient pulse occurs at the first terminal and the second terminal, the voltage stabilizing and clamping circuit is turned on to discharge the initial electrostatic or surge current, and the first voltage regulator tube D is connected to the first voltage regulator tube D1Forward biased, second voltage regulator tube D2The bidirectional symmetrical voltage stabilizing and clamping circuit is used for clamping the port voltage of the circuit of the embodiment of the invention to avoid latch-up effect, and also provides controllable trigger voltage for the bidirectional symmetrical electrostatic surge protection integrated circuit of the embodiment;
when the voltage stabilizing clamping circuit is started, the static electricity or surge current flows through a first resistor R in the NMOS switch control circuit1Voltage drop is generated and the NMOS tube M is coupled thereinnGate voltage of (2) so that NMOS transistor MnStarting, fast discharging current and uniform surface current due to NMOS transistor M in NMOS switch control circuitnThe body electrode of the NMOS switch control circuit is connected with the internal structure unit of the main current bleeder circuit, so that the NMOS switch control circuit can be used for driving the main current bleeder circuit to work and discharging most of static electricity or surge pulse;
the SCR structure in the main current bleeder circuit is driven to be opened by the current in the NMOS switch control circuit, and a first PNP triode T in the main current bleeder pathp1NPN triode TnAnd a second resistor R2A second PNP transistor T in the main current bleeder circuit for discharging forward electrostatic discharge or surge transient pulse between the first terminal and the second terminal of the circuitp2NPN triode TnAnd a second resistor R3The main current leakage circuit is used for leakage of reverse electrostatic discharge or surge transient pulse generated between the first terminal and the second terminal of the circuit, and the main current leakage circuit can realize the bidirectional electrostatic surge protection function of the circuit and enhance the robustness of the electrostatic surge protection integrated circuit with the bidirectional embedded MOS tube.
The first resistor R1 of the NMOS switch control circuit can be adjusted or removed according to the circuit characteristic requirements of the actual application, and the NMOS transistor Mn in the switch circuit can also be configured as a P-type MOS structure according to the integrated circuit manufacturing process, and its equivalent circuit diagram is shown in fig. 2.
Example three:
the embodiment provides an electrostatic surge protection method, which is implemented by using an electrostatic surge protection IC of a bidirectional embedded MOS transistor described in the second embodiment, and the method includes:
the voltage stabilizing clamping circuit comprises two voltage stabilizing diodes and is used for stabilizing two voltagesThe cathode end of the diode is connected and used for controlling an NMOS tube M in the NMOS switch control circuitnA gate voltage, the NMOS transistor M being operated when a forward electrostatic discharge or surge transient pulse occurs at the first and second terminalsnThe upper grid voltage is equal to the first voltage-stabilizing tube D in the voltage-stabilizing clamping circuit1Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started can push the unit structure in the main current bleeder circuit, thereby forming a first PNP triode Tp1And NPN triode TnThe main current discharge path is formed;
when negative static discharge or surge transient pulse occurs at the first terminal and the second terminal, the NMOS tube MnThe upper grid voltage is equal to a second voltage-stabilizing tube D in the voltage-stabilizing clamping circuit2Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started can push the unit structure in the main current bleeder circuit, thereby forming a second PNP triode Tp2And the NPN triode TnThe main current discharge path is formed.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.

Claims (10)

1. The utility model provides an electrostatic surge protection integrated circuit of two-way embedded MOS pipe which characterized in that, the circuit includes: the device comprises a voltage stabilizing clamping circuit, an NMOS switch control circuit and a main current discharge circuit;
the voltage stabilizing clamping circuit is used for controlling an NMOS tube M in the NMOS switch control circuitnA gate voltage, when a forward electrostatic discharge or surge transient pulse occurs at the first terminal and the second terminal,the NMOS tube MnThe upper grid voltage is equal to the first voltage-stabilizing tube D in the voltage-stabilizing clamping circuit1Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started pushes the unit structure in the main current bleeder circuit, thereby forming a first PNP triode Tp1And NPN triode TnA main current discharge path;
when negative static discharge or surge transient pulse occurs at the first terminal and the second terminal, the NMOS tube MnThe upper grid voltage is equal to a second voltage-stabilizing tube D in the voltage-stabilizing clamping circuit2Upper clamping voltage for starting the NMOS transistor MnThe current in the NMOS switch control circuit after being started pushes the unit structure in the main current bleeder circuit, thereby forming a second PNP triode Tp2And the NPN triode TnThe main current leakage path is formed.
2. The circuit of claim 1, wherein the regulation clamp circuit comprises: first voltage regulator tube D1And a second voltage regulator tube D2The first voltage regulator tube D1The anode of the first voltage regulator tube D is connected with the second terminal1And the second voltage-regulator tube D2Is connected with the cathode of the second voltage regulator tube D2Is connected to the first terminal for clamping the port voltage of the circuit to avoid latch-up and for pushing the NMOS switch control circuit inside the circuit to start up.
3. The circuit of claim 1, wherein the NMOS switch control circuit comprises a first resistor R1And the NMOS tube MnThe NMOS tube MnAnd the first resistor R1Is connected to one end of the first resistor R1And the other end of the first voltage regulator tube D1And the second stabilivolt D2Is connected to the cathode of the first resistor R1Upper for limiting the NMOS transistor MnOfCurrent and coupling the NMOS tube MnThe gate voltage of (1); the NMOS tube MnThe body electrode is connected with an internal structure unit in the main current discharge circuit and used for driving the main current discharge circuit to work.
4. The circuit of claim 3, wherein the first resistor R in the NMOS switch control circuit1Adjusted or removed according to application circuit characteristic requirements.
5. The circuit of claim 3, wherein the NMOS transistor MnThe P-type MOS structure is provided according to the integrated circuit manufacturing process.
6. The circuit of claim 1, wherein the main current drain circuit comprises the first PNP transistor Tp1The NPN triode TnThe second PNP triode Tp2A second resistor R2And a third resistor R3Said second resistance R2And the first PNP triode Tp1The emitters of the first and second resistors R are all connected with the first terminal2And the first PNP triode Tp1Base electrode of (1), the NPN tube TnCollector electrodes of the NMOS transistors MnIs connected with the drain electrode of the first PNP triode Tp1The collector electrode of the second PNP triode Tp2Collector electrode of (1), the NPN tube TnBase electrodes of the NMOS transistors MnThe second PNP triode Tp2Base electrode of (1), the NPN tube TnEmitter of, said NMOS tube MnAnd the source electrode of the first resistor R and the third resistor R3Is connected to the second PNP transistor Tp2And said third resistor R3And the other end of the first terminal is connected with the second terminal for enhancing the robustness of the circuit.
7. The circuit of claim 4, wherein said main current bleeding circuitThe first PNP triode Tp1The NPN triode TnAnd a second resistor R2A second PNP transistor T for discharging forward electrostatic discharge or surge transient pulse between the first and second terminals, the second PNP transistor T in the main current discharge circuitp2The NPN triode TnAnd a second resistor R3And the main current leakage circuit is used for realizing the bidirectional electrostatic surge protection function of the circuit.
8. The circuit of claim 1 or 4, wherein the circuit is applied to an integrated circuit bi-directional data transceiving port and a communication port.
9. The circuit according to claim 1 or 4, wherein the circuit is applied to a power port or a plug interface of an electronic device with forward and reverse power supply and working voltage of 3V to 6V.
10. An electrostatic surge protection method, which is implemented by using the electrostatic surge protection integrated circuit with the bidirectional embedded MOS transistor as claimed in any one of claims 1 to 9, and which includes:
firstly, the voltage stabilizing clamping circuit is utilized to provide continuous and stable grid voltage for an NMOS tube in the NMOS switch control circuit in the integrated circuit;
then, the current in the NMOS switch control circuit is used for pushing an SCR structure in the main current bleeder circuit to be started, and a first PNP triode T in the main current bleeder circuitp1NPN triode TnAnd a second resistor R2The second terminal is used for discharging forward electrostatic discharge or surge transient pulse between the first terminal and the second terminal;
second PNP triode T in main current discharge circuitp2NPN triode TnAnd a second resistor R3And the second end is used for discharging reverse electrostatic discharge or surge transient pulse between the first end and the second end.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168283A (en) * 1999-12-03 2001-06-22 Matsushita Electronics Industry Corp Surge protection device
US20020097532A1 (en) * 2001-01-23 2002-07-25 Voldman Steven Howard Variable voltage threshold ESD protection
US20030193765A1 (en) * 2002-04-12 2003-10-16 Tohru Kitano Electrostatic breakdown prevention circuit for semiconductor device
JP2007214420A (en) * 2006-02-10 2007-08-23 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
CN101083263A (en) * 2006-05-31 2007-12-05 恩益禧电子股份有限公司 Semiconductor device including ESD protection field effect transistor with adjustable back gate potential
US20080048215A1 (en) * 2006-08-25 2008-02-28 Robert Bruce Davies Electrical stress protection apparatus and method of manufacture
US20080278872A1 (en) * 2007-05-10 2008-11-13 Vimicro Corporation Electrostatic Discharge Protection Circuit
CN203415975U (en) * 2013-08-20 2014-01-29 中国大唐集团财务有限公司 Two-way surge protection circuit
CN104134978A (en) * 2013-05-02 2014-11-05 飞思卡尔半导体公司 Electrostatic discharge (ESD) clamp circuit with high effective holding voltage
CN214412283U (en) * 2021-04-21 2021-10-15 西安市新雷能电子科技有限责任公司 Overvoltage surge suppression circuit with high-voltage input

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001168283A (en) * 1999-12-03 2001-06-22 Matsushita Electronics Industry Corp Surge protection device
US20020097532A1 (en) * 2001-01-23 2002-07-25 Voldman Steven Howard Variable voltage threshold ESD protection
US20030193765A1 (en) * 2002-04-12 2003-10-16 Tohru Kitano Electrostatic breakdown prevention circuit for semiconductor device
JP2007214420A (en) * 2006-02-10 2007-08-23 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
CN101083263A (en) * 2006-05-31 2007-12-05 恩益禧电子股份有限公司 Semiconductor device including ESD protection field effect transistor with adjustable back gate potential
US20080048215A1 (en) * 2006-08-25 2008-02-28 Robert Bruce Davies Electrical stress protection apparatus and method of manufacture
US20080278872A1 (en) * 2007-05-10 2008-11-13 Vimicro Corporation Electrostatic Discharge Protection Circuit
CN104134978A (en) * 2013-05-02 2014-11-05 飞思卡尔半导体公司 Electrostatic discharge (ESD) clamp circuit with high effective holding voltage
CN203415975U (en) * 2013-08-20 2014-01-29 中国大唐集团财务有限公司 Two-way surge protection circuit
CN214412283U (en) * 2021-04-21 2021-10-15 西安市新雷能电子科技有限责任公司 Overvoltage surge suppression circuit with high-voltage input

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
S. VOLDMAN.ETC.: "Electrostatic discharge protection in silicon-on-insulator technology", 《1999 IEEE INTERNATIONAL SOI CONFERENCE》 *

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