CN114068397A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN114068397A
CN114068397A CN202010771089.7A CN202010771089A CN114068397A CN 114068397 A CN114068397 A CN 114068397A CN 202010771089 A CN202010771089 A CN 202010771089A CN 114068397 A CN114068397 A CN 114068397A
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Prior art keywords
sac
substrate
layer
top surface
contact
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CN202010771089.7A
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张峰溢
林盈志
蔡尚元
苏廷锜
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Guangdong Hanqi Industrial Technology Research And Development Co ltd
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Guangdong Hanqi Industrial Technology Research And Development Co ltd
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Priority to CN202010771089.7A priority Critical patent/CN114068397A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate and a grid electrode inserted on the substrate; the side wall of the grid is covered with a spacing layer, and the part of the spacing layer above the substrate is covered with a first contact etching stop layer; a first groove is formed on the top surface of the grid in an etching mode, and a SAC head is formed in the first groove in a filling mode; the part of the substrate between the gates is covered with a second contact etching stop layer; the second contact etching stop layer is covered with a first interlayer dielectric layer; SAC sub-spacers are formed on the top surface of the first interlayer dielectric layer and on the sidewalls of the first contact etch stop layer; the semiconductor structure further includes a contact member; the contact member is in contact with the substrate, completely covers the top surface of the SAC sub-spacer, and covers part or all of the top surface of the SAC header. The semiconductor structure and the manufacturing method thereof have novel design and strong practicability.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
In order to achieve the purpose of reducing the chip size, a SAC (Self-Aligned Contact) process is used in the conventional semiconductor process. Referring to FIGS. 1-2, FIG. 1 is a schematic diagram illustrating a pre-contact step of a SAC process for a conventional semiconductor structure; fig. 2 is a schematic diagram showing a state of a contact step of the SAC process shown in fig. 1. The contact part may cause some damage to the SAC head during contact with the SAC head. The contact dimension x of the contact member with the SAC head in the horizontal direction is inversely proportional to the degree of damage y of the SAC head in the vertical direction, as shown in fig. 3. Therefore, it is required to develop a method of increasing a contact size of the contact member with the SAC head in a horizontal direction.
Disclosure of Invention
The present invention is directed to a semiconductor structure and a method for fabricating the same.
The technical scheme for solving the technical problem is as follows:
the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
step S1, providing an infrastructure; the basic structure comprises a substrate and a grid electrode inserted on the substrate; the base structure further includes a spacer layer overlying sidewalls of the gates, a first contact etch stop layer overlying portions of the spacer layer overlying the substrate, a second contact etch stop layer overlying portions of the substrate between the gates, and a first interlayer dielectric layer overlying the second contact etch stop layer; the top surface of the first interlayer dielectric layer is flush with the top surface of the grid;
step S2, etching to form a first groove on the top surface of the grid, and filling the first groove to form a SAC head; etching the top surface of the first interlayer dielectric layer to form a second groove; forming SAC sub-spacers in the second recess and on the first contact etch stop layer sidewalls; then forming a second interlayer dielectric layer to cover the SAC head, the spacer layer, the first contact etch stop layer, the SAC sub-spacer and the first interlayer dielectric layer;
step S3, etching a third groove from the top surface of the second interlayer dielectric layer to expose the portion of the substrate between the gates, the top surface of the SAC head and the SAC sub-spacer; and then filling metal in the third groove to form a contact part.
In the method for manufacturing a semiconductor structure of the present invention, in step S2, the step of forming SAC sub-spacers in the second recess and on the sidewalls of the first contact etch stop layer includes:
depositing and forming a SAC sublayer such that the SAC sublayer covers the SAC head, the spacer layer, the first contact etch stop layer, and the first interlayer dielectric layer; the SAC sublayer is then etched to leave portions thereof forming SAC sub-spacers.
In the above-described method for manufacturing a semiconductor structure of the present invention, the SAC sublayer 260 or the SAC sub-spacer 240 is formed using one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC, and a metal oxide; wherein the metal oxide is Al2O3、TiO2、HfO2Or ZrO.
In the method for fabricating a semiconductor structure of the present invention, the SAC sub-spacers are deposited by a conformal deposition method.
The invention also provides a semiconductor structure, which comprises a substrate and a grid electrode inserted on the substrate; the side wall of the grid is covered with a spacing layer, and the part of the spacing layer above the substrate is covered with a first contact etching stop layer; a first groove is formed on the top surface of the grid in an etching mode, and a SAC head is formed in the first groove in a filling mode;
the part of the substrate between the gates is covered with a second contact etching stop layer; the second contact etching stop layer is covered with a first interlayer dielectric layer; SAC sub-spacers are formed on the top surface of the first interlayer dielectric layer and on the sidewalls of the first contact etch stop layer;
the semiconductor structure further includes a contact member; the contact member is in contact with the substrate, completely covers the top surface of the SAC sub-spacer, and covers part or all of the top surface of the SAC header.
In the semiconductor structure of the invention, the SAC secondary spacer is formed by one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC and metal oxide; wherein the metal is oxidizedThe substance is Al2O3、TiO2、HfO2Or ZrO.
In the semiconductor structure of the present invention, the SAC sub-spacers are deposited by a conformal deposition method.
The semiconductor structure and the manufacturing method thereof of the invention increase the contact size of the contact part and the SAC head in the horizontal direction by adopting the SAC sub-spacer, and can effectively improve the damage degree of the SAC head. Meanwhile, the contact size of the contact member with the substrate may be determined by the size of the gate, the spacer layer, the first contact etch stop layer, the SAC sub-spacer, while also being controlled by the deposition thickness of the SAC sub-spacer. The semiconductor structure and the manufacturing method thereof have novel design and strong practicability.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
FIG. 1 is a schematic diagram illustrating a pre-contact step of a SAC process for a conventional semiconductor structure;
FIG. 2 is a schematic diagram showing a state of a contact step of the SAC process shown in FIG. 1;
FIG. 3 is a schematic view showing a relationship between a contact size x of a contact part and a SAC head in a horizontal direction and a damage degree y of the SAC head in a vertical direction in the SAC process shown in FIG. 1;
FIG. 4 is a schematic diagram showing a first step state of a method of fabricating a semiconductor structure in accordance with a preferred embodiment of the present invention;
FIG. 5 is a second step state diagram of the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 6 is a third step state diagram of the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 7 is a fourth step state diagram of the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 8 is a state diagram illustrating a fifth step in the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 9 is a state diagram illustrating a sixth step in the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 10 is a state diagram illustrating a seventh step in the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 11 is a state diagram illustrating an eighth step of the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 12 is a state diagram illustrating a ninth step in the method of fabricating the semiconductor structure shown in FIG. 4;
FIG. 13 is a state diagram illustrating a tenth step in the method of fabricating the semiconductor structure shown in FIG. 4;
fig. 14 is a schematic structural view of a semiconductor structure manufactured by the method of manufacturing the semiconductor structure shown in fig. 4.
Detailed Description
In order to make the technical purpose, technical solutions and technical effects of the present invention more clear and facilitate those skilled in the art to understand and implement the present invention, the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.
The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
step S1, providing the infrastructure 100, as shown in fig. 4; the base structure 100 includes a substrate 110 and a gate 120 interposed on the substrate 110; base structure 100 further includes a spacer layer 130 overlying sidewalls of gates 120, a first contact etch stop layer 140 overlying portions of spacer layer 130 above substrate 110, a second contact etch stop layer 150 overlying portions of substrate 110 between gates 120, and a first interlayer dielectric layer 160 overlying second contact etch stop layer 150; the top surface of the first interlayer dielectric layer 160 is flush with the top surface of the gate 120;
in this step, the spacer layer 130 may be made of the following materials: titanium, titanium nitride, tantalum nitride, manganese oxide, cobalt oxide, cobalt nitride, nickel oxide, nickel nitride, silicon carbide, oxygen doped silicon carbide, nitrogen doped silicon carbide, silicon nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, polymers such as polyimide, PBO, or combinations thereof.
The first contact etch stop layer 140 or the second contact etch stop layer 150 may be silicon nitride, silicon carbide, silicon oxide, a low-k dielectric (such as a carbon-doped oxide), an ultra-low-k dielectric (such as porous carbon-doped silicon dioxide), the like, or combinations thereof, and may be formed using CVD, PVD, ALD, a spin-on dielectric process, the like, or combinations thereof.
Step S2, forming a first groove 210 by etching on the top surface of the gate 120, as shown in fig. 5, and filling the first groove 210 with a SAC head 220, as shown in fig. 6; etching a second recess 230 on the top surface of the first interlayer dielectric layer 160, as shown in fig. 7; forming SAC sub-spacers 240 in the second grooves 230 and on the sidewalls of the first contact etch stop layer 140, as shown in fig. 8-9; then, a second interlayer dielectric layer 250 is formed such that the second interlayer dielectric layer 250 covers the SAC head 220, the spacer layer 130, the first contact etch stop layer 140, the SAC sub-spacers 240, and the first interlayer dielectric layer 160, as shown in fig. 10;
in this step, SAC sub-spacers 240 are deposited by conformal deposition.
Specifically, as shown in fig. 8-9, the step of forming SAC sub-spacers 240 in the second grooves 230 and on the sidewalls of the first contact etch stop layer 140 includes:
depositing a SAC sublayer 260 such that the SAC sublayer 260 covers the SAC head 220, the spacer layer 130, the first contact etch stop layer 140, and the first interlayer dielectric layer 160; the SAC sublayer 260 is then etched to leave portions thereof forming SAC sub-spacers 240.
Further, the SAC sublayer 260 or the SAC sub-spacer 240 may be formed using one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC, and metal oxide, and the material of the SAC sublayer 260 or the SAC sub-spacer 240 should have high selectivity to SiO 2; wherein the metal oxide is Al2O3、TiO2、HfO2Or ZrO.
Step S3, etching a third recess 300 from the top surface of the second ild 250 such that the portion of the substrate 110 between the gates 120, the top surface of the SAC head 220 and the SAC sub-spacer 240 are exposed, as shown in fig. 11-12; the third recess 300 is then filled with metal to form a contact member 400, as shown in fig. 13.
The contact part 400 may be made of tungsten, copper, aluminum, etc. or a combination thereof. The conductive layer 66 may be formed by a deposition process such as electrochemical plating, PVD, CVD, the like, or combinations thereof.
In this step, as shown in fig. 11 to 12, etching the third recess 300 from the top surface of the second interlayer dielectric layer 250 further includes:
arranging a photoresist 500 on the top of the second interlayer dielectric layer 250, and then transferring the pattern on the mask to the photoresist 500 in a manner that the mask is irradiated by ultraviolet light, thereby forming a pattern on the photoresist 500; dissolving the patterned portion of the photoresist 500 by a developing technique, thereby forming a hole 510 on the photoresist 500;
the portion of the top of the second ild layer 250 pointed by the hole 510 is processed by an etching process to form a third recess 300 in the top of the second ild layer 250, and the photoresist 500 is removed.
In the above-described method of manufacturing a semiconductor structure, the contact dimension of the contact member and the SAC head in the horizontal direction is increased by using the SAC sub-spacer, and the degree of damage of the SAC head can be effectively improved. Meanwhile, the contact size of the contact member with the substrate may be determined by the size of the gate, the spacer layer, the first contact etch stop layer, the SAC sub-spacer, while also being controlled by the deposition thickness of the SAC sub-spacer.
Further, as shown in fig. 13 and 14, the present invention also provides a semiconductor structure, including a substrate 110 and a gate 120 interposed on the substrate 110; the sidewall of the gate 120 is covered with a spacer 130, and the portion of the spacer 130 above the substrate 110 is covered with a first contact etch stop layer 140; a first groove 210 is etched on the top surface of the gate 120, and a SAC head 220 is filled in the first groove 210;
the portion of the substrate 110 between the gates 120 is covered with a second contact etch stop layer 150; the second contact etch stop layer 150 is covered with a first interlayer dielectric layer 160; SAC sub-spacers 240 are formed on the top surface of the first interlayer dielectric layer 160 and on the sidewalls of the first contact etch stop layer 140;
the semiconductor structure further includes a contact member 400; the contact member 400 is in contact with the substrate 110, completely covers the top surface of the SAC sub-spacer 240, and covers part or all of the top surface of the SAC head 220.
Wherein the SAC sub-spacer 240 is formed using one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC, and metal oxide; wherein the metal oxide is Al2O3、TiO2、HfO2Or ZrO.
The SAC sub-spacers 240 are deposited by a conformal deposition method.
As shown in fig. 14, in the above semiconductor structure, the contact dimension z of the contact member with the substrate may be determined by the dimensions of the gate, the spacer layer, the first contact etch stop layer, and the SAC sub-spacer, and specifically, in the embodiment shown in fig. 14, z ═ P- (a +2b +2 c).
It will be understood that modifications and variations can be made by persons skilled in the art in light of the above teachings and all such modifications and variations are intended to be included within the scope of the invention as defined in the appended claims.

Claims (7)

1. A method of fabricating a semiconductor structure, comprising the steps of:
step S1, providing an infrastructure (100); the base structure (100) comprises a substrate (110) and a gate (120) inserted on the substrate (110); the base structure (100) further comprises a spacer layer (130) overlying sidewalls of the gates (120), a first contact etch stop layer (140) overlying a portion of the spacer layer (130) above the substrate (110), a second contact etch stop layer (150) overlying a portion of the substrate (110) between the gates (120), and a first interlayer dielectric layer (160) overlying the second contact etch stop layer (150); the top surface of the first interlayer dielectric layer (160) is flush with the top surface of the grid electrode (120);
step S2, etching a first groove (210) on the top surface of the gate (120), and filling the first groove (210) with a SAC head (220); etching a second groove (230) on the top surface of the first interlayer dielectric layer (160); forming SAC sub-spacers (240) in the second recesses (230) and on the first contact etch stop layer (140) sidewalls; then forming a second interlayer dielectric layer (250) such that the second interlayer dielectric layer (250) covers the SAC head (220), the spacer layer (130), the first contact etch stop layer (140), the SAC sub-spacers (240), and the first interlayer dielectric layer (160);
step S3, etching a third trench (300) from the top surface of the second ild layer (250) to expose a portion of the substrate (110) between the gates (120), the top surface of the SAC head (220), and the SAC sub-spacer (240); then, the third groove (300) is filled with metal to form a contact member (400).
2. The method of manufacturing a semiconductor structure of claim 1, wherein in step S2, the step of forming SAC sub-spacers (240) in the second recess (230) and on the first contact etch stop layer (140) sidewalls comprises:
depositing a SAC sublayer (260) such that the SAC sublayer (260) covers the SAC head (220), the spacer layer (130), the first contact etch stop layer (140), and the first interlayer dielectric layer (160); the SAC sublayer (260) is then etched, leaving portions thereof forming SAC sub-spacers (240).
3. The method of manufacturing a semiconductor structure according to claim 2, wherein the SAC sublayer 260 or the SAC sub-spacer 240 is formed using one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC, and a metal oxide; wherein the metal oxide is Al2O3、TiO2、HfO2Or ZrO.
4. The method of claim 1, wherein the SAC sub-spacers (240) are deposited by a conformal deposition method.
5. A semiconductor structure is characterized by comprising a substrate (110) and a grid electrode (120) which is inserted on the substrate (110); the side wall of the gate (120) is covered by a spacer layer (130), and the part of the spacer layer (130) above the substrate (110) is covered by a first contact etching stop layer (140); a first groove (210) is formed on the top surface of the gate (120) in an etching way, and a SAC head (220) is filled in the first groove (210);
the part of the substrate (110) between the gates (120) is covered with a second contact etch stop layer (150); a first interlayer dielectric layer (160) is covered on the second contact etch stop layer (150); SAC sub-spacers (240) formed on the top surface of the first interlayer dielectric layer (160) and on the sidewalls of the first contact etch stop layer (140);
the semiconductor structure further comprises a contact member (400); the contact member (400) is in contact with the substrate (110), completely covers the top surface of the SAC subgasket (240), and covers part or all of the top surface of the SAC header (220).
6. The semiconductor structure of claim 5, wherein the SAC subgasket (240) is formed using one or more of SiN, SiON, SiOC, SiOCN, SiCN, SiC, and a metal oxide; wherein the metal oxide is Al2O3、TiO2、HfO2Or ZrO.
7. The semiconductor structure of claim 5, wherein the SAC sub-spacers (240) are deposited by a conformal deposition method.
CN202010771089.7A 2020-08-03 2020-08-03 Semiconductor structure and manufacturing method thereof Pending CN114068397A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049427A1 (en) * 2014-08-18 2016-02-18 Globalfoundries Inc. Integrated circuits with self aligned contact structures for improved windows and fabrication methods
TW201624711A (en) * 2014-12-26 2016-07-01 聯華電子股份有限公司 Semiconductor device and method of forming the same
CN107017297A (en) * 2015-12-29 2017-08-04 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160049427A1 (en) * 2014-08-18 2016-02-18 Globalfoundries Inc. Integrated circuits with self aligned contact structures for improved windows and fabrication methods
TW201624711A (en) * 2014-12-26 2016-07-01 聯華電子股份有限公司 Semiconductor device and method of forming the same
CN107017297A (en) * 2015-12-29 2017-08-04 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method

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