CN114067901A - Cluster test method, test terminal and storage medium of embedded storage chip - Google Patents
Cluster test method, test terminal and storage medium of embedded storage chip Download PDFInfo
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- CN114067901A CN114067901A CN202210045983.5A CN202210045983A CN114067901A CN 114067901 A CN114067901 A CN 114067901A CN 202210045983 A CN202210045983 A CN 202210045983A CN 114067901 A CN114067901 A CN 114067901A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1206—Location of test circuitry on chip or wafer
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The application provides a cluster test method, a test terminal and a storage medium of an embedded storage chip, wherein the method comprises the following steps: the power interface and the communication interface of the cluster testing device are connected, so that power is provided for a plurality of embedded memory chips in the cluster testing device through the power interface, and the embedded memory chips are respectively in communication connection with the communication interface; when the cluster testing device is set at the target temperature, allocating drive symbols for all the embedded memory chips one by one; and carrying out aging test, restart test, power-off test and read-write performance test on each embedded memory chip in parallel to obtain the test result of each embedded memory chip at the target temperature. Therefore, the performance test can be carried out on the embedded memory chip, and the delivered embedded memory chip is ensured to have better quality; in addition, the embedded memory chip testing system can also test a plurality of embedded memory chips in parallel, and greatly improves the testing efficiency.
Description
Technical Field
The present application relates to the field of embedded storage technologies, and in particular, to a cluster testing method for an embedded storage chip, a testing terminal, and a storage medium.
Background
An embedded memory chip (may also be referred to as an embedded memory) refers to a chip in which a controller chip, a NAND Flash (may also be referred to as a NAND Flash memory), and a DDR (Double Data Rate) are integrated. With the development of technology, embedded memory chips have been widely used in various electronic devices, such as civilian-grade electronic devices, industrial-grade electronic devices, and military-grade electronic devices.
In practical application, before the embedded memory chip leaves factory, the embedded memory chip needs to be tested to provide a qualified embedded memory chip for a user. However, in the prior art, the test of the embedded memory chip only aims at the NAND Flash, that is, only tests the NAND Flash, and therefore, the existing test method has no reliability.
Disclosure of Invention
Therefore, the application provides a cluster testing method, a testing terminal and a storage medium for the embedded memory chip, and the method can be used for carrying out performance testing on the embedded memory chip and ensuring that the shipped embedded memory chip has better quality.
In a first aspect, the present application provides a cluster testing method for an embedded memory chip, for testing a terminal, the method including:
connecting a power interface and a communication interface of a cluster test device so as to provide power for a plurality of embedded memory chips in the cluster test device through the power interface and be respectively in communication connection with each embedded memory chip through the communication interface;
when the cluster test device is set at a target temperature, allocating drive symbols to each embedded memory chip one by one; the target temperature is greater than or equal to-55 degrees and less than or equal to 125 degrees;
and performing aging test, restart test, power-off test and read-write performance test on each embedded memory chip in parallel to obtain a test result of each embedded memory chip at the target temperature.
In the cluster testing method provided by the application, the cluster testing device is further provided with a plurality of first indicator lamps and/or a plurality of second indicator lamps which are in one-to-one correspondence with the plurality of embedded memory chips;
one end of the first indicator light is connected with a preset voltage, and the other end of the first indicator light is connected with a read-write pin of the embedded memory chip;
one end of the second indicator light is connected with a power output pin of the embedded memory chip, and the other end of the second indicator light is connected with a grounding pin of the embedded memory chip.
In the cluster testing method provided by the application, each of the plurality of embedded memory chips is connected with the power interface through a power IC chip; and/or the number of the embedded memory chips is 20.
In the cluster testing method provided by the present application, allocating drive symbols to each of the embedded memory chips one by one includes:
carrying out partition formatting treatment on each embedded memory chip;
distributing disk symbols for the embedded memory chips subjected to the partition formatting treatment;
and/or the presence of a gas in the gas,
after allocating drive symbols for each embedded memory chip, the method further comprises:
and if the distribution of part of the plurality of embedded memory chips fails, redistributing the drive characters for the embedded memory chips with the distribution failure until the distribution is successful.
In the cluster testing method provided by the application, the aging test, the restart test, the power-off test and the read-write performance test are performed on the embedded memory chip to obtain the test result of the embedded memory chip at the target temperature, and the method comprises the following steps:
carrying out aging test, restarting test and power-off test on the embedded memory chip;
if the test terminal can still identify the drive letter corresponding to the embedded memory chip, performing read-write performance test on the embedded memory chip to obtain the read-write speed of the embedded memory chip;
if the read-write speed reaches the standard, obtaining a qualified test result of the embedded memory chip at the target temperature, otherwise obtaining an unqualified test result of the embedded memory chip at the target temperature;
and the number of the first and second groups,
the method further comprises the following steps:
in the process of performing aging test, restart test and power-off test on the embedded memory chip, if the embedded memory chip cannot normally operate, stopping the test and obtaining a test result that the embedded memory chip fails at the target temperature.
In the cluster test method provided by the application, the aging test of the embedded memory chip comprises the following steps:
circularly executing the following steps until the execution times are greater than or equal to a first preset threshold value: writing data into the embedded memory chip until the maximum storage capacity of the embedded memory chip, and deleting the written data after the writing is finished;
the embedded memory chip is subjected to restart test, which comprises the following steps:
restarting the embedded memory chip every set time length until the restart times is greater than or equal to a second preset threshold value;
and/or the presence of a gas in the gas,
the power-off test of the embedded memory chip comprises the following steps:
circularly executing the following steps until the execution times are greater than or equal to a third preset threshold: determining a power-off time point based on a random strategy, starting timing, and stopping supplying power to the embedded memory chip when the timing reaches the power-off time point; and restoring the power supply to the embedded memory chip which is powered off.
In the cluster testing method provided by the present application, the performing a read-write performance test on the embedded memory chip to obtain a read-write rate of the embedded memory chip includes:
writing a plurality of files with the size of 4K into an embedded memory chip to obtain a writing rate in the reading and writing rates;
reading a plurality of files with the size of 4K stored in an embedded memory chip to obtain the reading rate in the reading and writing rates;
and/or the presence of a gas in the gas,
after obtaining the read-write rate of the embedded memory chip, the method further comprises the following steps:
if the writing rate of the reading and writing rates is greater than or equal to a preset first rate threshold value and the reading rate of the reading and writing rates is greater than or equal to a preset second rate threshold value, determining that the reading and writing rates reach the standard; and/or storing the read-write speed of the embedded memory chip by screenshot.
In the cluster testing method provided by the present application, after obtaining the test result of each embedded memory chip at the target temperature, the method further includes:
and based on a preset ring block scanning strategy, carrying out ring block scanning on the embedded memory chip with a qualified test result.
In a second aspect, the present application provides a computer-readable storage medium storing a computer program, which when executed by a processor causes the processor to implement the cluster testing method for embedded memory chips according to the first aspect.
In a third aspect, the present application provides a test terminal comprising a processor and a memory; the memory for storing a computer program; the processor is configured to execute the computer program and implement the cluster testing method for the embedded memory chip according to the first aspect when executing the computer program.
The application provides a cluster test method, a test terminal and a storage medium of an embedded storage chip, wherein the method comprises the following steps: the power interface and the communication interface of the cluster testing device are connected, so that power is provided for a plurality of embedded memory chips in the cluster testing device through the power interface, and the embedded memory chips are respectively in communication connection with the communication interface; when the cluster testing device is set at the target temperature, allocating drive symbols for all the embedded memory chips one by one; wherein the target temperature is greater than or equal to-55 degrees and less than or equal to 125 degrees; and carrying out aging test, restart test, power-off test and read-write performance test on each embedded memory chip in parallel to obtain the test result of each embedded memory chip at the target temperature. Therefore, the performance test can be carried out on the embedded memory chip, and the delivered embedded memory chip is ensured to have better quality; in addition, the embedded memory chip testing system can also test a plurality of embedded memory chips in parallel, and greatly improves the testing efficiency.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flowchart of a cluster testing method for an embedded memory chip according to an embodiment of the present disclosure;
FIG. 2 is a schematic structural diagram of a cluster testing apparatus in an embodiment of the present application;
FIG. 3 is a schematic diagram of a circuit configuration of a first indicator light in an embodiment of the present application;
FIG. 4 is a schematic diagram of a circuit configuration of a second indicator light in an embodiment of the present application;
FIG. 5 is a flowchart illustrating an embodiment of allocating drive letters to an embedded memory chip by a test terminal;
FIG. 6 is a schematic flow chart illustrating the testing of an embedded memory chip by the testing terminal in the embodiment of the present application;
FIG. 7 is a flowchart illustrating a burn-in test performed by the test terminal on an embedded memory chip according to an embodiment of the present application;
FIG. 8 is a flowchart illustrating a reboot test performed by the test terminal on an embedded memory chip according to an embodiment of the present application;
FIG. 9 is a flowchart illustrating a power-off test performed by the test terminal on an embedded memory chip according to an embodiment of the present application;
FIG. 10 is a schematic flow chart illustrating a cluster testing method for an embedded memory chip according to an embodiment of the present application;
fig. 11 is a schematic structural diagram of a test terminal according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is to be understood that the terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of the present application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should also be understood that the terms "first," "second," "third," "fourth," and the like in the description, in the claims, or in the above-described drawings (if any) are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order, and may be construed to indicate or imply relative importance or implicitly to the features indicated. In addition, the term "connected" (if any) in the specification, claims or drawings of the present application is to be interpreted broadly, for example, the term "connected" may be a fixed connection, a detachable connection, an integrated connection, an electrical connection, or a signal connection, and the term "connected" may be a direct connection or an indirect connection via an intermediate medium. Furthermore, the term "and/or" (if present) as used in the specification, claims, or drawings of the present application refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In the prior art, the test of the embedded memory chip only aims at NAND Flash, that is, only tests NAND Flash, so that the quality of the shipped embedded memory chip cannot be ensured, that is, the existing test method does not have reliability. Therefore, the embodiment of the application provides a cluster test method, a test terminal and a storage medium for an embedded memory chip, and the method can be used for performing performance test on the embedded memory chip and ensuring that the shipped embedded memory chip has better quality; in addition, the method can also test a plurality of embedded memory chips in parallel, thereby greatly improving the test efficiency.
The cluster testing method for the embedded memory chip provided by the embodiment of the application can be used for testing terminals, and exemplarily, the testing terminals can be terminal devices with computing capability, such as a notebook computer and a desktop computer.
Referring to fig. 1, the method may include steps S10 to S30.
And step S10, connecting the power interface and the communication interface of the cluster testing device, so as to provide power for the plurality of embedded memory chips in the cluster testing device through the power interface, and respectively connect the embedded memory chips through the communication interface in a communication manner.
In the embodiment of the present application, as shown in fig. 2, the cluster testing apparatus has a power interface and a communication interface, and both interfaces are used for connecting external devices. Meanwhile, the cluster test device may place a plurality of embedded memory chips, for example, 10, 15, 20, 24, etc., and each embedded memory chip is connected to the power interface and is connected to the communication interface (the connection relationship is not shown in the figure), which may be simply understood as a parallel connection relationship between the chips, and it should be noted that, the embedded memory chip is connected to the power interface, which refers to that pins related to the chip and the power are connected to the power interface, and similarly, the embedded memory chip is connected to the communication interface, which refers to that pins related to the chip and the communication are connected to the communication interface.
In this case, the test terminal may be connected to the power interface and the communication interface of the cluster test apparatus, for example, the power interface of the cluster test apparatus is connected to the power port of the test terminal, and the communication interface of the cluster test apparatus is connected to the communication port of the test terminal. On one hand, the test terminal can supply power to each embedded memory chip through the power interface, so that the test terminal can determine whether to supply power to a certain embedded memory chip, for example, the test terminal can simultaneously supply power to all embedded memory chips, also can supply power to a part of the embedded memory chips, and does not supply power to the other part of the embedded memory chips; on the other hand, the test terminal can be respectively in communication connection with each embedded memory chip through the communication interface, so that the test terminal can determine whether to read and write data to one embedded memory chip, and similarly, the test terminal can simultaneously read and write data to all embedded memory chips, also can read and write data to one part of the embedded memory chips, and does not read and write data to the other part of the embedded memory chips. It should be noted that the test terminal is connected to the power interface and the communication interface of the cluster test device, which can facilitate the control of the test terminal on the embedded memory chip, and is beneficial to the subsequent chip test.
In an embodiment, as shown in fig. 2, the embedded memory chips are connected to the power interface through a power IC chip, and it can be understood that the power IC chip has a power processing function and can provide suitable and high-quality power for the embedded memory chips.
In one embodiment, the number of embedded memory chips is 20. Specifically, the test terminal has been allocated at least one drive letter, for example, a C drive (system drive), but in practical applications, the test terminal has been allocated two or three drive letters, for example, a C drive, a D drive, and so on. Since the drive letter needs to be allocated to the embedded memory chip in the subsequent test, the number of the embedded memory chips can be 20 in combination with the actual situation that the drive letter is allocated to the test terminal.
In one embodiment, as shown in fig. 2, the cluster testing apparatus is further provided with a plurality of first indicator LEDs 1 corresponding to the plurality of embedded memory chips one to one, that is, each embedded memory chip has a corresponding first indicator LED1 (e.g., a green light). In this embodiment, as shown in fig. 3, one end of the first indicator light LED1 is connected to a predetermined voltage VCC (e.g., 3.3V), and the other end is connected to the read/write PIN RD _ PIN of the embedded memory chip. Specifically, when the embedded memory chip can be read or written normally, the preset voltage VCC can supply power to the first indicator light LED1, so that the first indicator light LED1 emits light (e.g., green light). Therefore, during the subsequent test (e.g., burn-in test, restart test, power-off test), as long as the first indicator light LED1 is on, it indicates that the corresponding embedded memory chip under test has not found any problem temporarily, otherwise, the situation is the opposite. Therefore, the first indicator light LED1 can facilitate the user to know the test condition, and the user experience is improved. In one embodiment, as shown in fig. 3, the first indicator light LED1 may also be connected in series with a current limiting resistor.
In one embodiment, as shown in fig. 2, the cluster testing apparatus is further provided with a plurality of second indicator LEDs 2 corresponding to the plurality of embedded memory chips one to one, that is, each embedded memory chip has a second indicator LED2 (e.g., a red light) corresponding to it. In this embodiment, as shown in fig. 4, one end of the second indicator light LED2 is connected to a power output PIN VCC _ PIN (e.g., 1.2V) of the embedded memory chip, and the other end is connected to a ground PIN GND _ PIN (e.g., a PIN connected to the negative electrode of the power interface) of the embedded memory chip. Specifically, if the embedded memory chip is correctly placed, the embedded memory chip can be connected to the power interface, so it can be understood that the power output PIN VCC _ PIN of the embedded memory chip can supply power to the second indicator light LED2, so that the second indicator light LED2 emits light (for example, red light). So as long as the second indicator light LED2 is illuminated, it indicates that the embedded memory chip is properly positioned, otherwise the situation is reversed. Therefore, the second indicator light LED2 can be convenient for users to know the chip placement condition, and the user experience is improved. In one embodiment, as shown in fig. 4, the second indicator light LED2 may also be connected in series with a current limiting resistor.
Step S20, distributing drive symbols for each embedded memory chip when the cluster testing device is set at the target temperature; wherein the target temperature is greater than or equal to-55 degrees and less than or equal to 125 degrees.
In particular, when the embedded memory chip is used in industrial electronic devices or military electronic devices, the embedded memory chip is required to have higher quality, and therefore, the test of the embedded memory chip in the embodiment of the present application is performed at a target temperature, wherein the target temperature may be normal temperature, such as 15 degrees, 20 degrees, 25 degrees, and the like, or may be an extreme temperature, such as-55 degrees, -50 degrees, -45 degrees, and the like, and further such as 115 degrees, 120 degrees, 125 degrees, and the like.
Therefore, after the cluster testing device is placed at the target temperature, the subsequent steps can be performed. Before testing a plurality of embedded memory chips in parallel, a drive letter needs to be allocated to each embedded memory chip, so that the test terminal can perform subsequent tests. For example, if the disk identifier allocated to one embedded memory chip is E, the embedded memory chip may be treated as an E disk as a whole, so that the test terminal may perform the test on the embedded memory chip in the following steps.
In one embodiment, the step S20 of "allocating drive letters for each embedded memory chip" may include steps S210 to S220.
And step S210, carrying out partition formatting processing on each embedded memory chip.
And step S220, allocating the drive letter to the embedded memory chip which is subjected to the partition formatting processing.
In this embodiment, the embedded memory chip may be regarded as a solid state disk, and therefore, a formatting process needs to be performed before allocating the disk identifier, and therefore, the test terminal may perform a partition formatting process on each embedded memory chip, and further allocate the disk identifiers to the embedded memory chips that have been subjected to the partition formatting process one by one, for example, the disk identifier allocated to the embedded memory chips is D, E, F, G … ….
In an embodiment, after allocating drive symbols for each embedded memory chip, the method in the embodiment of the present application may further include the following steps:
and if the distribution of part of the embedded memory chips fails, redistributing the drive letter for the embedded memory chip with the distribution failure until the distribution is successful.
Specifically, a situation that some allocation fails may occur in the process of allocating the drive letter by the test terminal, so if the situation occurs, the embedded memory chips that respectively fail need to be reallocated until the drive letter is also successfully allocated to the embedded memory chips, thereby improving the reliability of the method.
For example, the test terminal may allocate drive letters to each embedded memory chip in parallel, and for a certain embedded memory chip, the process of allocating the drive letter may be as shown in fig. 5. Specifically, the test terminal may perform partition formatting processing on the embedded memory chip, and then allocate a drive letter to the embedded memory chip. And then judging whether the allocation is successful or not, if so, ending the operation of allocating the drive letter to the embedded memory chip, and if not, re-performing the partition formatting treatment and allocating the drive letter until the success. It should be noted that, the determining whether the allocation is successful may include: determining, by the user, whether the allocation was successful; and/or the test terminal acquires a disk list, if the disk list contains disk information allocated to the embedded memory chip, the allocation can be determined to be successful, otherwise, the allocation fails, for example, if the disk identifier allocated to the embedded memory chip is D, and the disk list acquired by the test terminal contains a C disk and a D disk, the allocation is successful.
And step S30, performing aging test, restart test, power-off test and read-write performance test on each embedded memory chip in parallel to obtain the test result of each embedded memory chip at the target temperature.
In the prior art, only NAND Flash is tested, so the obtained test result cannot be used for representing the performance of the embedded memory chip, and thus the quality of the shipped embedded memory chip cannot be ensured. Therefore, the embedded memory chip is subjected to multiple tests such as aging test, restart test, power-off test, read-write performance test and the like, and the obtained test result can be used for representing the performance of the embedded memory chip, so that the quality of the shipped embedded memory chip is ensured. In addition, for a plurality of embedded memory chips in the cluster testing device, because the testing terminal can independently control each embedded memory chip (for example, control power supply, control data read-write and the like), the embodiment of the application can perform parallel testing on the embedded memory chips, thereby greatly improving the testing efficiency. For example, for an embedded memory chip, if the embedded memory chip passes the four tests described above, it can be determined that the test result of the embedded memory chip at the target temperature is qualified, that is, the embedded memory chip has better quality; if one or more tests fail, the test result of the embedded memory chip at the target temperature can be determined to be not qualified.
In one embodiment, step S30 may include steps S310 through S330.
Step S310, carrying out aging test, restarting test and power-off test on the embedded memory chip.
Step S320, if the test terminal can still recognize the drive letter corresponding to the embedded memory chip, performing a read-write performance test on the embedded memory chip to obtain a read-write rate of the embedded memory chip.
And S330, if the read-write speed reaches the standard, obtaining a qualified test result of the embedded memory chip at the target temperature, otherwise obtaining an unqualified test result of the embedded memory chip at the target temperature.
From the foregoing discussion, it is known that the test terminal can test the embedded memory chips in parallel, that is, the test process of each embedded memory chip can be the same. Specifically, as shown in fig. 6, the testing process of an embedded memory chip may be as follows:
(1) the embedded memory chip is first subjected to burn-in test, reboot test and power-off test to determine whether the embedded memory chip is usable (which can be simply understood as whether it is readable and writable). Therefore, after the three tests are completed, if the test terminal can still recognize the drive letter corresponding to the embedded memory chip, the embedded memory chip is usable, and the read-write performance test can be performed. It should be noted that the sequence of the three tests is not limited in the embodiment of the present application, and those skilled in the art can flexibly select the sequence of the tests;
(2) under the condition that the embedded memory chip is determined to be available, the read-write performance needs to be tested. Therefore, the test terminal can test the read-write performance of the embedded memory chip so as to judge through the read-write speed. Specifically, if the read-write speed reaches the standard, the embedded memory chip has a certain read-write speed, so that the embedded memory chip can be determined to be a qualified product at the target temperature; on the contrary, if the read-write speed does not reach the standard, the embedded memory chip does not have a certain read-write speed, so that the embedded memory chip can be determined to be an unqualified product at the target temperature.
In this embodiment, the method in this embodiment may further include the following steps:
in the process of performing aging test, restart test and power-off test on the embedded memory chip, if the embedded memory chip cannot normally operate, the test is stopped and a test result that the embedded memory chip fails at a target temperature is obtained.
As can be seen from the foregoing discussion, if the embedded memory chip successfully passes the burn-in test, the restart test and the power-off test, it indicates that the embedded memory chip is usable, that is, the embedded memory chip can normally operate during the burn-in test, the restart test and the power-off test. However, in the test process of the three tests, as long as the situation that the embedded memory chip cannot normally operate occurs, it indicates that the embedded memory chip is unusable, i.e., a test result that the embedded memory chip fails at the target temperature can be obtained, and the subsequent test should be stopped.
In an embodiment, the "burn-in test of the embedded memory chip" in the method of the embodiment of the present application may include the following steps:
circularly executing the following steps until the execution times are greater than or equal to a first preset threshold value: and writing data into the embedded memory chip until the maximum storage capacity of the embedded memory chip, and deleting the written data after the writing is finished.
It is understood from the foregoing discussion that the burn-in process may be the same for each embedded memory chip. Specifically, for an embedded memory chip, since the embedded memory chip can be regarded as a solid state disk, data can be written into the embedded memory chip until the embedded memory chip is full, the written data can be deleted, and the aging test is completed after the embedded memory chip is circularly executed for a certain number of times (a first preset threshold, for example, 1000 times). For example, fig. 7 is a schematic flow chart of a burn-in test performed by a test terminal on an embedded memory chip, where a first preset threshold may be 1000. Therefore, in this example, each time the test terminal writes full data to the embedded memory chip and deletes the data, it may determine whether the embedded memory chip can still normally operate, for example, whether a drive letter corresponding to the embedded memory chip can also be identified, if not (it can be simply understood that the chip has a drive lost), it indicates that the embedded memory chip cannot normally operate, it indicates that the embedded memory chip is an unqualified product at the target temperature, if so, it may determine whether the execution time (i.e., the cycle time) is greater than or equal to 1000, if so, the next test is performed, and if not, the aging test is continued.
In an embodiment, the "performing a reboot test on an embedded memory chip" in the method according to the embodiment of the present application may include the following steps:
and restarting the embedded memory chip every set time length until the restart times are greater than or equal to a second preset threshold value.
Likewise, the reboot test procedure of each embedded memory chip may be the same. Specifically, for an embedded memory chip, since the embedded memory chip can be regarded as a solid state disk, a reboot (which can be simply understood as restarting a disk) can be performed, and a reboot test is completed after a certain number of reboots (a second preset threshold). For example, fig. 8 is a schematic flowchart of a process of performing a restart test on an embedded memory chip by a test terminal, where the second preset threshold may be 1000, and the set time length may be less than or equal to 5 seconds, for example, 4 seconds. Therefore, in this example, the embedded memory chip may be restarted after the set time length is passed each time, and then it may be determined whether the embedded memory chip is still able to normally operate, for example, whether a disk symbol corresponding to the embedded memory chip has a messy code, if the messy code occurs, it indicates that the embedded memory chip is not able to normally operate, it indicates that the embedded memory chip is an unqualified product at the target temperature, if the messy code does not occur, it may be determined whether the execution time (i.e., the cycle time) is greater than or equal to 1000, if so, a next test is entered, and if not, the restart test is continued.
In an embodiment, the method of the embodiment of the present application for performing a power-off test on an embedded memory chip may include the following steps:
circularly executing the following steps until the execution times are greater than or equal to a third preset threshold: determining a power-off time point based on a random strategy, starting timing, and stopping supplying power to the embedded memory chip when the timing reaches the power-off time point; and restoring the power supply to the embedded memory chip which is powered off.
Likewise, the power-down test procedure for each embedded memory chip may be the same. Specifically, in the embodiment, the power-off condition that the chip may encounter in practical application is simulated by randomly determining the power-off time point. And the test terminal can resume power supply after stopping supplying power to the embedded memory chip, for example, after a certain period of time. For example, fig. 8 is a schematic flow chart of a power-off test performed by the test terminal on an embedded memory chip, where a third preset threshold may be 3000, the determination of the power-off time point may be determined according to an existing random strategy, and a range of the power-off time point may also be limited, for example, the power-off time point is less than or equal to 1 second and less than or equal to 20 seconds. Therefore, in this example, the power supply for the embedded memory chip may be stopped when the power-off time point is reached every time, and then the power supply is resumed, and then, it may be determined whether the embedded memory chip can still normally operate, for example, whether a drive letter corresponding to the embedded memory chip can be identified, if not, it indicates that the embedded memory chip cannot normally operate, and indicates that the embedded memory chip is an unqualified product at the target temperature, and if so, it may be determined whether the execution frequency (i.e., the cycle frequency) is greater than or equal to 3000, if so, the next test is entered, and if not, the power-off test is continued.
In an embodiment, the step S320 of performing the read-write performance test on the embedded memory chip to obtain the read-write rate of the embedded memory chip may include the following steps:
writing a plurality of files with the size of 4K into an embedded memory chip to obtain a writing rate in the reading and writing rates; and reading a plurality of files with the size of 4K stored in the embedded memory chip to obtain the reading rate in the reading and writing rates.
In this embodiment, a file of 4K size refers to a file of 4K in volume, and therefore, the test terminal may acquire a plurality of files of 4K size, for example, a preset file or a temporary generated file, etc. Therefore, the test terminal can write the files into the embedded memory chip so as to obtain the write-in rate in the read-write rate in the write-in process; then, the test terminal can read the files from the embedded memory chip to obtain the read rate in the read-write rate in the reading process.
In an embodiment, after obtaining the read-write rate of the embedded memory chip, the method in the embodiment of the present application further includes the following steps:
if the writing rate in the reading and writing rates is greater than or equal to a preset first rate threshold value and the reading rate in the reading and writing rates is greater than or equal to a preset second rate threshold value, determining that the reading and writing rates reach the standard; and/or storing the read-write speed of the embedded memory chip by screenshot.
The read-write speed can be obtained after the test terminal performs the read-write performance test, but the embedded memory chip with the read-write speed reaching the standard is a qualified product. Therefore, the test terminal can judge whether the writing rate is greater than or equal to a preset first rate threshold value or not and whether the reading rate is greater than or equal to a preset second rate threshold value or not, if so, the reading and writing rate can be determined to reach the standard, otherwise, the reading and writing rate can be determined not to reach the standard. In addition, the test terminal can also store the read-write rate in a screenshot mode, so that the test terminal can be checked by a user after the test is finished, and the user experience is improved.
In an embodiment, as shown in fig. 10, after obtaining the test result of each embedded memory chip at the target temperature, the method in the embodiment of the present application may further include step S40.
And step S40, based on the preset ring block scanning strategy, carrying out ring block scanning on the embedded memory chip with the qualified test result.
Specifically, after step S30, a part of the embedded memory chips in the cluster testing apparatus are screened out as qualified embedded memory chips, and the rest of the embedded memory chips (if any) are rejected products. However, in the testing process of step S30, the embedded memory chip may be damaged, so to further improve the reliability of the method, in this embodiment of the present application, the ring block scanning is further performed on the embedded memory chip whose testing result is qualified, so as to determine whether a bad block exists in the part of the embedded memory chip, and in an implementation manner, if a bad block exists in the part of the embedded memory chip, the testing terminal may further generate corresponding prompt information to notify the user.
In addition, an embodiment of the present application further provides a test terminal, as shown in fig. 11, including a processor and a memory. The memory for storing a computer program; the processor is configured to execute the computer program and implement the cluster testing method for any embedded memory chip provided in the embodiment of the present application when executing the computer program.
It should be understood that the Processor may be a Central Processing Unit (CPU), and the Processor may be other general purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, etc. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the processor is enabled to implement the cluster testing method for any embedded memory chip provided in the embodiment of the present application.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer readable storage media (or non-transitory media) and communication media (or transitory media).
The term computer-readable storage medium includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
For example, the computer readable storage medium may be an internal storage unit of the test terminal according to the foregoing embodiment, such as a hard disk or a memory of the test terminal. The computer readable storage medium may also be an external storage device of the test terminal, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, provided on the test terminal.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A cluster test method of an embedded memory chip is used for testing a terminal, and the method comprises the following steps:
connecting a power interface and a communication interface of a cluster test device so as to provide power for a plurality of embedded memory chips in the cluster test device through the power interface and be respectively in communication connection with each embedded memory chip through the communication interface;
when the cluster test device is set at a target temperature, allocating drive symbols to each embedded memory chip one by one; the target temperature is greater than or equal to-55 degrees and less than or equal to 125 degrees;
and performing aging test, restart test, power-off test and read-write performance test on each embedded memory chip in parallel to obtain a test result of each embedded memory chip at the target temperature.
2. The method according to claim 1, wherein the cluster testing device is further provided with a plurality of first indicator lights and/or a plurality of second indicator lights in one-to-one correspondence with the plurality of embedded memory chips;
one end of the first indicator light is connected with a preset voltage, and the other end of the first indicator light is connected with a read-write pin of the embedded memory chip;
one end of the second indicator light is connected with a power output pin of the embedded memory chip, and the other end of the second indicator light is connected with a grounding pin of the embedded memory chip.
3. The method of claim 1, wherein each of the plurality of embedded memory chips is connected to the power interface via a power IC chip; and/or the number of the embedded memory chips is 20.
4. The method of any of claims 1-3, wherein assigning drive letters to each of the embedded memory chips comprises:
carrying out partition formatting treatment on each embedded memory chip;
distributing disk symbols for the embedded memory chips subjected to the partition formatting treatment;
and/or the presence of a gas in the gas,
after allocating drive symbols for each embedded memory chip, the method further comprises:
and if the distribution of part of the plurality of embedded memory chips fails, redistributing the drive characters for the embedded memory chips with the distribution failure until the distribution is successful.
5. The method of any one of claims 1 to 3, wherein performing a burn-in test, a restart test, a power-off test, and a read-write performance test on the embedded memory chip to obtain a test result of the embedded memory chip at the target temperature comprises:
carrying out aging test, restarting test and power-off test on the embedded memory chip;
if the test terminal can still identify the drive letter corresponding to the embedded memory chip, performing read-write performance test on the embedded memory chip to obtain the read-write speed of the embedded memory chip;
if the read-write speed reaches the standard, obtaining a qualified test result of the embedded memory chip at the target temperature, otherwise obtaining an unqualified test result of the embedded memory chip at the target temperature;
and the number of the first and second groups,
the method further comprises the following steps:
in the process of performing aging test, restart test and power-off test on the embedded memory chip, if the embedded memory chip cannot normally operate, stopping the test and obtaining a test result that the embedded memory chip fails at the target temperature.
6. The method of claim 5, wherein burn-in testing the embedded memory chip comprises:
circularly executing the following steps until the execution times are greater than or equal to a first preset threshold value: writing data into the embedded memory chip until the maximum storage capacity of the embedded memory chip, and deleting the written data after the writing is finished;
the embedded memory chip is subjected to restart test, which comprises the following steps:
restarting the embedded memory chip every set time length until the restart times is greater than or equal to a second preset threshold value;
and/or the presence of a gas in the gas,
the power-off test of the embedded memory chip comprises the following steps:
circularly executing the following steps until the execution times are greater than or equal to a third preset threshold: determining a power-off time point based on a random strategy, starting timing, and stopping supplying power to the embedded memory chip when the timing reaches the power-off time point; and restoring the power supply to the embedded memory chip which is powered off.
7. The method of claim 5, wherein the performing the read-write performance test on the embedded memory chip to obtain the read-write speed of the embedded memory chip comprises:
writing a plurality of files with the size of 4K into an embedded memory chip to obtain a writing rate in the reading and writing rates;
reading a plurality of files with the size of 4K stored in an embedded memory chip to obtain the reading rate in the reading and writing rates;
and/or the presence of a gas in the gas,
after obtaining the read-write rate of the embedded memory chip, the method further comprises the following steps:
if the writing rate of the reading and writing rates is greater than or equal to a preset first rate threshold value and the reading rate of the reading and writing rates is greater than or equal to a preset second rate threshold value, determining that the reading and writing rates reach the standard; and/or storing the read-write speed of the embedded memory chip by screenshot.
8. The method of claim 1, further comprising, after obtaining the test result of each of the embedded memory chips at the target temperature:
and based on a preset ring block scanning strategy, carrying out ring block scanning on the embedded memory chip with a qualified test result.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, causes the processor to implement the method of cluster testing of embedded memory chips according to any one of claims 1-8.
10. A test terminal comprising a processor and a memory;
the memory for storing a computer program;
the processor is used for executing the computer program and realizing the cluster testing method of the embedded storage chip according to any one of claims 1 to 8 when the computer program is executed.
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