CN115602242A - Storage device and test method thereof - Google Patents
Storage device and test method thereof Download PDFInfo
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- CN115602242A CN115602242A CN202211587534.XA CN202211587534A CN115602242A CN 115602242 A CN115602242 A CN 115602242A CN 202211587534 A CN202211587534 A CN 202211587534A CN 115602242 A CN115602242 A CN 115602242A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a storage device, at least comprising: the internal memory stores functional firmware, main test firmware and verification test firmware, and the main test firmware is provided with an operation frequency threshold; the processor is electrically connected with the internal memory, when the storage device is powered on, the processor reads and circularly runs the main test firmware until the running times of the main test firmware reach a running time threshold value, and main test data are obtained and stored, wherein after the main test data are obtained, the processor randomly runs the verification test firmware to obtain and store the verification test data; and the flash memory chip is connected with the processor and stores the main test data and the verification test data. The invention provides a storage device and a test method thereof, which are used for improving the test efficiency of the storage device and reducing the test cost.
Description
Technical Field
The invention relates to the field of storage testing, in particular to a storage device and a testing method thereof.
Background
After the chip is packaged, there may be potential defects, which may result in unstable performance or functional potential defects of the chip. If these potentially defective chips are used on critical equipment, they may malfunction, causing property loss or life hazard to the user. Therefore, after the chip is packaged, the chip needs to be subjected to a burn-in test to confirm the failure time of the chip. The cost of the chip aging test is too high, which is not beneficial to the large-scale use of the chip aging test.
Disclosure of Invention
The invention aims to provide a storage device and a test method thereof, so as to improve the test efficiency of the storage device and reduce the test cost.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a storage device, at least comprising:
the system comprises an internal memory, a main test firmware and a verification test firmware, wherein the internal memory stores the functional firmware, the main test firmware and the verification test firmware, and the main test firmware is provided with an operation frequency threshold;
a processor electrically connected to the internal memory, wherein when the memory device is powered on, the processor reads and circularly runs the main test firmware until the running frequency of the main test firmware reaches the running frequency threshold, acquiring and storing main test data, wherein after the main test data is acquired, the processor randomly runs the verification test firmware to acquire and store the verification test data; and
and the flash memory chip is connected with the processor, and the main test data and the verification test data are stored in the flash memory chip.
In an embodiment of the invention, the functional firmware includes an enabling module, when the enabling module is in a disabled state, the processor reads and runs the main test firmware when being powered on, when the enabling module is in an enabled state, the processor runs the main test firmware when receiving a host signal.
In an embodiment of the invention, the main test firmware includes an identification bit recognition module, and when the processor does not receive the host signal and runs the main test firmware, the identification bit recognition module sets up an identification bit in the processor.
In an embodiment of the present invention, the main test firmware includes a running time identification module, and when the identification position is set, the running time identification module obtains and records the running time of the main test firmware.
In an embodiment of the present invention, the operation number identification module is provided with an operation period, and the operation number of the main test firmware is the number of the operation period completed by the processor after the identification position.
In an embodiment of the present invention, the main test firmware includes a main test module, the main test module includes a plurality of test units, and the operation data of the test units is the main test data.
In an embodiment of the present invention, the verification test firmware includes a plurality of recorded information obtaining units, and the recorded information obtaining units are configured to read the stored data in the flash memory chip.
The invention provides a test method of a storage device, which comprises the following steps:
providing a storage device comprising an internal memory, a flash memory chip, and a processor, wherein the internal memory comprises functional firmware;
writing main test firmware into the internal memory, wherein the main test firmware is provided with a running time threshold;
when the storage device is powered on, the processor reads and circularly runs the main test firmware until the running times of the main test firmware reach the running time threshold, and main test data are obtained and stored;
writing verification test firmware into the internal memory, and after obtaining the main test data, the processor randomly runs the verification test firmware to obtain and store verification test data; and
storing the main test data and the verification test data in the flash memory chip.
In an embodiment of the invention, the functional firmware comprises an enabling module, and the enabling module is set to a disabled state before the main test firmware is run by the processor.
In an embodiment of the present invention, the step of obtaining the number of operations includes:
setting an operation period;
after the identification position of the main test firmware is set, timing the running process of the main test firmware; and
and acquiring the number of running cycles of the main test firmware according to the running time of the main test firmware, and taking the number of the running cycles as the running times.
As described above, the present invention provides a storage device and a test method thereof, which can perform an aging test on the storage device, thereby verifying whether the life of the storage device meets the design requirements, so as to ensure the quality of the storage device in the mass production process. Moreover, according to the storage device and the test method thereof provided by the invention, the storage device can be directly subjected to the aging test after being electrified under the condition that no signal generator is added, so that the aging test result of the storage device can be quickly and accurately obtained, the cost consumed in the test process is low, and the large-scale test is favorably carried out.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a testing apparatus according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a memory device according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a processor and an internal memory according to an embodiment of the invention.
FIG. 4 is a block diagram of a functional firmware according to an embodiment of the present invention.
FIG. 5 is a block diagram of main test firmware according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of the operation number identification module according to an embodiment of the present invention.
FIG. 7 is a schematic diagram of a main test module according to an embodiment of the present invention.
Fig. 8 is a schematic structural diagram of a firmware entry module according to an embodiment of the present invention.
FIG. 9 is a block diagram illustrating the location of a boot instruction according to an embodiment of the present invention.
Fig. 10 is a schematic diagram illustrating a location of a card open command according to an embodiment of the invention.
FIG. 11 is a block diagram illustrating the location of a dispatch instruction according to one embodiment of the present invention.
FIG. 12 is a block diagram of a data load instruction according to an embodiment of the present invention.
FIG. 13 is a diagram illustrating a location of a first test firmware according to an embodiment of the invention.
FIG. 14 is a diagram illustrating a second test firmware according to an embodiment of the present invention.
FIG. 15 is a flowchart illustrating a method for testing a memory device according to an embodiment of the present invention.
In the figure: 10. a testing device; 20. a temperature control box; 30. an aging machine; 40. an aging test board; 50. a storage device; 100. a flash memory chip; 200. a main controller; 300. a processor; 301. a main control unit; 302. a sub-control unit; 303. an interconnection unit; 304. a read-write unit; 305. a memory protection unit; 306. a prefetch unit; 307. a data processing unit; 308. a data cache unit; 309. an instruction cache unit; 400. a transmission unit; 500. an internal memory; 600. a main test firmware; 700. verifying the test firmware; 800. a functional firmware; 900. a data bus.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The chip is placed in a preset temperature environment within a period of time, and then a specific voltage is applied to the chip to accelerate the aging of the chip, so that the reliability of the chip can pass through an early failure period in advance and directly reach an accidental failure period or a fault accidental period, and the failure time of the chip is determined. The chip aging test standards vary, for example, when the chip can be aged for 1000 hours at 125 ℃, the service life of the chip can be considered to be 4 years. For another example, if the chip can be aged for 2000 hours at a temperature of 150 ℃, the lifetime of the chip can be considered to be 28 years. And simulating the service time of the chip according to different continuous aging times of the chip in different aging environments. In this embodiment, the chip subjected to the burn-in test may be a nonvolatile memory device, such as a NAND flash memory and a Read-only memory (ROM), or may be a memory device based on a nonvolatile memory device, such as an Embedded Multi Media Card (EMMC).
Referring to fig. 1, the present invention provides a testing apparatus 10 for a storage device, wherein the testing apparatus 10 includes a temperature control box 20, an burn-in board 30 and a burn-in board 40. Power is supplied to the temperature control box 20, the burn-in board 30 and the burn-in board 40. The temperature control box 20 includes a constant temperature box 201, and the aging machine 30 is placed in the constant temperature box 201. The burn-in board 40 is mounted on the burn-in board 30. Wherein the memory device 50 may be mounted on the burn-in board 40. The temperature of the temperature control box 20 may be, for example, 80 ℃ to 130 ℃. The temperature of the temperature control box 20 can be adjusted by the tester according to the test requirements. Before the test of the storage device 50 is started, the temperature of the temperature control box 20 is adjusted so that the temperature of the incubator 201 becomes constant. The memory device 50 is mounted on the burn-in board 40, and the memory device 50 is tested.
Referring to fig. 1 and fig. 2, the present invention provides a storage apparatus 50, and the storage apparatus 50 may be an embedded storage device. The memory device 50 includes a flash memory chip 100 and a host controller 200, and the flash memory chip 100 is electrically connected to the host controller 200. The main controller 200 includes a processor 300, a transmission unit 400, and an internal memory 500, and the main controller 200 and the flash memory chip 100 and the host device may perform data transmission through the transmission unit 400. The internal memory 500 may be a tightly coupled memory, and a plurality of firmware is stored in the internal memory 500. In the present embodiment, the processor 300 may be a Reduced Instruction System Computer (RISC), and may specifically be an ARM processor (Advanced RISC Machines).
Referring to fig. 1 to 3, in an embodiment of the invention, a processor 300 includes a main control unit 301, a sub-control unit 302, and an interconnection unit 303. Wherein the primary control unit 301 and the secondary control unit 302 are connected to different clock domains. In this embodiment, the primary control unit 301 and the secondary control unit 302 support synchronous clock transitions and/or asynchronous clock transitions. Specifically, the main control unit 301 and the sub control unit 302 may be AXI (Advanced eXtensible Interface) controllers. The interconnection unit 303 is electrically connected to the main control unit 301 and the sub-control unit 302, so as to transmit data information between the main control unit 301 and the sub-control unit 302. Processor 300 also includes data processing components and cache components. The data processing component includes a read/write unit 304, a memory protection unit 305, a prefetch unit 306, and a data processing unit 307. The read/write unit 304 is connected to the memory protection unit 305, the interconnection unit 303 and the data processing unit 307. The read/write unit 304 can read data from the data cache unit 308 and the instruction cache unit 309, and write data into the data cache unit 308. The memory protection unit 305 is electrically connected to the prefetch unit 306, and the memory protection unit 305 can protect the running task from damaging the operation of other tasks and prevent system resources and other tasks from being illegally accessed. The data processing unit 307 is electrically connected to the prefetch unit 306 and the read/write unit 304, and receives and processes data from the prefetch unit 306 and the read/write unit 304, and then transmits the processed data to the read/write unit 304 and the prefetch unit 306. The cache memory component includes a data cache unit 308 and an instruction cache unit 309. The data cache unit 308 and the command cache unit 309 are electrically connected to the main control unit 301 and the interconnect unit 303. The data buffer unit 308 may be a Random Access Memory (RAM) to store and transmit user data and system data in the main controller 200. The instruction buffer unit 309 may also be a random access memory device to store and transmit firmware instructions in the main controller 200 and instructions issued by the upper computer. In the present embodiment, the processor 300 is electrically connected to the data bus 900, and the data bus 900 may be an AXI bus having an AXI protocol.
Referring to fig. 2 to 4, in an embodiment of the invention, the internal memory 500 includes a main test firmware 600, a verification test firmware 700 and a functional firmware 800. Functional firmware 800 includes, among other things, an enabling module 801 and a functional module 802. When the memory device 50 is tested, the internal memory 500 is mounted on the test apparatus 10. The enabling module 801 includes an enabling interface electrically connected to an external host device. The enable module 801 includes an enabled state and a disabled state, and the default state of the enable module 801 is the enabled state. The enabling module 801 is electrically connected to the function module 802. After the testing apparatus 10 and the storage apparatus 50 are powered on, if the enabling module 801 is in an enabling state, when the main control unit 301 and the enabling module 801 jointly send a control signal to the functional module 801, the main control unit 301 reads out a program instruction from the functional module 802, so as to ensure the accuracy of instruction execution and avoid firmware errors. When receiving a first control instruction from the host device, the enabling module 801 starts sending a control signal to the function module 802, and allows the main control unit 301 to call up a program instruction in the function module 802. In this embodiment, if the enabling module 801 is in the disabled state, the main control unit 301 may directly call the program instruction from the functional module 802 to implement various functions such as data reading, writing, and editing. In the testing method of the memory provided by the invention, the enabling module 801 is set to the disabled state before the test firmware starts to run.
Referring to fig. 1 to 5, in an embodiment of the invention, a main control unit 301 runs a test firmware. Specifically, the main test firmware 600 is run first, and then the verification test firmware 700 is run. The main test firmware 600 includes an identification bit recognition module 601, a running number recognition module 602, a main test module 603, and a firmware entry module 604. The flag identification module 601 is used to determine the operation status of the main test firmware 600. When the main control unit 301 starts to run the main test firmware 600, the bit data bits of the param file are set. In this embodiment, the flag identifying module 601 identifies whether the bit data bit of the param file is set, and determines whether the internal memory 500 receives an instruction from the host device. When the internal memory 500 does not receive the instruction of the host device and the bit data bits of the param file are set, the main test firmware 600 starts to run. When the main test firmware 600 starts to run, the run-time identification module 602 starts to record the run-time or run-time period of the main test firmware 600. In this embodiment, the main test firmware 600 starts running, and the main control unit 301 executes the program instructions of the main test module 603. In this embodiment, the running process of the main test module 603 is set as a dead-loop process, and the main test module 603 is repeatedly executed. In this embodiment, the stop position of the main test module 603 is determined by the operation number identification module 602.
Referring to fig. 2 to 5 and fig. 8 to 13, in an embodiment of the invention, the firmware entry module 604 is used for entering the program instructions in the main test firmware 600 into the internal memory 500. The firmware entry module 604 includes a boot unit 6041, an instruction dispatch unit 6042, and an instruction load unit 6043. The main test firmware 600 may be burned into the internal memory 500 by a mass production tool, for example, by an MP tool. Among them, the boot unit 6041 includes a boot instruction, and the boot instruction is stored in the internal memory 500. After the storage device 50 is powered on, the boot instruction in the boot unit 706 automatically runs, and the card-open instruction is placed in the internal memory 500 through the instruction load unit 6043. Specifically, the card open instruction may be placed to address 0x00008000. The internal memory 500 includes an execution flag bit 501. When the card-open command is placed in the internal memory 500, the execution flag bit 501 is shifted to the card-open command. Wherein the dispatched instruction is transferred to a specified address, such as address 0x00020000, by instruction dispatch unit 6042. The logging and enabling of the main test firmware 600 is completed by scheduling instructions to log data load instructions into the internal memory 500 and completing the loading of all program instructions of the main test firmware 600 through the instruction load unit 6043.
Referring to fig. 2 to 6, in an embodiment of the invention, the operation number identification module 602 includes a timing unit 6021, an operation number recording unit 6022 and an operation termination unit 6023. The timing unit 6021 may be a timer for recording the running time of the main test firmware 600. In the present embodiment, a firmware operation cycle of the main test firmware 600 is set, and the firmware operation cycle is, for example, 15min to 11695in. The number-of-runs recording unit 6022 is used to record the number of runs of the main test firmware 600. The running time of the main test firmware 600 is acquired by the timing unit 6021, and the running number of the main test firmware 600 is increased once every time the main control unit 301 runs for one firmware running cycle. Wherein the number of times of operation of main test firmware 600 is recorded in a memory block of flash memory chip 100. In which periodic data that the main test firmware 600 has been run may be stored in a result page (result page) of a bad block (bad block). Specifically, the number of times of execution of the main test firmware 600 may be recorded at the positions of bad blocks 0x1f8 to 0x1fb. The operation cycles can be sorted according to time, and the sorted data can be stored in the first bit of the bad block result page. In this embodiment, an operation time threshold or an operation number threshold is set, and when the operation time of the main test firmware 600 reaches the operation time threshold or the operation number of the main test firmware 600 reaches the operation number threshold, the operation of the main test firmware 600 may be stopped by the operation termination unit 6023. The running time threshold may be set according to design requirements of different storage devices 50, for example, the running time threshold may be 1000h, 1200h, 1500h, and so on, and the invention does not limit the value of the running time threshold.
Referring to fig. 1 to 7, in an embodiment of the present invention, the main test module 603 includes a basic information obtaining unit 6031, a random buffer test unit 6032, a register test unit 6033, a transmission bandwidth test unit 6034, a flash granule test unit 6035, a data transmission test unit 6036, a device code error correction unit 6037, and a parameter collection unit 6038. In this embodiment, basic information of the storage apparatus 50, including a device identification code of a Read-Only Memory (ROM) and information of a one-time programmable Memory (eFuse), is acquired by the basic information acquiring unit 6031. Specifically, the storage device 50 may be set to the read-only mode, the basic information acquiring unit 6031 may acquire the device identification code of the read-only memory and the value of the otp memory, and if the device identification code of the read-only memory and the value of the otp memory are successfully read, the test item of the basic information acquiring unit 6031 passes. If the basic information of the storage device 50 cannot be acquired in a certain operation cycle, the test item of the basic information acquisition unit 6031 fails, and the failed test data is recorded in the flash memory chip 100.
Referring to fig. 1 to 7, in an embodiment of the invention, the random cache test unit 6032 is used for testing whether the data cache unit 308 and the instruction cache unit 309 can operate normally. Register test unit 6033 may be used to detect whether a bit flipping phenomenon exists for registers in storage 50. Specifically, when the cmd23 register control command sent by the host device to the host control unit 301 does not match the value of the cmd23 register, it is determined that the storage bit of the cmd23 register in the storage device 50 is inverted, and the test item of the register test unit 6033 does not pass. If the cmd23 register control command issued by the host apparatus to the main control unit 301 matches the value of the cmd23 register, the test item of the register test unit 6033 passes. The test information may be recorded in the flash memory chip 100. The transmission bandwidth test unit 6034 is used to check whether the data transmission bus can operate normally. In the present embodiment, the storage device 50 may be set to a read-only mode, and the flash memory chip 100 may be subjected to read, write, and compare tests through, for example, a 1-bit bus bandwidth, a 4-bit bus bandwidth, and an 8-bit bus bandwidth, and test information may be recorded in the flash memory chip 100. Wherein if the read, write, and compare tests pass at a plurality of bandwidths, the test item of the transmission bandwidth test unit 6034 passes. The flash granule test unit 6035 is used to check whether the wire bonding of the flash chip 100 on the storage device 50 is normal. Specifically, the flash granule test unit 6035 may read a device code (ID) of the flash chip 100 and a quantity of granules (die) of the flash chip 100. If the device code and the number of the flash memory granules read by the flash memory granule test unit 6035 match the initial information of the storage device 50, the test item of the flash memory granule test unit 6035 passes, and the test information is recorded in the flash memory chip 100.
Referring to fig. 1 to fig. 3 and fig. 7, in an embodiment of the invention, a data transmission test unit 6036 is used for testing whether the storage device 50 can correctly transmit data under the HS400 protocol. If the transmission data is correct, the test item of the data transmission test unit 6036 is passed. If the transmission data is not correct, the test item of the data transmission test unit 6036 fails, and the test information of the data transmission test unit 6036 is recorded in the flash memory chip 100. In the present embodiment, the device encoding error correction unit 6037 is used to test whether the device identification code in the storage apparatus 50 is written correctly. If the device identification code is correctly written in the flash memory chip 100, the test item of the data transfer test unit 6036 is passed. If the device identification code is not correctly written in the flash memory chip 100, the test item of the data transfer test unit 6036 is not passed, and the test information is recorded in the flash memory chip 100. In this embodiment, the parameter collecting unit 6038 is used for collecting data of the internal memory 500 and the processor 300 after the card-open instruction is executed.
Referring to fig. 1 to 13, in an embodiment of the present invention, after the main test firmware 600 is recorded in the internal memory 500, the storage device 50 is tested sequentially through the basic information obtaining unit 6031, the random buffer test unit 6032, the register test unit 6033, the transmission bandwidth test unit 6034, the flash memory granule test unit 6035, the data transmission test unit 6036, and the device code error correction unit 6037, and the parameter collecting unit 6038 collects test information and stores test data in the flash memory chip 100. Wherein the operation of the main test module 603 may be a dead loop. The parameter collection unit 6038 continues to execute the basic information acquisition unit 6031 to the code error correction unit 708 every time parameter collection of one cycle is completed. The running time of the main test firmware 600 is acquired by the timing unit 6021, the running frequency is recorded by the running frequency recording unit 6022, and the running termination unit 6023 can judge whether the running time of the main test firmware 600 meets the test requirement according to the running time threshold or the running frequency threshold. If the number of runs or the run time of the main test firmware 600 reaches a threshold, the main test firmware 600 stops running.
Referring to fig. 1, fig. 3 and fig. 5, and fig. 8 to fig. 13, in an embodiment of the present invention, during the operation process of the main test firmware 600, the operating state of the storage device 50 is confirmed by the verification test firmware 700. In this embodiment, the functional firmware 800 includes a firmware update module 801, and the firmware update module 801 may enter the verification test firmware 700 into the internal memory 500. Specifically, the storage device 50 may be an embedded memory, or may be a storage device including an embedded memory. In the present embodiment, the storage device 50 is adjusted to a Firmware online Update mode (FFU) before the verification test Firmware 700 is entered. Among other things, the firmware entry step of the firmware update module 801 may coincide with the firmware entry step of the firmware entry module 604. The position of the program instruction is adjusted by the boot instruction and the scheduling instruction, and the program instruction of the verification test firmware 700 is recorded in the internal memory 500 by the data load instruction. Wherein the verification test firmware 700 may be entered during the operation of the main test firmware 600. The verification test firmware 700 may also be entered after the main test firmware 600 finishes running.
Referring to fig. 1, fig. 3 and fig. 5, and fig. 14, in an embodiment of the invention, the verification test firmware 700 includes a storage test unit 701, an erasure test unit 702, a recording information obtaining unit 703, a protocol transmission test unit 704, an identification code error correction unit 705, a capacity test unit 706, and a data collection unit 707. The storage test unit 701 is used to detect whether the storage device 50 can work normally, and the storage test unit 701 includes a plurality of test items. Specifically, the storage test unit 701 may adjust the storage device 50 to a read-only mode, and then read the device id of the rom in the storage device 50, and if the device id of the rom can be read, the test item passes. Specifically, the information of the otp memory in the storage device 50 can be read out through the storage test unit 701, and if the information can be read out, the test item passes through. The value of the otp memory can be used as the identification code of the storage device 50. Specifically, the Memory test unit 701 can test whether a Static Random Access Memory (SRAM) in the Memory device 50 can normally operate. If the test item can work normally, the test item passes. Specifically, the storage test unit 701 may adjust the storage device 50 to a read-only mode, and perform read, write, and compare tests on the storage device 50 with different transmission bandwidths in the read-only mode of the storage device 50. If the storage device 50 can pass the read, write, and compare tests at different transmission bandwidths, the test item passes. Specifically, the storage test unit 701 may check whether the routing of the particles of the flash memory chip 100 on the storage device 50 is normal, and if the correct number of the particles and the correct number of the codes of the flash memory chip 100 can be read, the test item passes.
Referring to fig. 1, 3 and 5, and fig. 14, in an embodiment of the invention, the erase count of the memory device 50 can be tested by the erase value test unit 702. The number of times of erasing the flash memory chip 100 is limited to 3000 to 5000 times, for example. When the number of times of erasing the flash memory chip 100 reaches the upper limit, the flash memory chip 100 is excessively worn, and the theoretical life value is reached. Therein, the test information of the erasure value test unit 702 can be recorded in the flash memory chip 100. In the present embodiment, the storage data in the flash memory chip 100 may be acquired by the recording information acquisition unit 703. In which test data is stored in the flash memory chip 100 when the main test firmware 600 is run, the test information of the main test firmware 600 may be acquired by the recorded information acquiring unit 703. If the recorded information acquiring unit 703 does not read out the test information of the main test firmware 600, the test data of the main test firmware 600 is not stored in the flash memory chip 100, and the test item fails. If the test data of the main test firmware 600 is normally stored, the test data of the main test firmware 600 may be read out through the log information obtaining unit 703. The protocol transmission test unit 704 may be used to detect whether the protocol transmission of the storage device 50 is normal. Specifically, it can be detected whether the storage device 50 can correctly transmit data under the HS400, and if the storage device can correctly transmit data, the test item passes. The id correction unit 705 may be used to check the device id of the storage device 50, and if the device id is correctly written into the processor 300, the test item passes. In this embodiment, the Capacity testing unit 706 may test whether the Dynamic Capacity (Dynamic Capacity) of the storage device 50 is within a threshold range, and if so, the corresponding test item of the Capacity testing unit 706 passes the test item. Test data verifying test firmware 700 may be acquired by data collection unit 707.
Referring to fig. 1 to 15, the present invention provides a testing method of a memory device, which includes steps S10 to S50.
And step S10, providing a storage device, wherein the storage device comprises an internal memory, a flash memory chip and a processor, and the internal memory comprises functional firmware.
And step S20, writing main test firmware into the internal memory, wherein the main test firmware is provided with an operation time threshold.
And S30, when the storage device is powered on, the processor reads and circularly runs the main test firmware until the running times of the main test firmware reach a running time threshold, and the main test data are obtained and stored.
And S40, writing verification test firmware into the internal memory, and after the main test data is obtained, randomly running the verification test firmware by the processor to obtain and store the verification test data.
And S50, storing the main test data and the verification test data in the flash memory chip.
Referring to fig. 1 to fig. 3 and fig. 15, in step S10, in an embodiment of the present invention, the storage device 50 may be an Embedded memory (eMMC), or may be a storage device using an Embedded memory, such as an Embedded package on package memory. The memory device 50 includes a flash memory chip 100 and a main controller 200, wherein the main controller 200 includes a processor 300 and an internal memory 500 and a transmission unit 400. In the present embodiment, the internal memory 500 includes a functional firmware 800. Functional firmware 800 is the program instructions designed for the integrated circuit based on the desired functionality of the memory device. Functional firmware 800 includes, among other things, an enabling module 801 and a functional module 802. When the enable module 801 is in the enabled state, testing of the memory device 50 may begin when the host device sends a first signal to the processor 300. When the enabling module 801 is in the disabled state, the processor 300 may directly invoke the main test firmware 600 to test the memory device 50 in the power-on state of the memory device 50. In this embodiment, the enabling module 801 may be set to the disabled state before step S20 is performed or before step S30 is performed.
Referring to fig. 1 to 3 and 15, in an embodiment of the present invention, the storage device 50 is installed in the temperature control box 20, and the temperature of the temperature control box 20 is adjusted to be a constant temperature, for example, 80 ℃ to 130 ℃. A constant voltage, for example 3.63V, is provided to the storage device 50. In step S20, main test firmware 600 is written to internal memory 500 by firmware entry module 604. In step S30, when the storage device 50 is powered on, the processor 300 reads and loops the main test firmware 600 until the number of operation times of the main firmware reaches the operation time threshold. Main test firmware 600 is run to obtain main test data. In step S40, the verification test firmware 700 is written to the internal memory 500 by the firmware update module. The write verification test firmware 700 may be in the process of running the main test firmware 600 or after the main test firmware 600 is finished running. After the main test data is obtained, the verification test firmware 700 is executed by the processor 300 to verify the main test data and confirm that the main test data is recorded in the flash memory chip 100. Where processor 300 runs verification test firmware 700, verification test data may be obtained. In step S50, the main test data and the verification test data are stored in the flash memory chip 100, thereby completing the test of the memory device 50.
The embodiments of the invention disclosed above are intended merely to aid in the explanation of the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (10)
1. A storage device, comprising at least:
the system comprises an internal memory, a main test firmware and a verification test firmware, wherein the internal memory stores the functional firmware, the main test firmware and the verification test firmware, and the main test firmware is provided with an operation frequency threshold;
the processor is electrically connected with the internal memory, when the storage device is powered on, the processor reads and circularly runs the main test firmware until the running frequency of the main test firmware reaches the running frequency threshold value, and main test data are obtained and stored, wherein after the main test data are obtained, the processor randomly runs the verification test firmware to obtain and store the verification test data; and
and the flash memory chip is connected with the processor and stores the main test data and the verification test data.
2. A memory device according to claim 1, wherein the functional firmware comprises an enable module, and wherein the processor reads and runs the main test firmware when powered up when the enable module is in the disabled state, and wherein the processor runs the main test firmware when receiving a host signal when the enable module is in the enabled state.
3. The memory device of claim 2, wherein the main test firmware comprises an identification bit recognition module that sets an identification bit in the processor when the processor does not receive the host signal and the processor runs the main test firmware.
4. The storage device according to claim 3, wherein the main test firmware comprises a running number recognition module, and when the identification position is set, the running number recognition module acquires and records the running number of the main test firmware.
5. The storage device according to claim 3, wherein the operation number recognition module is configured to set an operation period, and the operation number of the main test firmware is the number of the operation period completed by the processor after the identification position.
6. The storage device according to claim 1, wherein the main test firmware comprises a main test module, and the main test module comprises a plurality of test units, and the operation data of the test units is the main test data.
7. The storage device according to claim 1, wherein the verification test firmware comprises a plurality of log information acquisition units for reading the stored data in the flash memory chip.
8. A method of testing a memory device, comprising the steps of:
providing a storage device comprising an internal memory, a flash memory chip, and a processor, wherein the internal memory comprises functional firmware;
writing main test firmware into the internal memory, wherein the main test firmware is provided with a running time threshold;
when the storage device is powered on, the processor reads and circularly runs the main test firmware until the running times of the main test firmware reach the running time threshold, and main test data are obtained and stored;
writing verification test firmware into the internal memory, and after obtaining the main test data, the processor randomly runs the verification test firmware to obtain and store verification test data; and
storing the main test data and the verification test data in the flash memory chip.
9. The method of claim 8, wherein the functional firmware comprises an enabling module, and wherein the enabling module is configured to be disabled before the main test firmware is executed by the processor.
10. The method of claim 8, wherein the step of obtaining the number of runs comprises:
setting an operation period;
after the identification position of the main test firmware is set, timing the running process of the main test firmware; and
and acquiring the number of running cycles experienced by the main test firmware according to the running time of the main test firmware, and taking the number of the running cycles as the running times.
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