CN114065674A - Method and device for predicting EOS failure rate of CMOS device - Google Patents
Method and device for predicting EOS failure rate of CMOS device Download PDFInfo
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Abstract
The embodiment of the invention provides a method and a device for predicting EOS failure rate of a CMOS device, belonging to the technical field of integrated circuits. The prediction method comprises the following steps: determining the basic EOS failure rate of the CMOS device; determining influence factors influencing EOS failure rate in all process links of the CMOS device; obtaining an evaluation result of EOS failure rate evaluation for each influence factor, and determining a weight value showing the influence degree of the influence factor on the EOS failure rate based on the evaluation result, wherein the larger the weight value is, the larger the influence degree of the influence factor on the EOS failure rate is; and establishing a prediction model aiming at the EOS failure rate based on the basic EOS failure rate and the weight values corresponding to the influence factors so as to obtain a predicted value of the EOS failure rate of the CMOS device. According to the invention, each process link of the CMOS device is systematically analyzed, each influence factor influencing the EOS failure rate of the CMOS device is comprehensively considered, and the obtained predicted value of the EOS failure rate is more accurate, so that accurate prediction basis can be provided for the EOS reliability prediction.
Description
Technical Field
The invention relates to the technical field of CMOS (complementary metal oxide semiconductor) devices, in particular to a method and a device for predicting EOS (Electrical Overstress) failure rate of a CMOS device.
Background
EOS is a main fault of field return of CMOS devices and is also a failure phenomenon which is most concerned among the field return faults of CMOS devices. EOS failures are usually manifested as short-circuiting or burning out of the chip at the pins, package, and inside the chip. The reasons for generating the EOS failure are many, and the reasons include field failure caused by potential electrostatic damage introduced in the processes of processing, manufacturing, transporting or testing in a wafer factory or a packaging factory; there are also field failures due to insufficient ESD (Electro-Static discharge) design or EMC (Electro magnetic Compatibility) design of the chip; and EOS damage due to harsh field use environments and improper application. However, there is currently a lack of comprehensive predictive solutions for CMOS device failure rates due to EOS.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a method and an apparatus for predicting an EOS failure rate of a CMOS device, so as to solve at least the above existing technical problems.
In order to achieve the above object, in a first aspect, an embodiment of the present invention provides a method for predicting an EOS failure rate of a CMOS device, where the method includes: determining a base EOS failure rate of the CMOS device; determining influence factors influencing EOS failure rate in all process links of the CMOS device; obtaining an evaluation result of EOS failure rate evaluation for each influence factor, and determining a weight value showing the influence degree of the influence factor on the EOS failure rate based on the evaluation result, wherein the larger the weight value is, the larger the influence degree of the influence factor on the EOS failure rate is; and establishing a prediction model aiming at the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each influence factor so as to obtain a predicted value of the EOS failure rate of the CMOS device.
Preferably, the determining the basic EOS failure rate of the CMOS device includes: and determining the basic EOS failure rate of the CMOS device according to experimental data of EOS experiments on the CMOS device or field return data of field detection on the CMOS device.
Preferably, the obtaining of the evaluation result of the EOS failure rate evaluation for each influence factor includes: testing each influence factor to be suitable for one or more preset EOS failure rate evaluation items, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to the adaptation degree, wherein the higher the adaptation degree is, the lower the EOS failure rate score is; and summarizing EOS failure rate scores under all the EOS failure rate evaluation items of each influence factor to serve as evaluation results of the EOS failure rate evaluation of the influence factors.
Preferably, a weight value showing the degree of influence of the influence factor on the EOS failure rate is determined based on the evaluation result using the following formula:
wherein the content of the first and second substances,
is a weight value for the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
Preferably, the influencing factors include one or more of: the system comprises a chip-level electrostatic discharge ESD and Latch UP design factor, a chip-level electrostatic discharge ESD test quality factor, an integrated circuit electrostatic discharge ESD control factor, a system-level electromagnetic compatibility EMC test quality factor, a printed circuit board PCB schematic diagram design factor, a PCB layout and wiring design factor, a system equipment-level electromagnetic compatibility EMC design factor, a field application climate environment factor and a field application electromagnetic environment factor.
Preferably, a predictive model for the EOS failure rate is established using the following formula:
wherein the content of the first and second substances,
for the underlying EOS failure rate of the CMOS device,
is a predictive value of the EOS failure rate of the CMOS device,
、
…
is the weight value of the influence factor.
In a second aspect, an embodiment of the present invention provides an apparatus for predicting an EOS failure rate of a CMOS device, where the apparatus includes: a first determining unit, configured to determine a basic EOS failure rate of the CMOS device; the second determining unit is used for determining influence factors influencing EOS failure rate in all process links of the CMOS device; a third determining unit, configured to obtain an evaluation result of the EOS failure rate evaluation performed on each impact factor, and determine, based on the evaluation result, a weight value indicating an impact degree of the impact factor on the EOS failure rate, where a larger weight value indicates a larger impact degree of the impact factor on the EOS failure rate; and the failure rate prediction unit is used for establishing a prediction model aiming at the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each influence factor so as to obtain a prediction value of the EOS failure rate of the CMOS device.
Preferably, the first determining unit is configured to determine the basic EOS failure rate of the CMOS device by: and determining the basic EOS failure rate of the CMOS device according to experimental data of EOS experiments on the CMOS device or field return data of field detection on the CMOS device.
Preferably, the third determining unit is configured to obtain an evaluation result of the EOS failure rate evaluation for each influence factor in the following manner: testing each influence factor to be suitable for one or more preset EOS failure rate evaluation items, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to the adaptation degree, wherein the higher the adaptation degree is, the lower the EOS failure rate score is; and summarizing EOS failure rate scores under all failure rate evaluation items of each influence factor to serve as evaluation results of the EOS failure rate evaluation of the influence factors.
Preferably, the third determination unit determines a weight value showing the degree of influence of the influence factor on the EOS failure rate based on the evaluation result using the following formula:
wherein the content of the first and second substances,
is a weight value for the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
Preferably, the failure rate prediction unit establishes a prediction model for the EOS failure rate by using the following formula:
wherein the content of the first and second substances,
for the underlying EOS failure rate of the CMOS device,
is a predictive value of the EOS failure rate of the CMOS device,
、
…
is the weight value of the influence factor.
In a third aspect, an embodiment of the present invention provides a machine-readable storage medium, where instructions are stored on the machine-readable storage medium, and the instructions are configured to cause a machine to execute the method for predicting the EOS failure rate of a CMOS device according to any one of the first aspect of the present application.
In a fourth aspect, an embodiment of the present invention provides a processor, configured to execute a program, where the program is executed to perform: a method of predicting EOS failure rate of a CMOS device as claimed in any of the first aspects.
Through the technical scheme, each process link of the CMOS device is systematically analyzed, each influence factor of EOS failure of the CMOS device can be comprehensively considered, the obtained predicted value of the EOS failure rate is more accurate, and therefore accurate prediction basis can be provided for EOS reliability prediction.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a flow diagram illustrating a method for predicting EOS failure rate of a CMOS device in accordance with an exemplary embodiment;
FIG. 2 is a flowchart illustrating a method for obtaining evaluation results for EOS failure rate evaluation for each impact factor according to an exemplary embodiment;
fig. 3 is a block diagram illustrating an apparatus for predicting EOS failure rate of a CMOS device in accordance with an example embodiment.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a method for predicting an electrical overstress EOS failure rate of a CMOS device according to an exemplary embodiment, the method comprising:
and step S11, determining the basic EOS failure rate of the CMOS device.
The basic EOS failure rate may also be understood as a general failure rate, which refers to a probability that a product working to a certain time fails due to EOS within a unit time after the certain time.
For example, the underlying ESO failure rates vary from device to device. For example, the recommended value of the basic EOS failure rate of the CMOS device is 2.7/109 hours, namely 2.7 fit. The recommended value can be obtained by calculation based on historical experience data or by query of a relevant reliability standard manual.
In the preferred embodiment of the present application, the basic EOS failure rate of the CMOS device can be determined by performing statistical analysis on the CMOS device EOS experimental data or the field return data.
For example, in one aspect, the embodiment of the present application may perform different test tests on a CMOS device, for example, according to a relevant specification of the CMOS device, the CMOS device may be subjected to, for example, a parameter test, a function test, a tolerance test, or the like, so as to obtain different test data. The test data includes failure conditions of the CMOS device under different test tests. On the other hand, the embodiment of the application can also acquire field return data of the CMOS device, for example, fault data of the CMOS device in the field actual use process. And analyzing the EOS fault problem according to the obtained experimental data or the field return data, so as to obtain the basic EOS failure rate of the CMOS device. Therefore, the basic EOS failure rate of the CMOS device determined by the preferred embodiment is more matched with the actual situation of the CMOS device, and the determined basic EOS failure rate is more accurate.
And step S12, determining influence factors influencing EOS failure rate in all process links of the CMOS device.
Specifically, the process links related to the CMOS device include chip design, wafer manufacturing, package manufacturing, reliability testing, transportation protection, single board manufacturing, PCB schematic design, PCB layout and wiring design, field application environment, and the like. The CMOS device in any of the above-mentioned links may have a certain effect on its EOS failure rate. For example, CMOS devices are susceptible to ESD discharges, which can cause the devices to be damaged by electrostatic breakdown. Therefore, in the chip design process, the EOS failure rate of the CMOS device designed by the ESD protection scheme is different from that of the CMOS device not designed by the ESD protection scheme. With the ESD design, the CMOS device can effectively prevent failures due to ESD problems, so the longer the lifetime, the higher the reliability. It can be seen that whether the ESD protection scheme is adopted or not has an impact on the EOS failure rate of the CMOS device. For another example, in the field application environment link, for a CMOS device, the influence of temperature and humidity in the working environment on the device function is particularly important. If the humidity in the working environment is high, the welding spots and the wiring positions of the CMOS device on the PCB are easily corroded, and the CMOS device is broken down due to short circuit; or leakage coupling may occur due to excessively high humidity, and static electricity may be easily generated due to excessively low humidity. If the temperature of the working environment is too high or too low, which exceeds the temperature range endured by the CMOS device itself, it will also cause some damage to the CMOS device. For example, if the CMOS device is operated in the southern area and rain water is more likely, the CMOS device will have a greater impact on the EOS failure rate due to higher temperature and humidity in the southern area. Therefore, by analyzing each link of the CMOS device, whether the link affects the EOS failure rate of the CMOS device or not is judged, and further, an influence factor affecting the EOS failure rate of the CMOS device can be determined.
In a preferred embodiment of the present application, the influence factor includes one or more of the following: the system comprises chip-level ESD and Latch UP design factors, chip-level ESD test quality factors, integrated circuit ESD control factors, system-level EMC test quality factors, PCB schematic diagram design factors, PCB layout and wiring design factors, system equipment-level EMC design factors, field application climate environment factors and field application electromagnetic environment factors.
Specifically, the influence factors are determined for the chip design, wafer manufacturing, package manufacturing, reliability testing, transportation protection, single board manufacturing, PCB schematic design, PCB layout and wiring design, field application environment and other links related to the CMOS device. The embodiment of the present disclosure is not limited to the above listed influence factors, and the embodiment of the present disclosure may also determine corresponding influence factors according to actual analysis conditions of the CMOS device for other process links that influence the EOS failure rate of the CMOS device.
Step S13, obtaining an evaluation result of the EOS failure rate evaluation for each influence factor, and determining a weight value showing the influence degree of the influence factor on the EOS failure rate based on the evaluation result, wherein the larger the weight value is, the larger the influence degree of the influence factor on the EOS failure rate is.
In a preferred embodiment, fig. 2 is a flowchart illustrating a method for obtaining an evaluation result of failure rate evaluation for each influence factor according to an exemplary embodiment, where the method specifically includes:
step S21, performing a test adapted to one or more preset EOS failure rate evaluation items on each influence factor, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to an adaptation degree, wherein the higher the adaptation degree is, the lower the EOS failure rate score is.
For example, for a field application scenario of a CMOS device, the determined impact factor includes a field application climate factor. According to the determined influence factors, the temperature, the humidity and the weather condition of the site environment are analyzed, and then the evaluation items about the temperature, the humidity and the lightning condition are preset. Meanwhile, corresponding evaluation criteria are preset for the preset evaluation items. For example, the CMOS device may be preset to set different scores for different ranges. Wherein the magnitude of the score is related to the degree of impact on EOS failure rate of the CMOS device.
In a more preferred embodiment of the present application, for different evaluation items, a next level of subdivision may be performed according to the evaluation content of the evaluation item, and further, a plurality of second level evaluation items under the evaluation item.
The evaluation items preset for different influence factors and the corresponding preset evaluation criteria will be described in detail in the embodiments of the present application with reference to the following table.
TABLE 1 evaluation table of chip-scale ESD and Latch UP design factors
Table 1 mainly aims at the CMOS device design link, and obtains the evaluation results of the chip-level ESD and Latch UP design factors by determining whether the corresponding ESD design is adopted in the CMOS device design.
Specifically, evaluation items for checking an ESD design, an ESD design rule, and a Latch UP design rule are specifically set for a chip-level ESD and Latch UP design factor in a chip design link. And evaluating the entries for ESD designs. Further, for the ESD design evaluation items, the embodiments of the present application provide secondary evaluation items regarding pin ESD design, pin secondary ESD design, and ground and earth ESD protection.
For other influence factors, the evaluation items set for each influence factor and the evaluation criteria for each evaluation item are described in detail, respectively, with reference to the following tables 2 to 9.
TABLE 2 evaluation chart of quality factor of chip-level ESD test
Table 2 mainly refers to a test procedure after designing a CMOS device, and after the CMOS chip is designed, the embodiment of the present application performs different ESD tests on the CMOS device based on corresponding test standards, and determines whether the ESD design related to the CMOS device meets the specified standard.
TABLE 3 evaluation chart of ESD control factors of integrated circuit
Table 3 is mainly directed to the evaluation result of the ESD control factor of the integrated circuit obtained by determining whether the specified ESD control standard is met in the production, packaging, and transportation links of the CMOS device.
Table 4 system-level EMC test factor evaluation table
Table 4 mainly aims at the CMOS device test link, and determines whether the test result meets the specified standard by performing the related system level EMC test on the CMOS device, so as to obtain the evaluation result of the system level EMC test factor.
TABLE 5-1 PCB schematic design factor evaluation Table
TABLE 5-2 PCB schematic design factor evaluation Table
TABLE 5-3 evaluation chart of PCB schematic diagram design factor
Table 5-4 PCB schematic design factor evaluation table
Tables 5-1 to 5-4 mainly obtain evaluation results for the PCB schematic design factors by judging whether the PCB where the CMOS device is located adopts different ESD protection designs.
TABLE 6-1 PCB layout and wiring design factor evaluation chart
TABLE 6-2 PCB layout and wiring design factor evaluation chart
Table 6-3 evaluation table of PCB layout and wiring design factors
Table 6-4 evaluation table of PCB layout and wiring design factors
Table 6-5 evaluation table of PCB layout and wiring design factors
Table 6-6 evaluation table of PCB layout and wiring design factors
Table 6-7 evaluation table of PCB layout and wiring design factors
Table 6-8 evaluation table of PCB layout and wiring design factors
Table 6-9 evaluation table of PCB layout and wiring design factors
Table 6-10 evaluation table of PCB layout and wiring design factors
Tables 6-1 to 6-10 are mainly directed to the PCB design and wiring link, and analyze whether the PCB design and wiring meets the relevant standard requirements to obtain the evaluation result of the PCB layout and wiring design factor.
TABLE 7-1 evaluation chart of EMC design factor of system equipment level
TABLE 7-2 evaluation chart of EMC design factor of system equipment level
Tables 7-1 to 7-2 mainly evaluate the degree of influence of the equipment where the CMOS device is located on the EOS failure rate by determining whether the equipment EMC design is performed, and further obtain the evaluation result of the system equipment EMC design factor.
TABLE 8-1 evaluation chart of climate environmental factors for field application
TABLE 8-2 evaluation chart of climate environmental factors for field application
TABLE 8-3 evaluation chart of climate environmental factors for field application
Tables 8-1 to 8-3 are results of evaluating the influence degree of the temperature and humidity range on the EOS failure rate of the CMOS device according to the lightning, the temperature and the humidity in the field use environment of the CMOS device, and further obtaining the evaluation result of the field application climate environmental factor.
TABLE 9-1 evaluation chart of electromagnetic environmental factors for field application
TABLE 9-2 evaluation chart of electromagnetic environmental factors for field application
Tables 9-1 to 9-2 mainly analyze the degree of influence on the failure rate of the EOS according to the electromagnetic environment where the CMOS device is located, and further obtain the evaluation result of the electromagnetic environment factor applied on the site.
It should be noted that, for the different influence factors, the embodiments of the present application are not limited to the design entries in the table, and the present application may flexibly set different evaluation entries according to the actual situation of the CMOS device.
As shown in the above tables, embodiments of the present invention determine an EOS failure rate score as 0-5, wherein the higher the degree of fit, the lower the EOS failure rate score.
For example, also taking the above-mentioned ESD protection between ground and ground as an example, for this item, the embodiment of the present application first performs a ground and ground ESD protection test on the CMOS, and detects whether there is a protection circuit between all the grounds and the ground. If the detection finds that all the places and the places have the protection circuits, the result shows that the current test result has high adaptation degree with the evaluation standard aiming at the test item, and the score is the lowest score. For example, the satisfaction of the criterion is set to 0 point, the partial satisfaction is set to 3 points, and the non-satisfaction is set to 5 points.
Correspondingly, the evaluation criteria in the above table can be referred to, and the corresponding scores of the CMOS devices can be determined according to the test results of the CMOS devices for different evaluation items, respectively.
And step S22, summarizing EOS failure rate scores under all failure rate evaluation items of each influence factor to serve as evaluation results of EOS failure rate evaluation of the influence factors.
For the obtained evaluation result, the embodiment of the present application determines the weight value of each evaluation item based on a weight method, and further calculates the weight value of the influence factor. In addition, the embodiment of the application also analyzes the EOS influence degree of each evaluation item, and sets the weight coefficients for different evaluation items based on the EOS influence degree, so that the weight value of each influence factor can be obtained more accurately. The specific formula is as follows:
wherein the content of the first and second substances,
is a weight value of the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
For example, since the maximum value of the failure rate score is 5 points in the evaluation entries in the above table, the value of "a" may be 5. Taking chip-level ESD and Latch UP design factors as an example, based on the evaluation items and evaluation criteria preset in table 1, the weight values of the impact factors are:
。
step S14, establishing a prediction model for the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each influence factor, so as to obtain a predicted value of the EOS failure rate of the CMOS device.
For example, the EOS failure rate prediction model is established as follows:
wherein the content of the first and second substances,
for the underlying EOS failure rate of CMOS devices,
the weighting values of the factors are designed for the ESD and Latch-UP of the on-chip ESD,
the weighted value of the quality factor of the chip-level electrostatic discharge ESD test is obtained,
a weighted value for the ESD control factor for the integrated circuit,
a weight value for a system level EMC test quality factor,
the weight values of the design factors for the printed circuit board PCB schematic,
weight values for the printed circuit board PCB layout design factor,
the weight values for the system equipment level electromagnetic compatibility EMC design factors,
for the on-site application of the weight value of the climate environmental factor,
the weighting value of the electromagnetic environment factor is applied on site.
When the prediction model is applied, the weight value of the man may be set to 0 depending on the determined influence factor, and if there is an influence factor unsuitable or not considered for application.
Furthermore, the obtained weight values of the various influence factors are substituted into the prediction model, and a prediction value of the EOS failure rate of the CMOS device can be obtained.
With respect to the prediction method procedure of the above steps, the above prediction method will be described in detail by a more specific embodiment.
For example, the EOS failure rate index of a certain MCU chip applied in the field is predicted.
Firstly, the basic EOS failure rate of the MCU chip is obtained
. The embodiments of the present application
The recommended value for CMOS devices, i.e., 2.7fit, is used.
Secondly, analyzing all links of the MCU chip to determine influence factors influencing EOS failure rate of the MCU chip, wherein the influence factors comprise:
(chip-level ESD and Latch UP design factors) and
(chip-level ESD test quality factor) two impact factors.
And thirdly, based on the evaluation items and the evaluation criteria preset for the two influence factors, specifically referring to table 1 and table 2 in the table, adapting the MCU related test result, and determining the failure rate score under the corresponding item.
The failure rate scores for the evaluation items numbered 1 to 6 in table 1 were 5 points, 0 points, NC, 5 points, and 0 points, respectively. Wherein NC represents that no evaluation is involved for the evaluation item.
The failure rate scores for the evaluation items numbered 1 to 5 in table 2 were 0 point, 2 points, 3 points, and 5 points, respectively.
According to the failure rate score, determining the weight value of the corresponding influence factor:
chip level ESD and Latch UP design factors:
chip-level ESD test quality factor:
and finally, establishing a prediction model according to the determined influence factors:
and the basic EOS failure rate of the MCU chip is compared
Chip level ESD and Latch UP design factors
And chip-level ESD test quality factor
Substituting the weight value of (a) into the prediction model:
finally, a predicted value of EOS failure rate prediction of the MCU chip is obtained: 6.048 fit.
In summary, the prediction method of the present application has the following advantages: 1) the influence on the failure rate of the CMOS chip is analyzed systematically from each link, and the prediction result is more accurate and reliable; 2) different evaluation items and evaluation standards are flexibly set based on each link related to EOS failure rate of the CMOS device, and a prediction result is more matched with the actual result; 3) providing a prediction basis for improving reliability and accuracy for subsequent reliability prediction, and providing a reliable basis for subsequent chip design and type selection and the like; 4) the operability is strong, and the method conforms to the actual environment condition of the site where the CMOS device is located.
Based on the same concept as the above prediction method, as shown in fig. 3, an embodiment of the present application further provides a prediction apparatus 10 for EOS failure rate of a CMOS device, where the prediction apparatus 10 includes: a first determining unit 110, configured to determine a basic EOS failure rate of the CMOS device; a second determining unit 120, configured to determine an influence factor that influences an EOS failure rate in all process links of the CMOS device; a third determining unit 130, configured to obtain an evaluation result of the EOS failure rate evaluation performed on each impact factor, and determine, based on the evaluation result, a weight value indicating an impact degree of the impact factor on the EOS failure rate, where a larger weight value indicates a larger impact degree of the impact factor on the EOS failure rate; and the failure rate prediction unit 140 is configured to establish a prediction model for the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each impact factor, so as to obtain a prediction value of the EOS failure rate of the CMOS device.
In a preferred embodiment, the first determining unit 110 is configured to determine the basic EOS failure rate of the CMOS device by: and determining the basic EOS failure rate of the CMOS device according to experimental data of EOS experiments on the CMOS device or field return data of field detection on the CMOS device.
In a preferred embodiment, the third determining unit 130 is configured to obtain an evaluation result of the EOS failure rate evaluation for each influence factor in the following manner: testing each influence factor to be suitable for one or more preset EOS failure rate evaluation items, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to the adaptation degree, wherein the failure rate score is lower when the adaptation degree is higher; and summarizing failure rate scores under all EOS failure rate evaluation items of each influence factor to serve as evaluation results of the EOS failure rate evaluation of the influence factors.
In a preferred embodiment, the third determining unit 130 determines a weight value showing the degree of influence of the influence factor on the EOS failure rate based on the evaluation result using the following formula:
wherein the content of the first and second substances,
is a weight value of the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
In a preferred embodiment, the failure rate prediction unit 140 builds a prediction model for the EOS failure rate using the following formula:
wherein the content of the first and second substances,
for the underlying EOS failure rate of the CMOS device,
prediction of EOS failure rate for the CMOS deviceThe value of the one or more of the one,
、
…
is the weight value of the influence factor.
The embodiment of the present application further provides a machine-readable storage medium, where the machine-readable storage medium has stored thereon instructions for causing a machine to execute the method for predicting the EOS failure rate of the CMOS device according to the embodiment of the present application.
An embodiment of the present application further provides a processor, configured to execute a program, where the program is executed to perform: the method for predicting the EOS failure rate of the CMOS device in the embodiment is described above.
The prediction device comprises a processor and a memory, wherein the first determining unit, the second determining unit, the third determining unit, the failure rate predicting unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The core may be set to one or more values that predict the EOS failure rate of the CMOS device by adjusting the core parameters (object of the present invention).
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
An embodiment of the present invention provides a storage medium on which a program is stored, the program implementing the prediction method when executed by a processor.
The embodiment of the invention provides a processor, which is used for running a program, wherein the prediction method is executed when the program runs.
The embodiment of the invention provides equipment, which comprises a processor, a memory and a program which is stored on the memory and can run on the processor, wherein the EOS failure rate of the CMOS device is realized when the processor executes the program. The device herein may be a server, a PC, a PAD, a mobile phone, etc.
The present application further provides a computer program product adapted to perform a program of initializing the steps of the prediction method of EOS failure rate of a CMOS device as described above, when executed on a data processing device. As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (13)
1. A method for predicting EOS failure rate of a CMOS device is characterized by comprising the following steps:
determining a base EOS failure rate of the CMOS device;
determining influence factors influencing EOS failure rate in all process links of the CMOS device;
obtaining an evaluation result of EOS failure rate evaluation for each influence factor, and determining a weight value showing the influence degree of the influence factor on the EOS failure rate based on the evaluation result, wherein the larger the weight value is, the larger the influence degree of the influence factor on the EOS failure rate is;
and establishing a prediction model aiming at the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each influence factor so as to obtain a predicted value of the EOS failure rate of the CMOS device.
2. The prediction method of claim 1, wherein the determining the base EOS failure rate of the CMOS device comprises:
and determining the basic EOS failure rate of the CMOS device according to experimental data of EOS experiments on the CMOS device or field return data of field detection on the CMOS device.
3. The prediction method according to claim 1, wherein the obtaining of the evaluation result of the EOS failure rate evaluation for each influence factor comprises:
testing each influence factor to be suitable for one or more preset EOS failure rate evaluation items, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to the adaptation degree, wherein the failure rate score is lower when the adaptation degree is higher;
and summarizing EOS failure rate scores under all the EOS failure rate evaluation items of each influence factor to serve as evaluation results of the EOS failure rate evaluation of the influence factors.
4. The prediction method according to claim 3, wherein a weight value showing the degree of influence of the influence factor on the EOS failure rate is determined based on the evaluation result using the following formula:
wherein the content of the first and second substances,
is a weight value for the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
5. The prediction method according to any one of claims 1 to 4, wherein the impact factors include one or more of: the system comprises a chip-level electrostatic discharge ESD and Latch UP design factor, a chip-level electrostatic discharge ESD test quality factor, an integrated circuit electrostatic discharge ESD control factor, a system-level electromagnetic compatibility EMC test quality factor, a printed circuit board PCB schematic diagram design factor, a PCB layout and wiring design factor, a system equipment-level electromagnetic compatibility EMC design factor, a field application climate environment factor and a field application electromagnetic environment factor.
6. The prediction method of claim 1, wherein the prediction model for the EOS failure rate is established using the following formula:
wherein the content of the first and second substances,
for the underlying EOS failure rate of the CMOS device,
is a predictive value of the EOS failure rate of the CMOS device,
、
…
is the weight value of the influence factor.
7. An apparatus for predicting EOS failure rate of a CMOS device, the apparatus comprising:
a first determining unit, configured to determine a basic EOS failure rate of the CMOS device;
the second determining unit is used for determining influence factors influencing EOS failure rate in all process links of the CMOS device;
a third determining unit, configured to obtain an evaluation result of the EOS failure rate evaluation performed on each impact factor, and determine, based on the evaluation result, a weight value indicating an impact degree of the impact factor on the EOS failure rate, where a larger weight value indicates a larger impact degree of the impact factor on the EOS failure rate;
and the failure rate prediction unit is used for establishing a prediction model aiming at the EOS failure rate based on the basic EOS failure rate and the weight value corresponding to each influence factor so as to obtain a prediction value of the EOS failure rate of the CMOS device.
8. The prediction apparatus of claim 7, wherein the first determination unit is configured to determine a base EOS failure rate of the CMOS device by:
and determining the basic EOS failure rate of the CMOS device according to experimental data of EOS experiments on the CMOS device or field return data of field detection on the CMOS device.
9. The prediction apparatus according to claim 7, wherein the third determination unit is configured to obtain an evaluation result of the EOS failure rate evaluation for each influence factor in the following manner:
testing each influence factor to be suitable for one or more preset EOS failure rate evaluation items, adapting the test result to an evaluation standard preset for the corresponding item, and determining an EOS failure rate score of the influence factor under the corresponding item according to the adaptation degree, wherein the higher the adaptation degree is, the lower the EOS failure rate score is;
and summarizing EOS failure rate scores under all the EOS failure rate evaluation items of each influence factor to serve as evaluation results of the EOS failure rate evaluation of the influence factors.
10. The prediction apparatus according to claim 9, wherein the third determination unit determines a weight value showing an influence degree of the influence factor on the EOS failure rate based on the evaluation result using a formula:
wherein the content of the first and second substances,
is a weight value for the impact factor,
for the EOS failure rate score for each evaluation entry for the impact factor,
in order to evaluate the number of items,
the maximum value of the EOS failure rate score under the evaluation item.
11. The prediction apparatus of claim 7, wherein the failure rate prediction unit builds a prediction model for the EOS failure rate using the following formula:
wherein the content of the first and second substances,
for the underlying EOS failure rate of the CMOS device,
is a predictive value of the EOS failure rate of the CMOS device,
、
…
is the weight value of the influence factor.
12. A machine-readable storage medium having stored thereon instructions for causing a machine to perform the method of predicting EOS failure rate of a CMOS device of any of claims 1-6.
13. A processor configured to execute a program, wherein the program is configured to perform: the method of predicting EOS failure rate of a CMOS device as in any one of claims 1-6.
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