CN111460600B - Reliability judging method and storage device - Google Patents
Reliability judging method and storage device Download PDFInfo
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- CN111460600B CN111460600B CN201910043243.6A CN201910043243A CN111460600B CN 111460600 B CN111460600 B CN 111460600B CN 201910043243 A CN201910043243 A CN 201910043243A CN 111460600 B CN111460600 B CN 111460600B
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Abstract
The invention provides a reliability judging method, which is used for testing semiconductor devices in batches and comprises the following steps: obtaining weber distribution of life of a batch of semiconductor devices; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a confidence level; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; judging that the first slope is larger than the second slope; and determining a prediction reliability of the batch of semiconductor devices at the target quality level based on the first section.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a reliability determining method for determining reliability of a semiconductor device.
Background
Currently, most reliability predictions use global fitting (global fitting), and thus, in order to save test costs, the number of samples for reliability tests is often very limited (e.g., hundreds of samples for predicting the lifetime of a 1ppm semiconductor device), so that under the limited number of samples, the global fitting is too conservative for reliability predictions at a target quality level, and thus, a lot of manufacturing costs are required to improve quality. If the number of samples for reliability test is increased, the reliability test cost is greatly increased. Therefore, a more efficient reliability prediction method is needed.
Disclosure of Invention
In view of the above, the present invention provides a reliability determining method for testing a batch of semiconductor devices, comprising: obtaining a weber distribution (Welbull distribution) of the lifetime of the batch of semiconductor devices; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level (confidence interval); generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; judging that the first slope of the first section is greater than the second slope of the second section; and determining a predicted reliability (estimated reliability) of the batch of semiconductor devices at a target quality level (target quality level) based on the first section.
According to an embodiment of the present invention, the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first section further includes: the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
According to an embodiment of the present invention, the step of obtaining the weber distribution of the batch of semiconductor devices includes: obtaining a breakdown voltage; applying a stress voltage to an insulating layer of the batch of semiconductor devices, and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage; applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers; comparing the stress current with the base current to judge a life distribution of the semiconductor device; and obtaining the weber distribution according to the service life distribution.
According to an embodiment of the present invention, the insulating layer is an insulating layer of a front-end process, a middle-end process and/or a back-end process.
According to an embodiment of the present invention, the step of simulating the first section to the predetermined quality level to obtain the first reliability and/or the step of simulating the second section to the predetermined quality level to obtain the second reliability comprises: expanding a first number of samples of the first section to a predetermined number to be a first expanded section according to the first confidence level; and expanding a second number of samples of the second section to the predetermined number as a second expanded section according to the first confidence level, wherein the predetermined number is related to the target quality level.
According to an embodiment of the present invention, the reliability determining method further includes: combining the first expansion section with the second expansion section to generate an expansion weber distribution; dividing the extended weber distribution into at least a first analog segment and a second analog segment, wherein the first analog segment and the second analog segment meet a second confidence level, wherein the first analog segment has a first analog trend line, the second analog segment has a second analog trend line, wherein the first analog trend line has a first analog slope, and the second analog trend line has a second analog slope; judging that the first simulation slope of the first simulation section is larger than the second simulation slope of the second simulation section; and determining the predicted reliability of the batch of semiconductor devices at the target quality level based on the first simulation segment.
The present invention further provides a storage device accessible by a machine and configured to store a program of instructions, wherein the machine executes the program of instructions to perform a reliability test method for testing a batch of semiconductor devices. The reliability method comprises the following steps: obtaining a weber distribution of the lifetime of the batch of semiconductor devices; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; judging that the first slope of the first section is greater than the second slope of the second section; and determining a predicted reliability of the batch of semiconductor devices at the target quality level based on the first section.
According to an embodiment of the present invention, the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first section of the reliability determination method further includes: the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
According to an embodiment of the present invention, the step of obtaining the weber distribution of the batch of semiconductor devices in the reliability determination method includes: obtaining a breakdown voltage; applying a stress voltage to an insulating layer of the batch of semiconductor devices, and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage; applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers; comparing the stress current with the base current to judge a life distribution of the semiconductor device; and obtaining the weber distribution according to the service life distribution.
According to an embodiment of the present invention, the insulating layer is an insulating layer of a front-end process, a middle-end process and/or a back-end process.
According to an embodiment of the present invention, the step of simulating the first section to the predetermined quality level to obtain the first reliability and/or the step of simulating the second section to the predetermined quality level to obtain the second reliability of the reliability judging method includes: expanding a first number of samples of the first section to a predetermined number to be a first expanded section according to the first confidence level; and expanding a second number of samples of the second section to the predetermined number as a second expanded section according to the first confidence level, wherein the predetermined number is related to the target quality level.
According to an embodiment of the present invention, the reliability determining method further includes: combining the first expansion section with the second expansion section to generate an expansion weber distribution; dividing the extended weber distribution into at least a first analog segment and a second analog segment, wherein the first analog segment and the second analog segment meet a second confidence level, wherein the first analog segment has a first analog trend line, the second analog segment has a second analog trend line, wherein the first analog trend line has a first analog slope, and the second analog trend line has a second analog slope; judging that the first simulation slope of the first simulation section is larger than the second simulation slope of the second simulation section; and determining the predicted reliability of the batch of semiconductor devices at the target quality level based on the first simulation segment.
Drawings
FIG. 1 is a graph showing an acceleration test analysis according to an embodiment of the invention;
FIG. 2 is a flowchart showing a reliability determination method according to another embodiment of the present invention;
FIGS. 3A-3D are graphs showing acceleration test analysis according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for acquiring metrology data in accordance with one embodiment of the present invention;
FIG. 5 is a flowchart showing a reliability determination method according to another embodiment of the present invention; and
fig. 6 is a graph showing acceleration test analysis according to another embodiment of the present invention.
Symbol description:
100. graph chart
110. 310, 610 measurement data
120. Trend line
121. Upper boundary line
122. Lower boundary line
311. 611 first section
312. 612 second section
313. 613 third section
314. 614 fourth section
321. 621 first expansion section
322. 622 second expansion section
323. 623 third expansion section
324. 624 fourth expansion section
330. Expanding weber distribution
331. First analog section
332. A second analog section
341. First simulated trend line
621. First trend line
342. Second analog trend line
622. Second trend line
623. Third trend line
624. Fourth trend line
YR set years
P1 first probability
m1 first slope
m2 second slope
m3 third slope
m4 fourth slope
Y1 first year
Y2 second year line
S210-S260 step flow
S410-S460 step flow
S510-S550 step flow
Detailed Description
The following description is of embodiments of the invention. The purpose is to illustrate the general principles of the invention and should not be taken as limiting the invention, the scope of which is defined by the scope of the claims.
It is noted that the following disclosure may provide numerous embodiments or examples for practicing various features of the present invention. The following specific examples and arrangements of components are set forth only to provide a brief description of the spirit of the invention and are not intended to limit the scope of the invention. In addition, the following description may repeat use of the same reference numerals and/or letters in the various examples. However, repeated use is for purposes of providing a simplified and clear illustration only and is not intended to limit the relationship between the various embodiments and/or configurations discussed below. Furthermore, descriptions of one feature being connected to, coupled to, and/or formed over another feature described in the specification below may actually be comprised of a multitude of different embodiments, including those features that are in direct contact, or other additional features being formed between the features, etc., so that they are not in direct contact.
FIG. 1 is a graph showing an acceleration test analysis according to an embodiment of the invention. As shown in fig. 1, the horizontal axis of the graph 100 represents lifetime (in years) and the vertical axis represents cumulative failure rate (in percent (%)). According to one embodiment of the present invention, a predetermined lot of semiconductor devices are sampled and the life of the semiconductor devices is calculated using an accelerated test analysis method (e.g., by increasing temperature and/or increasing voltage to reduce test time required for testing the life of the semiconductor devices) and a calculation formula. Next, the lifetime of the obtained semiconductor devices of a predetermined lot is plotted out as measurement data 110. According to one embodiment of the present invention, the measurement data 110 is a weber distribution.
According to an embodiment of the present invention, when the lifetime of the same semiconductor device is estimated by using the predetermined lot of measurement data 110, a global fitting (global fitting) method is used to find a trend line 120 of the measurement data 110, and an extrapolation method is performed according to the trend line 120 to determine that the probability that the lifetime of the semiconductor device is not greater than the predetermined age YR is the first probability P1.
According to one embodiment of the present invention, trend line 120 meets a first confidence level and is located within a confidence interval between upper boundary line 121 and lower boundary line 122. According to an embodiment of the present invention, the tester can determine why the first confidence level is.
Since the smaller number of given lots makes the lifetime of the semiconductor device estimated by using the trend line 120 more conservative, there is a need for improvement in the reliability determination method.
Fig. 2 is a flowchart showing a reliability judging method according to another embodiment of the invention. First, weber distribution on the lifetime of the semiconductor device is obtained (step S210). And the weber distribution is divided into a plurality of sections according to the confidence level (step S220).
Fig. 3A-3D are graphs showing acceleration test analysis according to another embodiment of the present invention. As shown in FIG. 3A, the metrology data 310 corresponds to the metrology data 110 of FIG. 1, representing a Weber distribution of the lifetime of a given lot of semiconductor devices. As shown in FIG. 3A, the measurement data 310 is divided into a first section 311, a second section 312, a third section 313, and a fourth section 314, which is shown in FIG. 3B.
According to an embodiment of the present invention, the measurement data 310 is divided into a first section 311, a second section 312, a third section 313 and a fourth section 314 according to a first confidence level. According to an embodiment of the invention, the first confidence level is above 90%. According to other embodiments of the present invention, the first confidence level may be self-determining and is not limited in any way herein. According to other embodiments of the present invention, the measurement data 310 may be divided into a plurality of sections according to the first confidence level, and four sections are used herein for illustration only, and are not limited thereto in any way.
Returning to step S220 of fig. 2, when the measurement data 310 is divided into the first section 311, the second section 312, the third section 313 and the fourth section 314 shown in fig. 3B, the number of each of the first section 311, the second section 312, the third section 313 and the fourth section 314 is further increased to a predetermined number (step S230).
That is, the first section 311, the second section 312, the third section 313 and the fourth section 314 shown in fig. 3B are expanded by the first expansion section 321, the second expansion section 322, the third expansion section 323 and the fourth expansion section 324 shown in fig. 3C.
For example, when the target quality level is 1ppm, at least the total number of samples of the first section 311, the second section 312, the third section 313, and the fourth section 314 is extended to a level of 10 ten thousand (i.e., approximately the order of magnitude required for 1 ppm). For example, assume that the first section 311, the second section 312, the third section 313, and the fourth section 314 account for 10%, 40%, 35%, and 15% of the number of samples of the measurement data 310, respectively. Thus, the number of samples of the first expansion section 321, the second expansion section 322, the third expansion section 323, and the fourth expansion section 324 is 1 ten thousand, 4 ten thousand, 3.5 ten thousand, and 1.5 ten thousand, respectively. The above is for illustrative purposes only and the invention is not limited thereto in any way.
Returning to step S230, the first expansion section 311, the second expansion section 312, the third expansion section 313 and the fourth expansion section 314 of fig. 3C are combined to form the expanded weber distribution 330 shown in fig. 3D (step S240). And, the extended weber distribution 330 is divided into a plurality of analog sections again according to the second confidence level (step S250).
According to an embodiment of the invention, the second confidence level is the same as the first confidence level. According to another embodiment of the invention, the second confidence level is different from the first level. For example, the first confidence level is 90% and the second confidence level is 99% in order to obtain a more accurate trend line.
As shown in fig. 3D, the expanded weber distribution 330 is divided into a first analog section 331 and a second analog section 332, which are exemplified herein by being divided into two analog sections, but are not limited thereto in any way. And, the first simulation section 331 generates a first simulated trend line 341 according to the second confidence level, and the second simulation section 332 generates a second simulated trend line 342 according to the second confidence level.
Returning to step S250, the lifetime of the batch of semiconductor devices predicts reliability based on the simulated section with the largest slope (step S260). According to one embodiment of the present invention, reliability is the lifetime of a semiconductor device at a target quality level. As shown in fig. 3D, first analog trend line 341 has a first slope m1 and second analog trend line 342 has a second slope m2, wherein second slope m2 is greater than first slope m1. Thus, the lifetime of the batch of semiconductor devices is predicted from the second simulated trend line 342.
According to an embodiment of the present invention, for example, as shown in fig. 3D, when the target quality level is 1ppm (i.e., 0.0001%), the lifetime of the semiconductor device is the first year Y1, that is, the probability that the lifetime of the semiconductor device is not greater than the first year Y1 is 1ppm. According to one embodiment of the present invention, when predicting the lifetime of the semiconductor device based on the second simulated trend line 342, extrapolation is used to the target quality level to estimate the lifetime of the target quality level.
When predicting the lifetime of a semiconductor using the global fit approach shown in fig. 1, trend line 120 is closer to the first simulated trend line 341 of fig. 3D, such that the predicted lifetime is more conservative. When the number of samples of the metrology data 310 is expanded, it can be seen that the tail end of the expanded weber distribution 330 (i.e., the second simulation segment 332) is more significant, so that the lifetime of the semiconductor device at the target quality level can be more accurately predicted by using the reliability of the prediction performed by the second simulation segment 332 with a poor lifetime.
According to an embodiment of the present invention, the measurement data 310 relates to the withstand voltage lifetime of the insulating layer of the semiconductor device. According to an embodiment of the present invention, the insulating layer of the semiconductor is a front-end-of-line (FEOL) insulating layer. According to another embodiment of the present invention, the insulating layer of the semiconductor is an insulating layer of a middle-of-line (MEOL). According to another embodiment of the present invention, the insulating layer of the semiconductor is a back-end-of-line (BEOL) insulating layer.
FIG. 4 is a flowchart illustrating a method for acquiring metrology data in accordance with one embodiment of the present invention. First, a breakdown voltage of an insulating layer of a semiconductor device is obtained (step S410), and a stress voltage is applied to the insulating layer of the semiconductor device (step S420), wherein the stress voltage is lower than the breakdown voltage and greater than a base voltage applied to the insulating layer when the semiconductor device is operating normally.
Then, a base voltage applied to the insulating layer during normal operation of the semiconductor device is applied to the insulating layer of the semiconductor device, and a stress current flowing through the insulating layer of the semiconductor device is measured (step S430), and then a base voltage is applied to the insulating layer of the semiconductor device, and a base current flowing through the insulating layer of the semiconductor device is measured (step S440).
According to an embodiment of the present invention, the base voltage is a voltage applied to the insulating layer during normal operation of the semiconductor device, and when the semiconductor device is subjected to the acceleration test, a stress voltage higher than the base voltage is applied to the insulating layer in a special environment (high temperature and/or high voltage can be matched), so as to rapidly estimate the lifetime of the semiconductor device.
The stress current and the base current are compared to determine the lifetime distribution of the semiconductor device (step S450). According to an embodiment of the present invention, after the acceleration test, if the stress current exceeds a threshold value of the base current, it is determined that the semiconductor device has been subjected to the acceleration test and has generated an electrical leakage, thereby determining that the semiconductor device has been damaged. According to another embodiment of the present invention, if the adaptive current does not exceed the threshold value of the base current, it is determined that the semiconductor device is still operating stably after the acceleration test.
The lifetime distribution obtained according to the determination in step S450 is depicted as the measurement data 110 of fig. 1 or the measurement data 310 of fig. 3A (step S460), wherein the measurement data 110 and the measurement data 310 are weber distributions.
According to other embodiments of the present invention, the measurement data 310 relates to the lifetime of other parameters of the semiconductor device and the lifetime of various electrical parameters of the semiconductor circuit, and the lifetime of the insulating layer of the semiconductor device is exemplified above and is not limited thereto in any way.
Fig. 5 is a flowchart showing a reliability judging method according to another embodiment of the invention. As shown in fig. 5, first, weber distribution on the lifetime of the semiconductor device is acquired (step S510). And the weber distribution is divided into a plurality of sections according to the confidence level (step S520).
Fig. 6 is a graph showing acceleration test analysis according to another embodiment of the present invention. According to an embodiment of the present invention, the measurement data 610 corresponds to the measurement data 310. As shown in fig. 6, in step S510, measurement data 610 is obtained, and in step S520, the measurement data 610 is divided into a first section 611, a second section 612, a third section 613 and a fourth section 614 according to a first confidence level.
In step S530, the first, second, third and fourth trend lines 621, 622, 623 and 624 of the first, second, third and fourth segments 611, 612, 613 and 614 are generated according to the first confidence level. As shown in fig. 6, first trend line 621 has a first slope m1, second trend line 622 has a second slope m2, third trend line 623 has a third slope m3, and fourth trend line 624 has a fourth slope m4.
Next, it is determined which of the first slope m1, the second slope m2, the third slope m3 and the fourth slope m4 is large (step S540), and the expected reliability of the semiconductor device is determined by using one of the first trend line 621, the second trend line 622, the third trend line 623 and the fourth trend line 624 with the largest slope (step S550). According to an embodiment of the present invention, since the fourth slope m4 of the fourth trend line 624 is the largest, the fourth trend line 624 is used to predict the lifetime of the semiconductor device at the target quality level, i.e., the expected reliability of the semiconductor device.
According to one embodiment of the invention, for example, the target quality level is 0.0001% (i.e., 1 ppm), and the lifetime of the semiconductor device at the target quality level is the second year line Y2 according to the fourth trend line 624.
The invention provides a reliability judging method, so that the reliability of the semiconductor device is closer to the actual situation of a product, the reliability judgment of the product is simpler, and the production cost is reduced.
The foregoing is a summary of the embodiments. Those skilled in the art should readily devise and/or modify this invention based on such knowledge to effect the same and/or achieve the same advantages as the embodiments described herein. Those skilled in the art should also realize that the same arrangements do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention. The illustrative method only represents exemplary steps, but the steps do not have to be performed in the order represented. Additional steps may be added, substituted, altered in order and/or eliminated as appropriate and consistent with the spirit and scope of the disclosed embodiments.
Claims (10)
1. A reliability determination method for testing a batch of semiconductor devices, comprising:
obtaining a weber distribution of a lifetime of the batch of semiconductor devices, wherein the step of obtaining the weber distribution of the batch of semiconductor devices comprises:
obtaining a breakdown voltage;
applying a stress voltage to an insulating layer of the batch of semiconductor devices, and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage;
applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers;
comparing the stress current with the base current to judge a life distribution of the semiconductor device; and
obtaining the weber distribution according to the life distribution;
dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level;
generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope;
judging that the first slope of the first section is greater than the second slope of the second section; and
and judging a prediction reliability of the batch of semiconductor devices at a target quality level according to the first section.
2. The reliability determination method of claim 1 wherein the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level based on the first section further comprises:
the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
3. The method of claim 1, wherein the insulating layer is an insulating layer of a front-end process, a middle-end process and/or a back-end process.
4. The reliability determination method of claim 1, further comprising:
expanding a first number of samples of the first section to a predetermined number to be a first expanded section according to the first confidence level; and
expanding a second number of samples of the second section to the predetermined number as a second expanded section according to the first confidence level, wherein the predetermined number is related to the target quality level.
5. The reliability determination method of claim 4, further comprising:
combining the first expansion section with the second expansion section to generate an expansion weber distribution;
dividing the extended weber distribution into at least a first analog segment and a second analog segment, wherein the first analog segment and the second analog segment meet a second confidence level, wherein the first analog segment has a first analog trend line, the second analog segment has a second analog trend line, wherein the first analog trend line has a first analog slope, and the second analog trend line has a second analog slope;
judging that the first simulation slope of the first simulation section is larger than the second simulation slope of the second simulation section; and
and judging the prediction reliability of the batch of semiconductor devices at the target quality level according to the first simulation section.
6. A memory device accessible by a machine for storing a program of instructions, wherein execution of the program of instructions by the machine performs a reliability test method for testing a batch of semiconductor devices, the reliability test method comprising:
obtaining a weber distribution of a lifetime of the batch of semiconductor devices, wherein the obtaining the weber distribution of the batch of semiconductor devices of the reliability determination method comprises:
obtaining a breakdown voltage;
applying a stress voltage to an insulating layer of the batch of semiconductor devices, and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage;
applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers;
comparing the stress current with the base current to judge a life distribution of the semiconductor device; and
obtaining the weber distribution according to the life distribution;
dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level;
generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope;
judging that the first slope of the first section is greater than the second slope of the second section; and
and judging a prediction reliability of the batch of semiconductor devices at a target quality level according to the first section.
7. The storage device of claim 6, wherein the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level based on the first section of the reliability determination method further comprises:
the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
8. The memory device of claim 6, wherein the insulating layer is an insulating layer of a front-end process, a middle-end process, and/or a back-end process.
9. The memory device of claim 6, further comprising:
expanding a first number of samples of the first section to a predetermined number to be a first expanded section according to the first confidence level; and
expanding a second number of samples of the second section to the predetermined number as a second expanded section according to the first confidence level, wherein the predetermined number is related to the target quality level.
10. The storage device of claim 9, wherein the reliability determination method further comprises:
combining the first expansion section with the second expansion section to generate an expansion weber distribution;
dividing the extended weber distribution into at least a first analog segment and a second analog segment, wherein the first analog segment and the second analog segment meet a second confidence level, wherein the first analog segment has a first analog trend line, the second analog segment has a second analog trend line, wherein the first analog trend line has a first analog slope, and the second analog trend line has a second analog slope;
judging that the first simulation slope of the first simulation section is larger than the second simulation slope of the second simulation section; and
and judging the prediction reliability of the batch of semiconductor devices at the target quality level according to the first simulation section.
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