CN111460600A - Reliability judging method and storage device - Google Patents
Reliability judging method and storage device Download PDFInfo
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- CN111460600A CN111460600A CN201910043243.6A CN201910043243A CN111460600A CN 111460600 A CN111460600 A CN 111460600A CN 201910043243 A CN201910043243 A CN 201910043243A CN 111460600 A CN111460600 A CN 111460600A
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Abstract
The invention provides a reliability judging method for testing batches of semiconductor devices, which comprises the following steps: obtaining a weber distribution of the lifetimes of the semiconductor devices in a batch; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a confidence level; generating a first trend line of the first section and a second trend line of the second section according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; judging that the first slope is larger than the second slope; and determining the prediction reliability of the batches of semiconductor devices under the target quality level according to the first section.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a reliability determining method for determining reliability of a semiconductor device.
Background
Currently, most reliability predictions are made by global fitting (global fitting), and since the number of samples for reliability tests is very limited (for example, hundreds of samples for predicting the lifetime of a semiconductor device of 1ppm) in order to save the testing cost, the global fitting method is too conservative for the reliability prediction at the target quality level under the limited number of samples, and thus a large amount of manufacturing cost is required to increase the quality. If the number of samples for reliability testing is increased, the testing cost of reliability must be greatly increased. Therefore, a more efficient reliability prediction method is needed.
Disclosure of Invention
In view of the above, the present invention provides a reliability determination method for testing a batch of semiconductor devices, comprising: obtaining a weibull distribution (Welbull distribution) of the lifetimes of the batch of semiconductor devices; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both conform to a first confidence level (confidence interval); generating a first trend line of the first segment and a second trend line of the second segment according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; determining that the first slope of the first segment is greater than the second slope of the second segment; and determining a predicted reliability (estimated reliability) of the batch of semiconductor devices at a target quality level (target quality level) based on the first section.
According to an embodiment of the present invention, the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first section further comprises: the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
According to an embodiment of the present invention, the step of obtaining the weber distribution of the batch of semiconductor devices includes: obtaining a breakdown voltage; applying a stress voltage to an insulating layer of the batch of semiconductor devices and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage; applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers; comparing the stress current with the base current to judge the service life distribution of the semiconductor device; and acquiring the Weber distribution according to the service life distribution.
According to an embodiment of the present invention, the insulating layer is an insulating layer of a front end treatment process, a middle end treatment process and/or a back end treatment process.
According to an embodiment of the present invention, the step of simulating the first segment to the predetermined quality level to obtain the first reliability and/or the step of simulating the second segment to the predetermined quality level to obtain the second reliability comprises: expanding a first number of samples of the first segment to a predetermined number to form a first expanded segment according to the first confidence level; and expanding a second number of samples of the second segment to the predetermined number as a second expanded segment according to the first confidence level, wherein the predetermined number is related to the target quality level.
According to an embodiment of the present invention, the method for determining reliability further includes: combining the first extension segment with the second extension segment to generate an extended weber distribution; dividing the expanded weber distribution into at least a first simulation segment and a second simulation segment, wherein the first simulation segment and the second simulation segment meet a second confidence level, wherein the first simulation segment has a first simulation trend line, the second simulation segment has a second simulation trend line, the first simulation trend line has a first simulation slope, and the second simulation trend line has a second simulation slope; determining that the first analog slope of the first analog segment is greater than the second analog slope of the second analog segment; and determining the prediction reliability of the batch of semiconductor devices at the target quality level according to the first simulation section.
The present invention further provides a storage device accessible by a machine and storing a program of instructions, wherein the machine executes the program of instructions to perform a reliability testing method, wherein the reliability testing method is used for testing a batch of semiconductor devices. The reliability method comprises the following steps: obtaining a weber distribution of the lifetimes of the batch of semiconductor devices; dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level; generating a first trend line of the first segment and a second trend line of the second segment according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope; determining that the first slope of the first segment is greater than the second slope of the second segment; and determining a predicted reliability of the batch of semiconductor devices at the target quality level according to the first segment.
According to an embodiment of the present invention, the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first segment further includes: the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
According to an embodiment of the present invention, the step of obtaining the weber distribution of the batch of semiconductor devices in the reliability determination method includes: obtaining a breakdown voltage; applying a stress voltage to an insulating layer of the batch of semiconductor devices and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage; applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers; comparing the stress current with the base current to judge the service life distribution of the semiconductor device; and acquiring the Weber distribution according to the service life distribution.
According to an embodiment of the present invention, the insulating layer is an insulating layer of a front end treatment process, a middle end treatment process and/or a back end treatment process.
According to an embodiment of the present invention, the step of simulating the first segment to the predetermined quality level to obtain the first reliability and/or the step of simulating the second segment to the predetermined quality level to obtain the second reliability of the reliability determination method comprises: expanding a first number of samples of the first segment to a predetermined number to form a first expanded segment according to the first confidence level; and expanding a second number of samples of the second segment to the predetermined number as a second expanded segment according to the first confidence level, wherein the predetermined number is related to the target quality level.
According to an embodiment of the present invention, the method for determining reliability further includes: combining the first extension segment with the second extension segment to generate an extended weber distribution; dividing the expanded weber distribution into at least a first simulation segment and a second simulation segment, wherein the first simulation segment and the second simulation segment meet a second confidence level, wherein the first simulation segment has a first simulation trend line, the second simulation segment has a second simulation trend line, the first simulation trend line has a first simulation slope, and the second simulation trend line has a second simulation slope; determining that the first analog slope of the first analog segment is greater than the second analog slope of the second analog segment; and determining the prediction reliability of the batch of semiconductor devices at the target quality level according to the first simulation section.
Drawings
FIG. 1 is a graph illustrating an accelerated test analysis according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a reliability determination method according to another embodiment of the invention;
3A-3D are graphs illustrating accelerated test analysis according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for obtaining metrology data according to one embodiment of the present invention;
FIG. 5 is a flowchart illustrating a reliability determination method according to another embodiment of the invention; and
FIG. 6 is a graph illustrating an accelerated test analysis according to another embodiment of the invention.
Description of the symbols:
100 graph
110. 310, 610 measurement data
120 trend line
121 upper boundary line
122 lower boundary line
311. 611 first section
312. 612 second section
313. 613 third section
314. 614 fourth section
321. 621 first expansion section
322. 622 second expansion section
323. 623 third expansion section
324. 624 fourth expansion section
330 extended Weber distribution
331 first simulation segment
332 second analog section
341 first analog trend line
621 first trend line
342 second analog trend line
622 second trend line
623 third trend line
624 fourth trend line
Predetermined age of YR
P1 first Rate
m1 first slope
m2 second slope
m3 third slope
m4 fourth slope
First year Y1
Y2 second year line
S210-S260 process flow
S410-S460 Process flow
S510-S550 Process
Detailed Description
The following description is an example of the present invention. It is intended to illustrate the general principles of the invention and not to limit it, the scope of which is defined by the claims.
It is noted that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. The following specific examples and arrangements of components are merely illustrative of the spirit of the invention and are not intended to limit the scope of the invention. Moreover, the following description may repeat reference numerals and/or letters in the various examples. However, this repetition is for the purpose of providing a simplified and clear illustration only and is not intended to limit the scope of the various embodiments and/or configurations discussed below. Moreover, the description below of one feature connected to, coupled to, and/or formed on another feature, and the like, may actually encompass a variety of different embodiments that include the feature in direct contact, or that include other additional features formed between the features, and the like, such that the features are not in direct contact.
FIG. 1 is a graph illustrating an accelerated test analysis according to an embodiment of the present invention. As shown in fig. 1, the horizontal axis of the graph 100 represents the lifetime (in years) and the vertical axis represents the cumulative failure rate (in percentage (%)). According to an embodiment of the present invention, a predetermined lot of semiconductor devices are sampled and the life of the semiconductor devices is calculated using an accelerated test analysis method (e.g., using a method of raising the temperature and/or raising the voltage to shorten the test time required to test the life of the semiconductor devices) and a calculation formula. Next, the lifetime of the semiconductor devices of the predetermined lot is obtained, and the measurement data 110 is plotted. According to an embodiment of the present invention, the measurement data 110 is a weber distribution.
According to an embodiment of the present invention, when the lifetime of the same semiconductor device is estimated by using the predetermined lot of measurement data 110, a global fitting (global fitting) method is used to find the trend line 120 of the measurement data 110, and an extrapolation method is performed according to the trend line 120 to determine that the probability that the lifetime of the semiconductor device is not greater than the predetermined age YR is the first probability P1.
According to an embodiment of the present invention, the trend line 120 meets the first confidence level and is located in the confidence interval between the upper boundary line 121 and the lower boundary line 122. According to an embodiment of the present invention, the tester can determine what the first confidence level is.
Since the lifetime of the semiconductor device estimated by using the trend line 120 is conservative due to the small number of the predetermined lot, it is necessary to improve the reliability determination method.
Fig. 2 is a flowchart illustrating a reliability determination method according to another embodiment of the invention. First, a weber distribution regarding the lifetime of the semiconductor device is acquired (step S210). And dividing the weber distribution into a plurality of sections according to the confidence level (step S220).
Fig. 3A-3D are graphs illustrating accelerated test analysis according to another embodiment of the present invention. As shown in FIG. 3A, the metrology data 310 corresponds to the metrology data 110 of FIG. 1 and represents a Weber distribution of lifetimes for a given lot of semiconductor devices. As shown in FIG. 3A, the measurement data 310 is divided into a first section 311, a second section 312, a third section 313 and a fourth section 314, which is shown in FIG. 3B.
According to an embodiment of the present invention, the metrology data 310 is divided into a first section 311, a second section 312, a third section 313 and a fourth section 314 according to a first confidence level. According to an embodiment of the invention, the first confidence level is above 90%. According to other embodiments of the present invention, the first confidence level may be determined by itself, and is not limited thereto in any way. According to other embodiments of the present invention, the metrology data 310 may be divided into a plurality of segments according to a first confidence level, and only four segments are used for illustration and not for limitation.
Returning to step S220 of fig. 2, when the metrology data 310 is divided into the first section 311, the second section 312, the third section 313 and the fourth section 314 shown in fig. 3B, the number of each of the first section 311, the second section 312, the third section 313 and the fourth section 314 is further increased to a predetermined number (step S230).
That is, the first section 311, the second section 312, the third section 313 and the fourth section 314 shown in fig. 3B are extended by the number of the first extension section 321, the second extension section 322, the third extension section 323 and the fourth extension section 324 shown in fig. 3C.
For example, when the target quality level is 1ppm, the total number of samples of at least the first section 311, the second section 312, the third section 313 and the fourth section 314 is expanded to a level of 10 ten thousand (i.e., an order of magnitude required to approach 1 ppm). For example, assume that the first section 311, the second section 312, the third section 313 and the fourth section 314 account for 10%, 40%, 35% and 15% of the number of samples of the measurement data 310, respectively. Therefore, the number of samples of the first expansion section 321, the second expansion section 322, the third expansion section 323, and the fourth expansion section 324 is 1 ten thousand, 4 ten thousand, 3.5 ten thousand, and 1.5 ten thousand, respectively. The foregoing is by way of illustration only, and the invention is not intended to be limited thereto in any way.
Returning to step S230, the first extension section 311, the second extension section 312, the third extension section 313 and the fourth extension section 314 of fig. 3C are combined to form the extended weber distribution 330 shown in fig. 3D (step S240). The extended weber distribution 330 is subdivided into a plurality of simulation segments according to the second confidence level (step S250).
According to an embodiment of the invention, the second confidence level is the same as the first confidence level. According to another embodiment of the invention, the second confidence level is different from the first level. For example, the first confidence level is 90% and the second confidence level is 99% to obtain a more accurate trend line.
As shown in fig. 3D, the extended weber distribution 330 is divided into a first simulation segment 331 and a second simulation segment 332, which are not limited to two simulation segments. The first simulation section 331 generates a first simulated trend line 341 according to the second confidence level, and the second simulation section 332 generates a second simulated trend line 342 according to the second confidence level.
Returning to step S250, the life of the batch of semiconductor devices is predicted based on the simulation interval having the greatest slope (step S260). According to an embodiment of the present invention, the reliability is a lifetime of the semiconductor device at a target quality level. As shown in fig. 3D, the first simulated trend line 341 has a first slope m1, and the second simulated trend line 342 has a second slope m2, wherein the second slope m2 is greater than the first slope m 1. Therefore, the lifetime of the batch of semiconductor devices is predicted from the second simulated trend line 342.
According to an embodiment of the present invention, for example, as shown in fig. 3D, when the target quality level is 1ppm (i.e., 0.0001%), the lifetime of the semiconductor device is the first age Y1, i.e., the probability that the lifetime of the semiconductor device is not greater than the first age Y1 is 1 ppm. According to an embodiment of the present invention, when the lifetime of the semiconductor device is predicted according to the second simulation trend line 342, the lifetime of the target quality level is estimated by extrapolation to the target quality level.
When the lifetime of the semiconductor is predicted by using the global fitting method shown in fig. 1, the trend line 120 is closer to the first simulated trend line 341 of fig. 3D, so that the predicted lifetime is more conservative. When the number of samples of the metrology data 310 is extended, it can be seen that the tail end of the extended weber distribution 330 (i.e., the second simulation segment 332) is more significant, and thus the lifetime of the semiconductor device at the target quality level can be more accurately predicted by using the second simulation segment 332 with a shorter lifetime for prediction reliability.
The measurement data 310 relates to the voltage endurance of an insulating layer of a semiconductor device according to an embodiment of the present invention, the insulating layer of the semiconductor is an insulating layer of a front-end-of-line (FEO L) according to an embodiment of the present invention, the insulating layer of the semiconductor is an insulating layer of a middle-end-of-line (MEO L) according to another embodiment of the present invention, the insulating layer of the semiconductor is an insulating layer of a back-end-of-line (BEO L) according to another embodiment of the present invention.
FIG. 4 is a flowchart illustrating a method for obtaining metrology data according to one embodiment of the present invention. First, a breakdown voltage of an insulating layer of a semiconductor device is obtained (step S410), and a stress voltage is applied to the insulating layer of the semiconductor device (step S420), wherein the stress voltage is lower than the breakdown voltage and is greater than a base voltage applied to the insulating layer when the semiconductor device is normally operated.
Next, a base voltage applied to the insulating layer during normal operation of the semiconductor device is applied to the insulating layer of the semiconductor device and a stress current flowing through the insulating layer of the semiconductor device is measured (step S430), and a base voltage is applied to the insulating layer of the semiconductor device and a base current flowing through the insulating layer of the semiconductor device is measured (step S440).
According to an embodiment of the present invention, the base voltage is a voltage applied to the insulating layer during normal operation of a general semiconductor device, and when the semiconductor device is subjected to an accelerated test, a stress voltage higher than the base voltage is applied to the insulating layer in a special environment (which may be accompanied by high temperature and/or high voltage) so as to rapidly estimate the lifetime of the semiconductor device.
The stress current and the base current are compared to determine the lifetime distribution of the semiconductor device (step S450). According to an embodiment of the present invention, after the accelerated test, if the stress current exceeds the base current by a threshold value, it represents that the semiconductor device has been electrically leaked after the accelerated test, thereby determining that the semiconductor device is damaged. According to another embodiment of the present invention, if the adaptive current does not exceed the threshold value of the base current, it indicates that the semiconductor device is still operating stably after the accelerated test, and thus it is determined that the semiconductor device is still normal.
Based on the lifetime distribution obtained by the determination of step S450, the metrology data 110 of fig. 1 or the metrology data 310 of fig. 3A is plotted (step S460), wherein the metrology data 110 and the metrology data 310 are weber distributions.
According to other embodiments of the present invention, the measurement data 310 relates to the lifetime of other parameters of the semiconductor device and the lifetime of various electrical parameters of the semiconductor circuit, which are exemplified above and not limited in any way to the lifetime of the insulating layer of the semiconductor device.
Fig. 5 is a flowchart illustrating a reliability determination method according to another embodiment of the invention. As shown in fig. 5, first, a weber distribution regarding the lifetime of the semiconductor device is acquired (step S510). And divides the weber distribution into a plurality of sections according to the confidence level (step S520).
FIG. 6 is a graph illustrating an accelerated test analysis according to another embodiment of the invention. According to an embodiment of the present invention, the metrology data 610 corresponds to the metrology data 310. As shown in fig. 6, in step S510, the metrology data 610 is acquired, and in step S520, the metrology data 610 is divided into a first section 611, a second section 612, a third section 613 and a fourth section 614 according to a first confidence level.
In step S530, a first trend line 621, a second trend line 622, a third trend line 623 and a fourth trend line 624 of the first section 611, the second section 612, the third section 613 and the fourth section 614 are respectively generated according to the first confidence level. As shown in fig. 6, first trend line 621 has a first slope m1, second trend line 622 has a second slope m2, third trend line 623 has a third slope m3, and fourth trend line 624 has a fourth slope m 4.
Next, it is determined which of the first slope m1, the second slope m2, the third slope m3 and the fourth slope m4 is greater (step S540), and one of the first trend line 621, the second trend line 622, the third trend line 623 and the fourth trend line 624 having the largest slope is used to determine the expected reliability of the semiconductor device (step S550). According to an embodiment of the present invention, since the fourth slope m4 of the fourth trend line 624 is the largest, the fourth trend line 624 is used to predict the lifetime of the semiconductor device at the target quality level, i.e., the expected reliability of the semiconductor device.
According to an embodiment of the present invention, the target quality level is 0.0001% (i.e., 1ppm), for example, and the lifetime of the semiconductor device at the target quality level is the second year line Y2 according to the fourth trend line 624.
The invention provides a reliability judging method, which enables the reliability of a semiconductor device to be closer to the real situation of a product, the reliability of the product to be judged more simply and the production cost to be reduced.
What has been described above is a general characterization of the embodiments. Those skilled in the art should readily appreciate that they can readily use the present disclosure as a basis for designing or modifying other structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. The illustrative method represents exemplary steps only, and the steps are not necessarily performed in the order represented. Additional, alternative, changed order and/or elimination steps may be added, substituted, changed order and/or eliminated as appropriate and consistent with the spirit and scope of the disclosed embodiments.
Claims (12)
1. A reliability determination method for testing a batch of semiconductor devices, comprising:
obtaining a weber distribution of the lifetimes of the batch of semiconductor devices;
dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level;
generating a first trend line of the first segment and a second trend line of the second segment according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope;
determining that the first slope of the first segment is greater than the second slope of the second segment; and
and judging a predicted reliability of the batch of semiconductor devices under a target quality level according to the first section.
2. The method of claim 1, wherein the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first segment further comprises:
the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
3. The reliability determination method according to claim 1, wherein the step of obtaining the weber distribution of the batch of semiconductor devices comprises:
obtaining a breakdown voltage;
applying a stress voltage to an insulating layer of the batch of semiconductor devices and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage;
applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers;
comparing the stress current with the base current to judge the service life distribution of the semiconductor device; and
and acquiring the Weber distribution according to the service life distribution.
4. The method of claim 3, wherein the insulating layer is an insulating layer of a front end treatment process, a middle end treatment process and/or a back end treatment process.
5. The reliability determination method of claim 1, further comprising:
expanding a first number of samples of the first segment to a predetermined number to form a first expanded segment according to the first confidence level; and
expanding a second number of samples of the second segment to the predetermined number to be a second expanded segment according to the first confidence level, wherein the predetermined number is related to the target quality level.
6. The reliability determination method of claim 5, further comprising:
combining the first extension segment with the second extension segment to generate an extended weber distribution;
dividing the expanded weber distribution into at least a first simulation segment and a second simulation segment, wherein the first simulation segment and the second simulation segment meet a second confidence level, wherein the first simulation segment has a first simulation trend line, the second simulation segment has a second simulation trend line, the first simulation trend line has a first simulation slope, and the second simulation trend line has a second simulation slope;
determining that the first analog slope of the first analog segment is greater than the second analog slope of the second analog segment; and
and according to the first simulation section, judging the prediction reliability of the batch of semiconductor devices under the target quality level.
7. A memory device accessible by a machine and storing a program of instructions, the machine executing the program of instructions to perform a reliability testing method for testing a batch of semiconductor devices, the reliability testing method comprising:
obtaining a weber distribution of the lifetimes of the batch of semiconductor devices;
dividing the weber distribution into at least a first section and a second section, wherein the first section and the second section both meet a first confidence level;
generating a first trend line of the first segment and a second trend line of the second segment according to the first confidence level, wherein the first trend line has a first slope and the second trend line has a second slope;
determining that the first slope of the first segment is greater than the second slope of the second segment; and
and judging a predicted reliability of the batch of semiconductor devices under a target quality level according to the first section.
8. The memory device of claim 7, wherein the step of determining the predicted reliability of the batch of semiconductor devices at the target quality level according to the first segment of the reliability determination method further comprises:
the prediction reliability is obtained by performing an extrapolation of the first segment to the target quality.
9. The storage apparatus according to claim 7, wherein the step of obtaining the weber distribution of the batch of semiconductor devices of the reliability determination method includes:
obtaining a breakdown voltage;
applying a stress voltage to an insulating layer of the batch of semiconductor devices and measuring a stress current of the insulating layer, wherein the stress voltage is lower than the breakdown voltage and higher than a base voltage;
applying the base voltage to the insulating layers of the batch of semiconductor devices and measuring a base current of the insulating layers;
comparing the stress current with the base current to judge the service life distribution of the semiconductor device; and
and acquiring the Weber distribution according to the service life distribution.
10. The memory device of claim 9, wherein the insulating layer is a front end of line, a middle end of line, and/or a back end of line insulating layer.
11. The memory device of claim 7, further comprising:
expanding a first number of samples of the first segment to a predetermined number to form a first expanded segment according to the first confidence level; and
expanding a second number of samples of the second segment to the predetermined number to be a second expanded segment according to the first confidence level, wherein the predetermined number is related to the target quality level.
12. The storage device according to claim 11, wherein the reliability determining method further comprises:
combining the first extension segment with the second extension segment to generate an extended weber distribution;
dividing the expanded weber distribution into at least a first simulation segment and a second simulation segment, wherein the first simulation segment and the second simulation segment meet a second confidence level, wherein the first simulation segment has a first simulation trend line, the second simulation segment has a second simulation trend line, the first simulation trend line has a first simulation slope, and the second simulation trend line has a second simulation slope;
determining that the first analog slope of the first analog segment is greater than the second analog slope of the second analog segment; and
and according to the first simulation section, judging the prediction reliability of the batch of semiconductor devices under the target quality level.
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