JP2013024671A - Semiconductor integrated circuit test method, system, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method, system, and program, which reduce a test time required for testing the entire lot and prevent a non-defective product from being erroneously determined as a defective.SOLUTION: In testing the lot of LSIs (devices under test) which have the same configuration, a function test of a first LSI is executed using an execution test rate 1. If the function test result is pass, the function test of a second LSI is executed using the execution test rate 1. If it is fail, a retest of the first LSI is performed using an execution test rate 2. If the retest is passed, the execution test rate 1 is updated to a value that is obtained by adding an additional test rate to a current value, and the function test of the second LSI is executed using the updated execution test rate 1. If both of the function tests of the first LSI using the execution test rates 1 and 2 fail, the first LSI is determined to be defective.

Description

  The present invention relates to a test technique for a semiconductor integrated circuit.

  In response to the demand for higher functionality and higher performance of electronic equipment, various IP (Intellectual Property) cores have been installed, and semiconductor integrated circuits (LSIs) that have become larger in scale have been developed and manufactured (mass produced). . As semiconductor integrated circuits (LSIs) have become larger in scale and higher in functionality, test time has increased in testing of semiconductor integrated circuits (LSIs) using test devices and the like. An increase in test time leads to an increase in test cost. In particular, since the number of test patterns applied from a test apparatus to a semiconductor integrated circuit (LSI) to be tested (Device Under Test: also referred to as “DUT”) has increased, the function test (Functional Test) is an overall test. As the proportion of time has increased, the need to reduce the test time for these function tests has increased.

  For example, Patent Document 1 discloses a normal semiconductor device test for the purpose of obtaining an optimum test rate for shortening the test time regardless of the test environment. Before performing the function test at, SHMOO of each function test is executed as a preliminary test. From the result of the SHMOO, the test rate (test speed: time of one test period in the functional test, reciprocal of the test frequency) Calculate the margin and correct or shorten the test rate according to the calculated margin, and then perform the function test of the semiconductor device using the modified test rate as usual, so that the test rate is appropriate To reduce the total test time of semiconductor devices Method is disclosed.

  FIG. 10 is a diagram cited in FIG. 1 of Patent Document 1, and is a flowchart showing an LSI function test method (in FIG. 10, the reference numerals in FIG. 1 of Patent Document 1 are changed). A method for determining the optimum test rate for each function test will be described with reference to FIG.

  In step 1004, the test program is transferred into the memory 10 (FIG. 5 of Patent Document 1). In step (step) 1001, SHMOO of function test 1 is executed to extract the limit value of the operation test rate of the device under test. In the SHMOO execution step, the voltage and test rate of the power supply terminal of the device under test are changed in stages, and the function test is executed at each change point so that the device under test has any value of the power supply terminal. This is a step for obtaining the two-dimensional characteristics of the power supply voltage versus the test rate of the device under test indicating whether it normally operates (passes) up to the range of voltage and test rate. SHMOO has a function test preset. It is executed to investigate whether there is a sufficient margin in the voltage of the power supply terminal and the test rate. Some test equipment has the SHMOO function.

  In step 1002, the difference (margin) between the operation test rate limit value of the device under test extracted in step 1001 and the originally set operation test rate is larger or smaller than an arbitrarily determined threshold value. If the margin of each function test is equal to or greater than a threshold value, it is determined that the test rate can be shortened, and the test rate information section on the memory 10 (FIG. 5 of Patent Document 1) is stored. Update. That is, if it is determined that the margin is larger than the threshold value, the test rate for executing the function test is originally set as the test rate, and the limit value of the operation test rate of the device under test extracted in the step 1001 If it is determined that the rate is small, the test rate for executing the function test is not updated from the original set value.

  When the above preliminary tests (steps 1001 and 1002) for all the function tests are completed, the process proceeds to step 1003, which is a normal test. In step 1003, a function test is executed at the operation test rate set in step 1002.

JP 2002-156424 A

  The inventor's analysis regarding the related art is shown below.

  In the related technology, in the SHMOO execution step of step 1001 in FIG. 10, the function test is executed a plurality of times for the device under test corresponding to the combination of the set values of the power supply voltage and the test rate. In general, in order to set the optimum test rate of the function test from the execution result of SHMOO, at least the test rate is set in steps of, for example, about 5 to 10 times from the initial setting value for a given power supply voltage. It is necessary to change the function test for each set value. In this case, the execution time of the function test in SHMOO is at least 5 to 10 times longer than the function test in step 1003 (normal test).

  In the test method of Patent Document 1 shown in FIG. 10, before executing the function test in step 1003 (normal test), by performing steps 1001 and 1002 as a preliminary test, the test time of step 1003 is reduced. It is intended to shorten. However, when the number of devices under test (LSI) is large and the preliminary test (step 1001 and step 1002) is executed for each test of each device under test, the test time required for the preliminary test is enormous. Become.

  For this reason, when a large number of LSIs to be tested are intended to shorten the total test time including the preliminary test (steps 1001 and 1002 in FIG. 10) and the normal test (step 1003 in FIG. 10), It is necessary to set the number of times the test is executed (total test time of the preliminary test) so as not to exceed the test time that can be shortened in step 1003.

  As a result, the number of executions of the preliminary test (steps 1001 and 1002) is smaller than the number of devices under test (LSI) to be tested in the normal test (optimum test rate) in step 1003. In this case, in FIG. 10, the test time of the entire flow is the shortest only for the first execution of the normal test of the device under test (LSI) (step 1003) (only once), and the preliminary test (step 1002 and 1003).

  FIG. 9 schematically shows the distribution of the minimum test rate at which each LSI can operate normally in the function test of the LSI lot. FIG. 9 is a diagram newly created for the present specification by the present inventor in order to explain the problems of the related art. FIG. 9 shows that the preliminary test (1001 and 1002 in FIG. 10) is performed on the LSI that executes the normal test (1003 in FIG. 10) in FIG. It represents the case where the test was executed.

  In FIG. 9, the horizontal axis 902 represents the test rate, and the vertical axis 901 represents the number of LSIs (devices under test). Reference numeral 903 denotes a distribution of the minimum test rate at which each LSI in a lot (LSI group) can operate normally (substantially a normal distribution). Reference numeral 906 on the horizontal axis 902 represents an example of the test rate (default value) of the normal test before being reduced to the optimum test rate.

  For example, the minimum operation rate of the first LSI tested in the preliminary test SHMOO (1101 in FIG. 10) (the lower limit of the test rate that passed the function test of the device under test in SHMOO) was the operation rate of the point 907. In this case, the calculated optimum test rate of the normal test is set to a test rate 908 that is an intermediate value between the point 907 and the test rate 906.

  In this case, an LSI in which the operation rate (reciprocal of the normal operating frequency) in the lot is distributed to the right of the test rate 908 is the function at the test rate 908 in the normal test (1003 in FIG. 10). As a result of the test, it is determined as FAIL (defective).

  That is, in the normal test (1003 in FIG. 10), if the function test is executed at the test rate 906, the LSI that is determined to be PASS (non-defective product) executes the function test at the test rate 908. It will be erroneously determined as FAIL. As a result, the yield of the lot is reduced below the original value of the lot.

  Further, for example, in the preliminary test, when the minimum operation rate of the first LSI tested by SHMOO is the operation rate of the point 905, the calculated optimum test rate of the normal test is an intermediate value between the point 905 and the test rate 906. The test rate 909 is a value. In this case, there are almost no LSIs whose operation rate is distributed to the right of the test rate 909 in the lot, and PASS is performed in the normal test (1103 in FIG. 10), so that the yield is not lowered. However, since the test rate 909 is a value close to the test rate 906 before being reduced to the optimal test rate, the effect of reducing the test time due to the execution of the preliminary test is reduced.

  As described above, the test time of the preliminary test SHMOO (1001 in FIG. 10) takes 5 to 10 times as long as that of the normal test. Therefore, the test time of the normal test (1003 in FIG. 10) is calculated according to the calculated optimum test rate. When the test time increased by SHMOO (1001 in FIG. 10) of one preliminary test becomes larger than the shortened test time, the total test time of the entire flow of FIG. 10 increases.

  As described above, in the related technology, if the number of preliminary test executions is increased, the total test time of the preliminary test and the normal test cannot be shortened, and the number of preliminary test executions is reduced. However, depending on the value of the calculated optimum test rate, there arises a problem that the yield is lowered from the original value or the entire test time is increased.

  In order to solve at least one of the above problems, the present invention is generally configured as follows (however, the present invention is not limited to the following).

According to one aspect of the present invention, in testing at least the first and second devices under test composed of semiconductor integrated circuits having the same configuration,
Based on the test result of the function test at the first test rate of the first device under test,
In the case of a failure, based on the test result of the function test of the first device under test at a predetermined second test rate having a value larger than the first test rate, in the case of a pass,
The first test rate is updated to a value increased by an addition test rate of a predetermined value, and the result of the function test at the first test rate passes through the first device under test. As in the case of the
When the test results of the function test at the first and second test rates of the first device under test are both failed, the first device under test is determined to be defective with respect to the function test;
Semiconductor integration for performing a function test of the second device under test using the first test rate or the first and second test rates in the same procedure as the first device under test. A method for testing a circuit is provided. Alternatively, a test program for realizing the above method on a tester or a system for realizing the above method on a tester is provided.

  According to the present invention, it is possible to shorten the test time of the entire lot, which is a set of devices under test, and to avoid erroneously determining that a non-defective product is defective.

It is a flowchart for demonstrating the test method of LSI of one execution form of this invention. It is a flowchart explaining the procedure which calculates | requires an initial test rate in one execution form of this invention. It is a flowchart explaining the procedure which calculates | requires the maximum test rate in one execution form of this invention. It is a flowchart explaining the procedure which calculates | requires an addition test rate in one execution form of this invention. It is a flowchart explaining the process 213 of FIG. It is a figure explaining the example which determines the range in which a minimum value exists from four average test rates. It is a figure which shows distribution of the operation rate of several LSI. It is a figure which shows an example of the whole structure of the test system of one execution form of this invention. It is a figure which shows the distribution of the operation rate of LSI, and shows the problem of a prior art. 10 is a flowchart showing a test method of Patent Document 1.

According to some preferred embodiments of the present invention, in order to sequentially test at least the first and second devices under test composed of semiconductor integrated circuits having the same configuration, the function test of the first device under test is performed in the first manner. The test of the first test rate is performed based on the test result of the function test at the first test rate (execution test rate 1) of the first device under test. When the result is a failure (FAIL of 102B1 in FIG. 1), the second test rate (execution test rate 2), which is larger than the first test rate (execution test rate 1), is the second test rate. A function test of one device under test is performed, and the second test rate (execution test) of the first device under test is performed. Based on the test result of the function test according to the trait 2), when the test result of the second test rate is a pass (PASS of 102B2 in FIG. 1), the first test rate (execution test rate 1) is set in advance. When the result is updated to a value increased by a predetermined value added test rate (102B3 in FIG. 1), and the result of the function test at the first test rate passes through the first device under test. In the same manner as above, the non-defective product is determined for the function test (102B4 in FIG. 1),
When the function tests at the first and second test rates of the first device under test are both fail (FAIL of 102B1 in FIG. 1 and FAIL of 102B2 in FIG. 1), the first The device under test is determined to be defective with respect to the function test (102B5 in FIG. 1), and the function test of the second device under test is performed at the first test rate (execution test rate 1 at 102B1 in FIG. 1), or Using the first and second test rates (execution test rates 1 and 2 of 102B1 and 102B2 in FIG. 1), the same procedure as that of the first device under test is performed.

More specifically, according to one of the preferred embodiments, the initial test rate of the function test executed on the first device under test (LSI) in the device under test set (lot) is set to the first test rate (execution test). Rate 1)
Step 1 (102A in FIG. 1) of setting a maximum test rate, which is an upper limit test rate that guarantees normal operation of all of the plurality of LSIs, as a second test rate (execution test rate 2);
Step 2 (102B1 in FIG. 1) of performing an LSI function test using the first test rate;
When the result of the function test in the step 2 is a failure, the function test is performed again on the LSI that has been subjected to the function test in the step 2 by using the second test rate (FIG. 3). 1 102B2),
When the test result of the function test in the step 3 is a pass, a value obtained by adding the addition test rate to the first test rate (execution test rate 1) is used as a first test rate (execution test of the next LSI). Step 4 (102B3 in FIG. 1) to set as rate 1),
When the test result of the function test in the step 2 is pass, the LSI is regarded as a non-defective product (102B4 in FIG. 1), and the process proceeds to the function test of the next LSI,
If the test result of the function test in the step 2 is fail, the step 3 is executed. If the test result of the function test in the step 3 is fail, the LSI is regarded as a defective product (102B5 in FIG. 1). The process proceeds to the step 2 (102B1 in FIG. 1), which is the step of executing the LSI function test, and when the test result of the function test in the step 3 is pass, the step 4 (102B3 in FIG. 1) is executed. Then, a series of processes of making the LSI non-defective (102B4 in FIG. 1) and proceeding to the step 2 (102B1 in FIG. 1), which is the next LSI function test execution step, are performed for all the LSIs in the lot. Repeat until the function test is complete.

  Until now (before the filing of the present application), the function test was executed at the operation test rate fixed to the worst value (maximum test rate) of the operation test rate in the timing verification, regardless of the quality of the LSI manufacturing.

  On the other hand, according to the preferred embodiment of the present invention, in step 2, it is possible to perform a test at a first test rate (initial test rate) with a shortened value in accordance with the quality of LSI manufacturing. For this reason, it becomes possible to shorten the test time of the whole lot.

  In addition, there is a variation in operation test rate characteristics within the LSI manufacturing range, and even if FAIL is performed in step 2, the test can be performed at the maximum test rate in step 3, so that a non-defective product is erroneously determined as a defective product. There is no. In the following, a description will be given in connection with some exemplary embodiments.

<Exemplary Embodiment>
FIG. 8 is a diagram showing an example of a system configuration of a test system using an LSI tester for executing a test program creation method and an LSI function test according to the present invention.

  Referring to FIG. 8, an LSI tester 401, a computer device 407, and a network 406 connecting them are provided. The LSI tester 401 includes a processing unit 402 configured by a CPU (Central Processing Unit), a recording medium 403, an input / output unit 404 serving as an input / output interface, and an LSI tester test control unit 405. The computer device 407 includes a recording medium 409, a processing unit 408 configured by a CPU (Central Processing Unit), and an input / output unit 410 that is an input / output interface.

  A network 406 connects communication between the computer device 407 and the LSI tester 401. For example, the network 406 can be a mobile communication network, a private line network, various networks including wired communication and wireless communication such as a LAN (Local Area Network), or a network in which these networks are connected to each other. It is.

  The recording medium 403 of the LSI tester 401 stores a test program and a test pattern. The recording medium 403 includes a storage device such as a hard disk, a RAM (Random Access Memory), and a ROM (Read Only Memory). Further, the LSI tester 401 reads and executes a test program and a test pattern for realizing the function of the LSI tester 401 stored in the recording medium 403 by the processing unit 402, and performs a test via the LSI tester test control unit 405. The function of the LSI tester 401 is realized by transmitting and receiving signals to and from the target LSI (device under test) 400. Each execution program and pattern is stored in the recording medium 403 from the outside by an administrator of the LSI tester using an input / output unit 404 such as a keyboard, a mouse, or an LCD (Liquid Crystal Display). The LSI to be tested 400 is mounted on an LSI mounting apparatus (411) included in the LSI tester 401, thereby executing the above test.

  The computer device 407 executes test parameter creation described later. The computer device 407 is a general general-purpose computer such as a personal computer. Information on ION values and timing verification results, which will be described later, is stored in the storage medium 409 via the input / output unit 410. The processing unit 408 creates a test parameter to be described later using information on the ION value and the timing verification result stored in the storage medium 409. The computer device 407 can communicate with the LSI tester 401 via the network 406. The computer device 407 is connected to the LSI tester 401 via the network 406 and stores the test parameters in the storage unit 403.

  Note that the test system in FIG. 8 is merely an example of a typical configuration, and the method, program, and the like according to the present invention are arbitrary test systems that are computer-controlled and capable of executing an LSI function test. Can be implemented. In FIG. 8, the computer device 407 is a general general-purpose computer, but it can be replaced with a computer (processing unit, CPU) having a man-machine interface or a network interface in an LSI tester.

  FIG. 1 is a flowchart for explaining a function test procedure of a device under test (LSI) by the test system of FIG. 8 in one embodiment of the present invention. With reference to FIG. 1 and FIG. 8, the procedure of the LSI function test in this embodiment will be described.

Step 101:
In the computer device 407, various parameter values (initial test rate, maximum test rate, addition test rate) necessary for the function test are calculated and stored in the storage medium 409.

  The initial test rate is a test rate at the start of the test for the lot to be tested, and is an optimum test rate calculated in consideration of manufacturing variation and characteristics of the lot.

  The maximum test rate is the maximum test rate of each LSI in the lot.

  The addition test rate is an increment value when the test rate to be executed for the function test of the next LSI is increased when a failure is determined at the initial test rate.

  A method for calculating these three test rates will be described later.

Step 102:
In the LSI tester 401, a function test of a group (lot) of LSIs to be subjected to the function test is executed. Hereinafter, the process in step 102 will be described in detail. Here, in step 102, it is assumed that the test is sequentially performed on each LSI in the lot.

Step 102A:
In step 102B1, which will be described later, the initial test rate calculated in step 101 is set as the test rate for the function test executed in the first LSI, and the maximum test calculated in step 101 is set as the test rate for the function test executed in step 102B2, which will be described later. Set the rate. At this time, the test rate executed in step 102B1 is set to “execution test rate 1”, and the test rate executed in step 102B2 is set to “execution test rate 2”. In this step 102A, the initial test rate and the maximum test rate stored in the storage medium 409 of the computer device 407 are set to the execution test rate 1 area (not shown) of the storage medium 403 of the LSI tester 401 via the network 406. Stored in an execution test rate 2 area (not shown). Note that the process 102A may be executed once in a function test of a certain lot.

Step 102B:
A function test is executed on one LSI in the lot. The LSI to be tested is arbitrarily selected by the LSI tester 401. At this time, it is also possible to select the LSI to be tested from the input / output unit 404 from the outside.

  Hereinafter, the process in the step 102B will be described in detail.

Step 102B1:
The LSI tester 401 executes a function test using the execution test rate 1 stored in the storage medium 403. The test result is stored in the storage medium 403 and determined by the processing unit 402. If the determination of the test result is FAIL, the process proceeds to step 102B2, and if it is PASS, the process proceeds to step 102B4.

Step 102B2:
The function test is executed again using the execution test rate 2 stored in the storage medium 403. The test result is stored in the storage medium 403 and determined by the processing unit 402, as in the step 102B1. If the determination of the test result is PASS, the process proceeds to step 102B3. If the test result is FAIL, the process proceeds to step 102B5.

  Note that the test pattern for the function test using the execution test rate 2 in step 102B2 is the same as the test pattern for the function test using execution test rate 1 in step 102B1.

Step 102B3:
The test rate is updated by adding the value of the added test rate calculated in step 101 to the value of the execution test rate 1 in which the function test is executed in step 102B1, and the process proceeds to step 102B4. In this step 102B3, the addition test rate stored in the storage medium 409 of the computer device 107 is added to the execution test rate 1 of the storage medium 403 of the LSI tester 401 via the Internet 406 to update the execution test rate 1.

Step 102B4:
The LSI for which the function test has been executed is determined to be a non-defective product, and the process proceeds to Step 102C. In FIG. 1, in the lot test, tests other than the function test of the LSI as the device under test (for example, DC test) are omitted. Therefore, the non-defective product determination in step 102B4 means that the non-defective product determination has been made with respect to the function test, and all tests (DC test, etc.) other than the function test not shown are passed.

Step 102B5:
The LSI for which the function test has been executed is determined to be defective, and the process proceeds to step 102C.

Step 102C:
It is determined whether or not the function test of all the LSIs in the lot has been completed. Here, for example, the determination can be made based on whether the LSI tester 401 has executed the test of the number of LSIs to be tested.

  If it is determined in step 102C that the function test for all the LSIs in the lot has been completed, the test is terminated.

  On the other hand, if it is determined in step 102C that the function test for all the LSIs in the lot has not been completed, the process returns to step 102B1, and the function test for the next LSI is performed at the test rate updated in step 102B3. Run.

  Next, a method of calculating various parameter values (initial test rate, maximum test rate, addition test rate) necessary for the function test, which is executed in the computer apparatus 407, will be described.

  2, 3 and 4 show in detail the flow of setting the test parameters for the LSI function test in step 101 of FIG.

<Initial test rate>
FIG. 2 is a flowchart showing a procedure for obtaining an initial test rate in step 101 of FIG. The initial test rate is obtained by the following process.

Step 204:
ON current values (referred to as ION values) 201 of a plurality of LSI transistors;
An average operation rate value 202 obtained by timing verification assuming an ION value near the center of the LSI manufacturing variation;
A maximum operation rate value 203 obtained by timing verification assuming an ION value under worst conditions of LSI manufacturing variation;
Is calculated from the storage device, and the operation rate Rn for each of the extracted LSIs is calculated and stored in the storage device using the following equation (1).

  Note that the ION value 201 is measured by, for example, extracting several LSIs in a lot in advance after manufacturing the LSI, and using, for example, a dedicated transistor for characteristic measurement prepared in advance in the LSI.

  The operation rate value 202 is obtained by using the ION value of a transistor near the center of LSI manufacturing variation in timing verification performed during LSI design (step of analyzing and verifying LSI timing operation using a timing verification tool or the like). The maximum delay value between flip-flops in the LSI (the maximum delay value between flip-flops whose timing has been verified) is obtained.

  Similarly, the operation rate value 203 is the maximum delay value between all the flip-flops obtained by using the ION value of the transistor with the slowest operation speed of the LSI manufacturing variation in the timing verification performed at the time of LSI design.

However,

Step 206:
An average operation rate μ207 of the operation rate Rn205 calculated in step 205 (assuming a normal distribution as a distribution) is calculated.

Step 209:
The average operation rate 207 calculated in step 206 is set to the initial test rate (Rmin) 210 (stored in the storage device).

<Maximum test rate>
FIG. 3 is a flowchart showing a procedure for obtaining the maximum test rate in step 101 of FIG. The maximum test rate is determined by the following process.

Step 211:
The value of the maximum operation rate 203 obtained from the timing verification assuming the worst condition ION value of LSI manufacturing variation is set as the maximum test rate 212.

<Additional test rate>
FIG. 4 is a flowchart showing a procedure for obtaining the addition test rate in step 101 of FIG. The addition test rate is obtained by the following process.

Step 216:
The operating rate Rn205 is approximated to a normal distribution, and its standard deviation σ208 is calculated.

Step 213:
Based on the standard deviation 208, the initial test rate 210, the maximum test rate 212, and the number of LSIs 214 in one lot calculated in step 216, an addition test rate 215 is calculated.

  FIG. 5 is a diagram for explaining the procedure for calculating the addition test rate in step 213 of FIG. FIG. 5 shows a flow for obtaining the addition test rate α215 by numerical calculation from the standard deviation σ208, the maximum test rate Rmax212, the initial test rate Rmin210, and the number of LSIs S214 in one lot in FIG.

Step 301:
The maximum value αmax 302 of the added test rate α is calculated by the following equation (2) using the initial test rate 210 calculated in step 209 in FIG. 2 and the maximum test rate 212 calculated in step 211 in FIG.

  αmax = (maximum test rate 212) − (initial test rate 210) (2)

  Similarly, the minimum value αmin303 of the addition test rate α is calculated by the following equation (3).

  αmin = (maximum test rate 212−initial test rate 210) ÷ (number of LSIs in one lot S214) (3)

Step 304:
Using the maximum value αmax302 and the minimum value αmin303 calculated in the step 301, the value of the point obtained by dividing the interval (section) between the maximum value αmax302 and the minimum value αmin303 by the following formulas (4) and (5) (first) , Second intermediate value) α1 (305), α2 (306).

Step 307:
Standard deviation 208,
Initial test rate 210,
Maximum test rate 212,
αmax 302,
αmin 303,
α1 305,
α2 306,
Number of LSIs in one lot S 214
Using the following equations (6), (7), and (8), the four addition test rates αmax 302,
αmin 303,
α1 305,
α2 306
Each average test rate t (αmax) 311,
t (αmin) 308,
t (α1) 309,
t (α2) 310 is calculated.

In (6) and (7) above,
α: Addition test rate,
R _max : Maximum test rate,
R _min : initial test rate,
S: Number of LSIs in one lot σ: Standard deviation,
t: Average operating rate.

  F (r) in equations (6) and (7) is a cumulative distribution function of a normal distribution and is represented by the following equation (9).

である。 Where erf is the error function

It is.

In Expressions (6) and (7), the cumulative distribution function difference F (R _max ) −F (α × i + R _min ) is a probability P (α × i + R _min <X ≦ R _max ) (the random variable X is α × 1−F (α × i + R _min ) is a probability P (α × i + R _min <X ≦ ∞) (the probability variable X is α × i and + ∞), corresponding to the probability between i + R _min and R _max ). Corresponding probability). The variable (α × i + R _min ) of the cumulative distribution function corresponds to the addition operation of the addition test rate with respect to the initial test rate, and n of the index i (0 ≦ i ≦ n) is, for example, R _min + α × n < R _max is a positive integer having a value of R _min + α × (n + 1) ≧ R _max .

  In step 307, t (αmin) 308 is obtained from t and S in equation (8) from T and S where α in equations (6) and (7) is αmin. Similarly, from T and S where α in equations (6) and (7) is α1, α2, and αmax, t (α1) 309 and t (α2) 310 are obtained by t = S / T in equation (8). , T (αmax) 311 is obtained.

  Note that F (r) in the equations (6) and (7) is a cumulative distribution function of a normal distribution and is expressed by the following equation (9).

Step 312:
In step 307, the magnitude relationships of the respective values of t (αmin) 308, t (α1) 309, t (α2) 310, and t (αmax) 311 obtained are compared, and the values of αmax and αmin are updated.

  A specific method will be described with reference to FIG. In FIG. 6, the horizontal axis 601 represents the addition test rate α, and the vertical axis 602 represents the average test rate t.

In FIG. 6, the average test rate t is
t (αmax)> t (αmin)> t (α1)> t (α2)
The relationship between the added test rate α and the average test rate t is shown.

  When each point is approximated by a curve, the assumed curves are a curve 603 and a curve 604. In the case of the curve 603, the minimum value of the average test rate t is between α1 and α2, and the curve 604 In this case, it can be estimated that the minimum value of the average test rate t is between α2 and αmax.

  Therefore, in this case, the value of αmax is left as it is, and the value of αmin is updated to the value of α1. That is, in FIG. 6, since there is no minimum value between αmin and α1 in both curves 603 and 604, αmin is a new αmin, and αmin and αmax sections sandwiching the minimum value of average test rate t To narrow.

Step 313:
It is determined whether or not the difference between the values of αmax and αmin is smaller than a predetermined value (> 0). If the difference is smaller (| αmax−αmin | ≦ predetermined value), the process proceeds to step 314 and is larger ( | Αmax−αmin |> predetermined value), the process proceeds to step 307. In the case of FIG. 6, in step 307, α1 and α2 are obtained from the above equations (4) and (5) using αmax and the updated αmin.

  Note that the predetermined value in the determination in step 313 (| αmax−αmin | <predetermined value) indicates the addition test rate itself, and even if it is set to a smaller value, the effect of reducing the test rate cannot be expected. An arbitrary value. When this predetermined value is set small, the number of executions of the routines 307, 312 and 313 in FIG. 5 is increased, and an additional test rate with a higher test rate reduction effect can be calculated.

Step 314:
The average value ((αmin + αmax) / 2) of αmin and αmax (condition: | αmin−αmax | <satisfies a predetermined value) calculated in step 312 is calculated and set as the addition test rate 215.

  In this embodiment, before the function test is started, the initial test rate, the maximum test rate, and the addition test rate are calculated in advance in step 101, and the first LSI test is executed using the execution test rate 1 as the initial test rate (step 102B1), and the PASS / FAIL is determined. If it is PASS, it is determined as a non-defective product, and the process proceeds to the next LSI test.

  On the other hand, if it is FAIL, the same LSI test is executed with the execution test rate 2 as the maximum test rate (step 102B2), and PASS / FAIL is determined again.

  If the retest in step 102B2 is FAIL, it is determined as a defective product, and the process proceeds to the next LSI test. If it is PASS, the additional test rate is added to the initial test rate, and the next LSI test is executed. To do. This series of processes is repeated until the determination of non-defective / defective products is completed for all LSIs in the lot.

  Therefore, according to the present embodiment, even if an LSI that is originally a good product performs a function test at the initial test rate that is the optimum test rate in step 102B1, even if it is determined as FAIL, retesting at the maximum test rate in step 102B2 Therefore, the problem of lowering the yield does not occur.

  Further, according to the present embodiment, even if the test in step 102B1 is FAIL, if it is determined as good in step 102B2, the additional test rate is added to the execution test rate 1 in step 102B1 for the next LSI. Repeat to execute. For this reason, the test time for the entire lot can be shortened with respect to the lot that can find the most efficient optimum test rate for PASSing the LSI that is originally a good product in the test of the process 102B1. This effect will be described below with reference to FIG. FIG. 7 schematically shows an operation rate distribution of each LSI in a lot function test.

In FIG. 7, the horizontal axis 702 is the test rate, and the vertical axis 701 is the number of LSIs. Reference numeral 703 represents the distribution of the operation rate of each LSI in one lot. Further, 706 on the horizontal axis 702 indicates the maximum test rate 212 calculated by the procedure of FIG.
704 is the average operation rate 207 of the LSI,
705 is the maximum value of the operation rate of the LSI,
Reference numeral 707 denotes an operation rate of an arbitrary LSI.

  In general, an LSI is manufactured such that a value of an on-current ION of a transistor constituting the LSI is near the center of a manufacturing variation range. The distribution of LSI operation test rates is centered on an average value 704 (a test rate obtained from timing verification assuming the vicinity of the center of LSI manufacturing variation). For this reason, the number of LSIs distributed in the maximum test rate 706 is unlimited. Therefore, the largest operation test rate 705 in one lot exists between the average value 704 and the maximum test rate 706.

  When a function test is performed at an arbitrary test rate 707, if the LSI operation rate is shorter than the test rate 707, that is, if the LSI operation rate is on the left side of the position 707 in FIG. PASS to the function test at the test rate 707. When the LSI operation rate is on the right side of the position 707, the LSI fails the function test at the test rate 707.

  If the LSI operation rate is longer than the test rate 707, that is, if it is on the right side of the position 707 in FIG.

  Therefore, when an arbitrary test rate 707 is on the right side of the largest operation test rate 705 in one lot, the PASS is always performed.

  The execution test rate 1 executed in step 102B1 in FIG. 1 is at the initial test rate 704, for example, at the start of the lot test, and when the LSI tested at the execution test rate 1 is FAIL, the addition test rate 215 Will be added. Therefore, the operation test rate 705 + addition test rate 215, which is the largest in the lot, is never greater.

  Therefore, the test time in the process 109 of FIG. 1 can be shortened by the difference between the maximum test rate 706 and the operation value 705 of the LSI operating the slowest in one lot + the addition test rate 215. Therefore, the test time of the execution example 1 of the present invention can be shortened as compared with the conventional method.

  Further, a non-defective LSI is always tested at the execution test rate 2 even if it is FAILed at the execution test rate 1. The function test at the execution test rate 2 is always PASS, and a non-defective product is not erroneously determined as a defective product.

  It should be noted that the disclosures of the above patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Various combinations and selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

201 ION values 202 of a plurality of LSIs 202 Average operation rate of timing verification result under manufacturing variation central condition 203 Maximum operation rate of timing verification result under manufacturing variation worst condition 205 Operation rate 207 Average operation rate 208 Standard deviation 210 Initial test rate 212 Maximum test Rate 214 Number of LSIs in one lot 215 Addition test rate 302 αmax
303 αmin
305 α1
306 α2
308 t (αmin)
309 t (α1)
310 t (α2)
311 t (αmax)
400 LSI to be tested
401 LSI tester 402 Processing unit 403 Recording medium 404 Input / output unit 405 LSI tester test control unit 406 Network 407 Computer device 408 Processing unit 409 Recording medium 410 Input / output unit 411 LSI mounting device 601 Horizontal test axis 602 representing added test rate α Average test rate Vertical axis 603 representing t Curve 604 showing the relationship between the added test rate and the average test rate t Assumed curve 701 showing the relationship between the added test rate and the average test rate t A vertical axis 702 showing the LSI distribution Horizontal axis 703 indicating test rate Distribution of operation rate of LSI 704 Average value 705 in distribution of operation rate of LSI 705 Operation value of LSI of slowest operation in one lot 706 Maximum test rate 707 Arbitrary test rate 901 902 pieces Trait 903 normal operational minimum test rate of each LSI in the lot of the distribution 905,907,908 test rate (operation rate)
906 Test rate of normal test before shortening to optimal test rate

Claims (10)

In testing at least the first and second devices under test composed of semiconductor integrated circuits having the same configuration,
Based on the test result of the function test at the first test rate of the first device under test,
In the case of a failure, based on the test result of the function test of the first device under test at a predetermined second test rate having a value larger than the first test rate, in the case of a pass,
The first test rate is updated to a value increased by an addition test rate of a predetermined value, and the result of the function test at the first test rate passes through the first device under test. As in the case of the
When the test results of the function test at the first and second test rates of the first device under test are both failed, the first device under test is determined to be defective with respect to the function test;
Semiconductor integration for performing a function test of the second device under test using the first test rate or the first and second test rates in the same procedure as the first device under test. Circuit test method. When the device under test is an LSI and a function test is continuously performed on an LSI of a lot which is an LSI set,
The initial test rate of the function test of the first LSI of the lot is set as the first test rate, and the maximum test rate that is the upper limit test rate that guarantees the normal operation of all of the plurality of LSIs is set as the second test rate. A first step;
A second step of performing an LSI function test using the first test rate;
If the result of the function test in the second step is a failure, the function test is performed again on the LSI that has performed the function test in the second step using the second test rate. A third step to perform;
When the test result of the function test in the third step is a pass, a fourth step of setting a value obtained by adding the addition test rate to the first test rate as a first test rate of the next LSI When,
Have
If the test result of the function test in the second step is a pass, the LSI is regarded as a non-defective product, and the function test of the next LSI is performed.
If the test result of the function test in the second step is fail, the third step is executed. If the test result of the function test in the third step is fail, the LSI is regarded as defective. If the test result of the function test in the third step is a pass, the fourth step is executed and the LSI is replaced with a non-defective product. 2. The semiconductor integrated circuit according to claim 1, wherein a series of processes of shifting to the second process, which is a step of executing a function test of the next LSI, is repeated until the function tests of all the LSIs in the lot are completed. Testing method.   3. The semiconductor integrated circuit according to claim 2, wherein the initial test rate is an average value, a median value, or a value within a standard deviation value of a minimum rate distribution at which the LSI of the lot can operate normally. Testing method. The initial test rate is
An on-current value of a plurality of LSI transistors of the LSI;
The average operating rate value obtained by timing verification assuming an on-current value near the center of LSI manufacturing variation,
The value of the maximum operation rate obtained from the timing verification assuming the on-current value in the worst condition of LSI manufacturing variation,
Is read from the storage device to calculate the operation rate for each of the plurality of LSIs,
Calculating an average operation rate of the calculated operation rates;
3. The method of testing a semiconductor integrated circuit according to claim 2, wherein the calculated average operation rate is used as the initial test rate.   3. The test of a semiconductor integrated circuit according to claim 2, wherein the maximum test rate is a maximum value of a path delay between flip-flops output as a result of timing verification assuming the worst condition of LSI manufacturing variation in advance. Method. The addition test rate is
The initial test rate;
The maximum test rate;
The number of LSIs in one lot,
Distribution of LSI operation rate in the lot,
3. The test method for a semiconductor integrated circuit according to claim 2, wherein the calculation is performed based on: (A) obtaining a maximum value of the addition test rate from a difference between the initial test rate and the maximum test rate;
The minimum value of the addition test rate is obtained by dividing the difference between the initial test rate and the maximum test rate by the number of LSIs in one lot,
Calculating a first intermediate value and a second intermediate value for equally dividing the minimum value of the addition test rate and the interval of the minimum value into three;
(B) the standard deviation of the operation rate, the initial test rate, the maximum test rate, the maximum and minimum values of the addition test rate, the first and second intermediate values, and one lot of LSI And calculating the average test rate for each of the four addition test rates of the maximum value, the minimum value, and the first and second intermediate values,
(C) comparing the magnitude relation of each value of the average test rate of the four addition test rates, and updating the maximum value and / or the minimum value;
(D) It is determined whether or not the difference between the updated maximum value and the minimum value is smaller than a predetermined value. If the difference is larger, the process returns to (b). The semiconductor integrated circuit test method according to claim 6, wherein an average value of a maximum value and the minimum value is used as the addition test rate. A test system including a tester that performs at least a function test of a device under test at a set test rate,
In testing at least the first and second devices under test composed of semiconductor integrated circuits having the same configuration,
Based on the test result of the function test at the first test rate of the first device under test,
In the case of a failure, based on the test result of the function test of the first device under test at a predetermined second test rate having a value larger than the first test rate, in the case of a pass,
The first test rate is updated to a value increased by an addition test rate of a predetermined value, and the result of the function test at the first test rate passes through the first device under test. As in the case of the
When the test results of the function test at the first and second test rates of the first device under test are both failed, the first device under test is determined to be defective with respect to the function test;
The function test of the second device under test is performed in the same procedure as that of the first device under test using the first test rate or the first and second test rates. Test system to control.   When the device under test is an LSI and the function test is continuously performed on the LSIs of the lot that is an LSI set, the initial test rate of the function test of the first LSI of the lot is set as the first test rate. 9. The test according to claim 8, further comprising a computer device that is set in the tester and sets the maximum test rate, which is an upper limit test rate that guarantees normal operation of all of the plurality of LSIs, as the second test rate. system. A test program executed by a tester for testing a device under test,
In testing at least the first and second devices under test composed of semiconductor integrated circuits having the same configuration,
Based on the test result of the function test at the first test rate of the first device under test,
In the case of a failure, based on the test result of the function test of the first device under test at a predetermined second test rate having a value larger than the first test rate, in the case of a pass,
The first test rate is updated to a value increased by an addition test rate of a predetermined value, and the result of the function test at the first test rate passes through the first device under test. As in the case of the
When the test results of the function test at the first and second test rates of the first device under test are both failed, the first device under test is determined to be defective with respect to the function test;
The function test of the second device under test is performed in the same procedure as that of the first device under test using the first test rate or the first and second test rates. Test program to control.

Images