CN109145460A

CN109145460A - A kind of semiconductor reliability appraisal procedure and device

Info

Publication number: CN109145460A
Application number: CN201810985436.9A
Authority: CN
Inventors: 不公告发明人
Original assignee: Zhengyi Integrated Circuit (shanghai) Co Ltd
Current assignee: Hongqi Integrated Circuit Zhuhai Co ltd
Priority date: 2018-08-27
Filing date: 2018-08-27
Publication date: 2019-01-04
Anticipated expiration: 2038-08-27
Also published as: CN109145460B

Abstract

The present invention provides a kind of semiconductor fast reliability evaluation method and device, the testing scheme including efficient and reliable reliability benchmark (BL) management system and based on sequential probability than test (SPRT).For the credible setting for ensuring SPRT testing scheme, BL database is constantly updated using bayes method.This be SPRT for the first time be applied to tool there are two unknown parameter security risk assess.Using method and device provided by the invention, the reliability of semiconductor can be quickly measured, reduces sample size and testing time.

Description

Semiconductor reliability evaluation method and device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method and a device for evaluating reliability of a semiconductor.

Background

Semiconductor fabrication, one of the most complex process flows in modern industry, involves hundreds of complex process steps including photolithography, etching, thin film, diffusion, cleaning, etc. These processes can generally be divided into two parts: Front-End of Line (FEOL) and Back-End of Line (BEOL), FEOL processes are generally defined as starting from the wafer and ending when the metal Line connections begin. Transistors are fabricated in FEOL with considerable diffusion processes to form, for example, well junctions, field isolation and determine the Source/Drain (S/D) fields of the transistor. Gate oxide, one of the most critical features, is grown after S/D formation, followed by formation of polysilicon and Inter-Level Dielectrics (ILD). In BEOL, similarly, all lithographic processes are followed by etching, cleaning and Chemical Mechanical Polishing (CMP) processes. Semiconductor fabrication is completed after passivation deposition and pad opening. The wafer will then be subjected to a Wafer Acceptance Test (WAT) to confirm that the electrical performance meets the definitions in the specification. Subsequently, through an out-of-stock Quality Assurance (OQA) visual inspection, acceptable wafers can be shipped for subsequent processing, such as Chip Probing (CP), assembly, Final Test (FT), System assembly, and System Level Test (SLT).

Wafer level and package level reliability tests.

Reliability performance, one of the most fundamental goals from a system level perspective, is directly affected by semiconductor manufacturing process stability and robustness. As Integrated Circuits (ICs) become more widely used, reliability requirements have increased substantially from Parts Per Million (PPM) to Parts Per Billion (PPB) levels, particularly for health and safety (including automotive, aerospace) applications. To achieve such high reliability, considerable stress testing is required to early clear the defective parts. These stress tests include online screening of FEOL and BEOL phases, Wafer-Level Reliability Control (WLRC, sample test after WAT), stress test items in CP/FT, and routine Reliability monitoring. Basically, three reliability monitoring procedures can be divided: Wafer-Level Reliability (WLR), Package-Level Reliability (PLR), and Product-Level Reliability (PDR) tests. For the first two, such as in-line screening and WLRC, specially designed test structures were tested, while for PDR, the actual chip was tested. Traditionally, semiconductor practitioners refer to WLR and PLR tests as process reliability.

The main difference between WLR and PLR is the implementation tested; for WLR, an entire wafer is placed on a probe station for testing. For PLR, it is necessary to dice the wafers, pick up the test structures on dicing streets, mount them on a special carrier (commonly referred to as a "ceramic package"), and place the ceramic packaged samples in a special oven under high temperature and voltage stress. Typically, PLR testing times (hours to hundreds of hours) are much longer (seconds to hours) than WLR testing. To compensate for this, most PLR systems are designed on a Device Under Test (DUT) board to support multiple samples (e.g., six).

Fig. 1 shows an example of how WLR tests are performed on a wafer under test. Electrical signals and stress are applied to the test wafer through a probe card, which is primarily a Printed Circuit Board (PCB) with metal traces and probes. The probe directly contacts a pad of the test structure. In this example, the WLR test starts with the chip on top of the wafer and moves down, then starts from right to left or another way to guarantee the shortest path to save time. At the test end, test results can be seen, with the failed die (e.g., the two pink dies in fig. 1) typically being marked with different colors. As described above, throughput is critical, particularly when wafers are to wait for shipment, since WLR and WLRC tests are on wafers. This clearly requires a fast and efficient way to reduce test time.

And (II) testing the reliability of the conventional process.

The most common process reliability tests include Time Dependent Dielectric Breakdown (TDDB) and Electromigration (EM). TDDB is used to evaluate the reliability of thin films such as gate oxide, ILD and metal-insulator-metal (MIM) capacitors.

Probability maps are widely applied to reliability data based on linear transformation of a particular distribution in a simple visual presentation. Typical EM test results are shown in FIG. 2, which gives the standard deviation σ, median lifetime exp (μ), and R²(to reflect how well the fit is). EM test results are usually divided by lognormalAnd (4) modeling by using a cloth.

In fig. 2, it is clear that curve C is the best, as it possesses the longest median lifetime (exp (μ) ═ 53.4) and the smallest variance (σ ═ 0.32). Curve B shows a number of failure modes. For curve A, although the fit is good (R)²0.99), but its variance (σ 1.28) is too large to be acceptable; in practice, the σ for EM testing should be less than 1.2. Curve C is designated as Baseline (BL) representing a trustworthy reference; and the Lower Limit (LSL) and the Upper Limit (USL) are marked by vertical dashed lines in FIG. 2 according to their fitted distribution. It is confirmed from practical experience that LSL ═ max (exp (μ)_0.1％-4σ_0.1％),T_spec) And USL ═ exp (μ)_0.1％+4σ_0.1％) Wherein exp (μ)_0.1％) And σ_0.1％Respectively in the BL database_0.1％Mean and standard deviation of the lower (0.1% quantile failure time); t is_specIs corresponding to T having a lifetime of 10 years_0.1％This is mandatory lifetime. Using T_0.1％There are two reasons: first, it has become a standard requirement for most customers; secondly, from T_0.1％The influence of the slope is combined and thus depends only on the influence of the median lifetime.

In FIG. 2, LSL is set to 4.09 because it is greater than the corresponding T_spec(═ 3.46), it is the Z point marked with an "X". If T is_0.1％<LSL survey and improvement actions will be taken; these data are considered to be non-conforming (and therefore illegal) and are not updated to the reference database. In contrast, for T_0.1％>Those of USL, because it reveals a possible breakthrough for better reliability performance, once the improvements (through failure analysis and reliability physics) are confirmed and the feasibility determined, will incorporate these data into the BL and give a larger weighting factor, indicating that baseline performance will be improved to this new height. For T_0.1％Between LSL and USL, equal weights are used to enrich the BL database with these data.

A weibull distribution is commonly used to characterize TDDB failures. Some of the reasons for this are due to the advantages of the weibull distribution, whose shape parameter (γ in fig. 3) perfectly describes the failure behavior:

gamma <1: reduced failure rate (DFR)

Gamma 1: constant failure rate (CFR, exponential distribution)

Gamma >1 failure rate Increase (IFR).

Because of this, the shape parameters provide a reliable instant insight into the TDDB test used to evaluate material loss, which should be at IFR. That is, for the gate oxide TDDB, if the weibull slope is less than 1, it can be concluded that the test failed.

Unlike figure 2, the characteristic lifetime of the weibull plot is not exp (μ), but η. curve C in figure 3 is the one with the longest of the three η and the greatest slope γ. similar to curve B in figure 2, curve B in figure 3 shows a number of failure modes²Very large (═ 0.98), the material under test appears to have inherent defects similar to fig. 2, with two vertical lines representing LSL and usl, fig. 3, due to exp (ln (η)_0.1％)-4/γ_0.1％)<T_specSetting LSL ═ T_spec(＝1.19)。

For all test groups in fig. 2 and 3, there are at least 24 samples in each group, and all tests will continue until all samples fail. This takes a long time as shown in the two figures above. In modern reliability testing, most customer specifications for the test require complete failure unless on-board, such time consuming testing is unacceptable. For most reliability evaluations and evaluations, the decision needs to be made early and must be made before all samples fail.

From a system level, reliability performance, one of the most fundamental goals, is directly affected by the stability and robustness of the overall semiconductor manufacturing flow. As the application fields of integrated circuits continue to expand, reliability requirements are greatly increased, particularly for medical health, automotive electronics, aerospace, and other fields where safety is considered a primary concern. Worse still, conventional time-consuming reliability tests are becoming increasingly unacceptable due to intense product competition and drastically shortened update cycles. Thus, there is a strong need in the industry for a fast and efficient way to quickly assess the risk of reliability.

Disclosure of Invention

The invention solves the problem of providing a system scheme to integrate reliability benchmark management and a sequential probability ratio test method, which can quickly test the reliability of a semiconductor and reduce the sample size and the test time.

In order to solve the above problems, the present invention provides a method for evaluating the rapid reliability of a semiconductor, comprising the following steps:

s1, obtaining past monitoring data set, establishing a real-time updated reference BL database by means of Bayesian inference, and obtaining the original hypothesis H of sequential probability ratio test SPRT from the reference BL database₀；

S2, obtaining the test data of the current monitoring data sample, estimating the distribution parameter from the current test sample data, and using the distribution parameter as the alternative hypothesis H of the sequential probability ratio test SPRT₁；

S3, judging alternative hypothesis H₁Whether the medium shape parameter is within the acceptable range and the corresponding T_0.1％Whether the estimated value of (d) is better than the lower bound LSL;

s31, if the shape parameter is not in the acceptable range or the corresponding T_0.1％If the estimated value of the LSL is less than the lower limit LSL, terminating the test and searching the reason, and implementing an improvement action measure;

s32, if the shape parameter is in the acceptable range and the corresponding T is_0.1％If the estimated value is greater than or equal to the lower bound LSL, testing SPRT according to the sequential probability ratio, and calculating the log-likelihood of the current sample and the current reference BLThe ratio R;

s321, stopping sampling when R is less than or equal to B, and not rejecting the original hypothesis H₀；

S322, when B < R < A, the current result can not be judged, resampling is carried out, the test is continued, and the step S2 is carried out;

s323 refusing H when R is larger than or equal to A₀Terminating the test and searching the reason, and implementing an improved action measure;

wherein, the boundaries A and B are approximated by the formula:

where α represents a first category of errors, also referred to as risk to the producer, and β represents a second category of errors, also referred to as risk to the customer;

wherein the lower bound LSL is derived from the formula:

for a lognormal distribution: LSL ═ max (exp (μ)_0.1％-4σ_0.1％),T_spec)；

Wherein, T_specCorresponding to T having a lifetime of 10 years under normal operation_0.1％，σ_0.1％Corresponding to at T_0.1％The shape parameter of_0.1％Corresponding to at T_0.1％A scale parameter of;

for a weibull distribution:

wherein, T_specCorresponding to T having a lifetime of 10 years under normal operation_0.1％，γ_0.1％Corresponding to at T_0.1％Shape parameter of (2) η_0.1％Corresponding to at T_0.1％The following scale parameters.

Further, in the step S321, ifT corresponding to the current test_0.1％The estimated value of (1) is not more than the upper bound USL, the test results are integrated into the reference BL database, and the reference BL database is updated by Bayesian inference; if the current test corresponds to T_0.1％The estimated value of (2) is larger than the upper USL, the possible reason of the failure analysis FA is firstly confirmed, if the physical mechanism has feasibility, a larger weight factor is given and the probability is updated to the reference BL database.

Wherein the upper USL is derived from the formula:

for a lognormal distribution: USL ═ exp (μ)_0.1％+4σ_0.1％)；

for a weibull distribution:

Further, in step S1, the reference database contains reasonable prior information and is continuously updated by using bayesian inference, where the updating includes first constructing a prior distribution of unknown parameters to be explored by using initial test result information, where the prior distribution summarizes an initial evaluation of the possibility of the unknown parameters, and then optimizing the initial evaluation by using bayesian inference in combination with a current test result to obtain a first posterior distribution; and the former posterior distribution is used as the current prior distribution, the second group of data is used as the current data, the second posterior distribution is obtained by Bayesian inference, and the steps are repeated in this way and are iterated in sequence to obtain the latest posterior distribution of the current data.

Bayesian theorem describes:

here, the

p (θ | y) represents the posterior distribution.

p (y | θ) is the joint probability given the number data set y.

p (θ) is a prior distribution.

p (y) is the probability density, which can be ignored under the assumption of a ratio.

p (y | θ) can be obtained by a likelihood function of the data. The product of the probabilities at a given data set y, which depends on the model parameter θ, and can be expressed asWhere n is the total number of data.

Thus, bayesian law can be expressed as:

p(θ|y)∝L(y|θ)p(θ) (1)

this illustrates that the posterior distribution is proportional to the model parameters of L (y | θ) and the prior distribution, which covers the information of the past tests.

The log normal distribution is used here as an example, considering that bayesian inference for weibull and log normal distributions are quite similar. To facilitate analysis, the data is typically converted to a logarithmic scale to eliminate the failure life data skewness, i.e., y_i＝log(t_i) Here, the joint sampling density of the normally distributed random variable is

Examining equation (2) and fixing with respect to μ and y, it can be seen that the inverse gamma prior distribution form in equation (3) is σ²Is given.

Reconstructing the likelihood function in equation (2) for a given σ²The latter μ is:

is in the form of a normal distribution.

To complete the pairing of mu and sigma²Specification of a priori distribution, it is necessary to specify p (μ | σ)²) From equation (4), p (μ | σ)²) Can be written as mean δ and variance σ²Normal distribution of/κ. Thus, for a given σ²Is that the complete specification of the prior distribution of mu is

Where κ is controlled at a given σ²The level of diffusion of the prior distribution of the lower μ.

Combining equations (3) and (5) can derive μ and σ²Is proportional to

Finally, based on equation (1), the posterior distribution p (μ, σ) is combined²Y) is proportional to the product of equations (2) and (6)

Wherein

Further, defining parameter pairs θ ≡ (scale parameter, shape parameter), SPRT can be simply assumed as a hypothesis testing problem of double simple hypotheses in general₀:θ＝θ₀And H₁:θ＝θ₁Wherein theta₀≠θ₁。

Let α represent a risk for the first category of errors, also called producers, that is, if H₀Is true, the null hypothesis H is rejected₀β, and a second type of error, also referred to as a risk to the customer, is if H₀Not true but not reject H₀Unfortunately, this is a contradictory relationship, as reducing one is at the cost of increasing the other one, considering that both types of errors are equally important in practice, assuming that their probabilities are equal, i.e., α ═ β.

It is assumed that after the n-1 observation, the nth likelihood ratio can be interpreted as:

wherein, t_iRepresents the ith failure life, λ_BL，λ_SpecRepresenting the likelihood functions of the original hypothesis and the alternative hypothesis, respectively.

A sequential process divides the sample space into three regions; does not reject H₀Region, reject H₀Zone and continue test zone. The decision rule of SPRT is as follows:

wherein boundaries a and B are approximated by the following equations:

when 0< α ═ β <1/2, the error of equation (9) is negligible.

The Operating Characteristics (OC) function L (theta) is that H is not rejected when the real parameter is theta₀The OC function L (θ) based on α - β can be approximated as:

where h is the integral solution of equation (11):

from equation (11), it can be seen that h depends on the true parameter θ. However, for each θ, h cannot be explicitly calculated and numerical approximations must be employed. From equations (10) and (11), θ ═ θ₀,θ₁The value of L (θ) is:

an Approximation (ASN) E { N | θ } of the Average Sample Number (ASN) is derived by using the OC and the approximation equation, which requires that it be trueStop SPRT when the positive parameter is θ, haveWald shows that SPRT can provide the smallest ASN given the assumption and these approximations hold for small error probabilities (typically less than 0.05).

It is clear that ideally an OC function can be obtained that is as close to ideal as possible (which means a smaller sum) and a desired number of samples that is as small as possible, however, these two requirements are contradictory and compromise needs to be made, for example, as reliability requirements increase dramatically, failure rates in first year applications decrease from PPM levels to PPB levels, and thus first and second types of errors need to become much smaller, when the error probability (for both α and β) is less than 0.06, the required sample size can be significantly reduced, the intensity of α - β -0.02 can be 10 by a fixed sample size⁷Orders of magnitude testing and can be reduced by 10 using SPRT⁶Based on these past work, and confirmed by practice in the field, it is suggested that the choices at α and β for different failure rates levels are as follows:

>100PPM α＝β＝0.05

10PPM～100PPB α＝β＝0.01

<10PPB α＝β＝0.005。

further, when the failure distribution is a lognormal distribution, the probability density function of the lognormal distribution is defined as:

where exp (μ) is the median lifetime and σ is the log standard deviation.

The sample estimates of μ and σ in equation (12) are typically derived from a probability map, which in routine engineering analysis is typically time as the x-axis cumulative percent failure as the y-axis, which is also referred to as an approximate median rank estimate.

After plotting these points, a conventional parameter estimation method can be used to find the characteristic parameters based on the following linearized equation (13):

t_F％＝exp(Z_F·σ+μ) (13)

wherein Z_FRepresenting the multiple of the logarithmic standard deviation at cumulative fraction F%. according to JEDEC JP001[15 ]],t_0.1％At maximum operating temperature and maximum current density is defined as the characteristic life of the product, based on equation (13), t_0.1％＝exp(-3.09·σ+μ)。

In order to quickly get from BL (mu)₁,σ₁) And Spec (. mu.g)₂,σ₂) These two likelihood functions are:

based on equations (7) and (8), the likelihood ratio R and the decision equation of the log-normal distribution can be obtained.

Further, when the failure distribution is a Weibull distribution, the probability density function of the Weibull distribution is defined as

Where η is the characteristic lifetime, also referred to as the scale parameter, and γ is the shape parameter.

While the cumulative density function of the weibull distribution can be expressed as:

rearranging equation (14) and taking the appropriate logarithm, we can get a linear equation, ln [ -ln (1-F)]＝γ[ln(t/η)]. Likewise, by replacing CDF with the median rank equation (12), t_0.1％Can be derived as

t_0.1％＝η·exp((-6.91)/γ)。

Suppose it is desired to make a quick decision on a batch to confirm its performance and BL (with a parameter of γ)₁And η₁Weibull distribution of) and alternative assumptions (parameter γ)₂And η₂Weibull distribution) the two likelihood functions are:

from equations (7) and (8), the likelihood ratio R and the decision equation of the weibull distribution can be determined.

Further, the semiconductor rapid reliability evaluation method can be applied to batch test BT, wafer level test WLR, package level test PLR, product level test PDR, system level test SLT, chip detection CP, or final test FT.

The present invention also provides a semiconductor rapid reliability evaluation apparatus, comprising:

a reference base establishing unit for executing the step S1, obtaining past monitoring data set, establishing a reference BL database updated in real time by means of Bayesian inference, and obtaining a sequential probability ratio test S from the reference BL databasePrimary hypothesis H of PRT₀；

A test sample sampling unit, configured to execute step S2, obtain test data of a current monitoring data sample, estimate a distribution parameter of the current monitoring data sample from the current test sample, and use the distribution parameter as a candidate hypothesis H for testing the SPRT according to the sequential probability ratio₁；

A test unit for executing step S3 to determine alternative hypothesis H₁Whether the medium shape parameter is within the acceptable range and the corresponding T_0.1％Whether the estimated value of (d) is better than the lower bound LSL; if the shape parameter is not within the acceptable range or corresponding T_0.1％If the estimated value of the LSL is less than the lower limit LSL, terminating the test and searching the reason, and implementing an improvement action measure; if the shape parameter is in the acceptable range and the corresponding T_0.1％If the estimated value of the current sample is greater than or equal to the lower bound LSL, testing the SPRT according to the sequential probability ratio, and calculating the log-likelihood ratio R of the current sample and the current reference BL; stopping sampling when R is less than or equal to B, and not rejecting original hypothesis H₀(ii) a When R is greater than or equal to A, H is rejected₀Terminating the test and searching the reason, and implementing an improved action measure; when R is larger than B and smaller than A, the current result cannot be judged, re-sampling is carried out, the test is continued, and the step S2 is carried out;

wherein, the boundaries A and B are approximated by the formula:

wherein the lower bound LSL is derived from the formula:

for a lognormal distribution: LSL ═ max (exp (μ)_0.1％-4σ_0.1％),T_spec)，

Wherein, T_specCorresponding to a 10 year life under normal operationT_0.1％，σ_0.1％Corresponding to at T_0.1％The shape parameter of_0.1％Corresponding to at T_0.1％A scale parameter of;

for a weibull distribution:

Further, when R is less than or equal to B, if T corresponding to the current test is detected_0.1％The estimated value of (1) is not more than the upper bound USL, the test results are integrated into the reference BL database, and the reference BL database is updated by Bayesian inference; if the current test corresponds to T_0.1％The estimated value of (2) is larger than the upper USL, the possible reason of the failure analysis FA is firstly confirmed, if the physical mechanism has feasibility, a larger weight factor is given and the probability is updated to the reference BL database.

Wherein the upper USL is derived from the formula:

for a lognormal distribution: USL ═ exp (μ)_0.1％+4σ_0.1％)；

for a weibull distribution:

Further, the reference BL database contains reasonable prior information and is continuously updated by using bayesian inference, the updating includes firstly constructing a prior distribution to be explored for unknown parameters thereof by using initial test result information, the prior distribution summarizes initial evaluation of possibility of the unknown parameters, and then optimizing the initial evaluation by combining a current test result through bayesian inference to obtain a first posterior distribution; and the former posterior distribution is used as the current prior distribution, the second group of data is used as the current data, the second posterior distribution is obtained by Bayesian inference, and the steps are repeated in this way and are iterated in sequence to obtain the latest posterior distribution of the current data.

A sequential process divides the sample space into three regions; does not reject H₀Region, reject H₀SPRT has the following decision rules:

wherein boundaries a and B are approximated by the following equations:

when 0< α ═ β <1/2, the error of equation (17) is negligible.

where h is the integral solution of equation (19):

from equation (19), it can be seen that h depends on the true parameter θ. However, for each θ, h cannot be explicitly calculated and numerical approximations must be employed. From equations (18) and (19), θ ═ θ₀,θ₁The value of L (θ) is:

an Approximation (ASN) E { N | θ } of the Average Sample Number (ASN) is derived by using the OC and the approximation equation, which requires stopping the SPRT when the true parameter is θ, someWald shows that SPRT can provide the smallest ASN given the assumption and these approximations hold for small error probabilities (typically less than 0.05).

It is clear that ideally one could obtain a OC function that is as close to ideal as possible (which means a small sum) and a desired number of samples that is as small as possible, however, these two requirements are conflicting and compromise needs to be made, e.g. as reliability requirements increase dramatically, failure rates in first year applications decrease from PPM level to PPB level, and thus first and second type errors need to become much smaller, SPRT can significantly reduce the required sample size when the error probability (for a sum) is less than 0.06. the intensity of α - β -0.02 can be 10 by a fixed sample size⁷Orders of magnitude testing and can be reduced by 10 using SPRT⁶Based on these past work, and confirmed by practice in the field, it is suggested that the choices at α and β for different failure rates levels are as follows:

>100PPM α＝β＝0.05

10PPM～100PPB α＝β＝0.01

<10PPB α＝β＝0.005。

where exp (μ) is the median lifetime and σ is the log standard deviation.

The sample estimates of μ and σ in equation (20) are typically derived from a probability map, which in routine engineering analysis is typically time as the x-axis cumulative percent failure as the y-axis, which is also referred to as an approximate median rank estimate.

After plotting these points, a conventional parameter estimation method can be used to find the characteristic parameters based on the following linearized equation (21):

t_F％＝exp(Z_F·σ+μ) (21)

wherein Z_FRepresents the multiple of the log standard deviation at cumulative fraction F%. t_0.1％At maximum operating temperature and maximum current density is defined as the characteristic life of the product based on equation (21), t_0.1％＝exp(-3.09·σ+p)。

based on equations (15) and (16), the likelihood ratio R and the decision equation of the log-normal distribution can be obtained.

While the cumulative density function of the Weibull distribution can be expressed as

Rearranging the formula (22) and taking the appropriate logarithm, a linear equation can be obtained, ln [ -ln (1-F)]＝γ[ln(t/η)]. Likewise, t is obtained by replacing the Cumulative Distribution Function (CDF) with the median rank equation (20)_0.1％Can be derived as t_0.1％＝η·exp((-6.91)/γ)。

Suppose it is desired to make a quick decision on a batch to confirm its performance and BL (with a parameter of γ)₁And η₁Weibull distribution of) and alternative assumptions (parameter γ)₂And η₂Weibull distribution of (v). The two likelihood functions are:

from equations (15) and (16), the likelihood ratio R and the decision equation of the weibull distribution can be determined.

Compared with the prior art, the invention has the following advantages:

the present invention proposes a comprehensive method comprising an efficient and reliable reliability Benchmark (BL) management system and a Sequential Probability Ratio Test (SPRT) based test scheme. In order to ensure the credible setting of the SPRT test scheme, the BL database is continuously updated by applying a Bayesian method.

This is the first application of SPRT to reliability risk assessment with two unknown parameters. The invention can rapidly measure the reliability of the semiconductor and reduce the sample size and the test time.

From these practical situations, the method provided by the invention has wide applicability, and can be applied to wafer level reliability test WLR, package level reliability test PLR, product level test PDR and the like, batch test BT, system level test SLT, chip probing CP, or final test FT.

Drawings

FIG. 1 is a schematic diagram of a WLR test sequence;

FIG. 2 is a graph of log-normal distribution probability for an actual EM test;

FIG. 3 is a Weibull distribution probability chart of an actual TDDB test

FIG. 4 shows the accurate reliability prediction using prior information in Bayesian method provided by the present invention

FIG. 5 is a flowchart of a method for evaluating the fast reliability of a semiconductor according to the present invention

FIG. 6(a) is a multiple-iteration posterior distribution of parameter μ, and FIG. 6(b) is a multiple-iteration posterior distribution of parameter σ;

FIG. 7(a) is a graph of probability of failure for a lognormal distribution, and FIG. 7(b) is a graph of SPRT for a lognormal distribution;

FIG. 8(a) is a graph of the probability of failure for a lognormal distribution, and FIG. 8(b) is a graph of the SPRT for a lognormal distribution;

FIG. 9 is a graph of log normal distribution probability of failure for 100% samples;

FIG. 10(a) is a graph of log Weibull distribution failure probability, and FIG. 10(b) is a graph of SPRT for Weibull distribution;

FIG. 11 is a graph of the probability of Weibull distribution of failure for a 100% sample;

FIG. 12 is a graph of SPRT used for batch-compliant lognormal distribution reliability tests;

fig. 13 shows SPRT for CP testing using α - β -0.01;

fig. 14 is SPRT for CP testing using α ═ 0.01 and β ═ 0.001;

FIG. 15 is a wafer diagram illustrating various defect modes;

FIG. 16 is a test sequence for a wafer sample with edge defects.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments.

In practice, almost identical devices will not fail simultaneously in most cases when they are subjected to the same stress conditions, even if at all, due to differences in material microstructure and manufacturing process. Therefore, in the semiconductor reliability evaluation of the present invention, not only the Time To Failure (TTF) but also the distribution of the Time To Failure is of interest. This reflects the main difference between the present invention and the approach proposed in the previous reliability demonstration experiments. Traditionally, two probability density functions are widely applied to failures in the semiconductor industry: lognormal (lognormal) and Weibull (Weibull) distributions. Weibull distributions are commonly used to model phenomena that exhibit extreme behavior that encompasses many competing mechanisms in parallel, any failure of which may lead to a failure of the entire system or product. One basis for using lognormal distributions is the scale-up or multiplication model. In this case, the failure model is a gradual change, with the change or degradation beginning so slowly that over time the change grows or doubles.

Referring to fig. 4, the present invention provides an accurate reliability prediction method using the prior information in the bayesian method. The reference database comprises reasonable prior information and is continuously updated by Bayesian inference, wherein the updating comprises the steps of firstly constructing a prior distribution needing to be researched for unknown parameters by utilizing initial test result information, summarizing initial evaluation on the possibility of the unknown parameters by the prior distribution, and then optimizing the initial evaluation by combining the current test result through Bayesian inference to obtain a first posterior distribution; and the former posterior distribution is used as the current prior distribution, the second group of data is used as the current data, the second posterior distribution is obtained by Bayesian inference, and the steps are repeated in this way and are iterated in sequence to obtain the latest posterior distribution of the current data.

Referring to fig. 5, a flowchart of a method for evaluating the fast reliability of a semiconductor according to the present invention is shown in fig. 5. S1, obtaining past monitoring data set, establishing a real-time updated reference BL database by means of Bayesian inference, and obtaining the original hypothesis H of sequential probability ratio test SPRT from the reference BL database₀(ii) a S2, obtaining the test data of the current monitoring data sample, estimating the distribution parameter from the current test sample data, and using the distribution parameter as the alternative hypothesis H of the sequential probability ratio test SPRT₁(ii) a S3, judging alternative hypothesis H₁Whether the medium shape parameter is within the acceptable range and the corresponding T_0.1％Whether the estimated value of (d) is better than the lower bound LSL; s31, if the shape parameter is not in the acceptable range or the corresponding T_0.1％If the estimated value of the LSL is less than the lower limit LSL, terminating the test and searching the reason, and implementing an improvement action measure; s32, if the shape parameter is in the acceptable range and the corresponding T is_0.1％If the estimated value is greater than or equal to the lower bound LSL, the SPRT is tested according to the sequential probability ratio, and the current sample are calculatedThe log-likelihood ratio R of the current reference BL; s321, stopping sampling when R is less than or equal to B, and not rejecting the original hypothesis H₀(ii) a S322 is treated as B<R<When A is needed, the current result cannot be judged, re-sampling is carried out, the test is continued, and the step S2 is carried out; s323 refusing H when R is larger than or equal to A₀Terminating the test and searching the reason, and implementing an improved action measure; wherein, the boundaries A and B are approximated by the formula:

wherein the lower bound LSL is derived from the formula:

for a lognormal distribution: LSL ═ max (exp (μ)_0.1％4σ_0.1％)，T_spec)

for a weibull distribution:

And (I) establishing a benchmark by adopting Bayesian inference.

First, a set of EM monitoring data (Table I) was collected from 4 quarterly monitoring of the same product under the same stress conditions.

First, based on the BL database, μ ═ 3.8 and σ ═ 0.15 are used as a priori information. The first quarterly TTF is then used as the current data to calculate a first a posteriori distribution, such as the lightest gray curve in fig. 6.

The first posterior distribution then becomes the prior distribution to obtain an updated posterior distribution using the second quarterly TTF as the current data. The latest a posteriori distributions can be obtained by successive iterations. Table II summarizes the corresponding results for (μ, σ) of the posterior distribution for each iteration. These all "legal" priors are used to form new BL's by bayesian method. The validity of the data is defined as the absence of early failure and the effect of no rejects.

TABLE I

TTF value per quarter

And (I) carrying out sequential reliability test.

1) Log normal distribution electromigration test.

Based on these updated BL parameters, a null hypothesis parameter H is assumed₀Is theta₀(4.026,0.22), which is from the values marked by the boxes in table II. Alternative hypothesis parameter θ₁Is a pair of parameters that determine the lowest acceptable T_0.1％(corresponding to the 10 year life specification). Wherein the shape parameters are estimated sequentially from the current sequential samples. Furthermore, in order to obtain a relatively accurate estimate, the slope is estimated starting from the 3 rd sample, as shown in fig. 7. Even a small change in the shape parameters (standard deviation σ for a lognormal distribution) will have a substantial effect on the hypothesis test, but not on the scale parameters. This is why in fig. 5a "pre-check" of the slope, i.e. another representation of the shape parameter, is performed to limit possible fluctuations of the SPRT.

TABLE II

Posterior distribution parameters mu and sigma

Thus, after pre-inspection (one star-level decision point in FIG. 5), the slope estimated from the data is used as "Virtual BL" in FIG. 7(a) and its T is always guaranteed_0.1％Equal to "Real BL" and for T_0.1％By doing so, the two-parameter, single-parameter SPRT problem is successfully simplified. The "SPEC" line in FIG. 7(a) represents a 10 year life boundary. Thus, if the "test" line is to the left of the "SPEC" line, the lifetime of the current data set is less than 10 years. For the case in fig. 7, set LSL ═ T_specThis may mean that the reliability is poorly performing.

It was determined by sequential analysis whether the batch compares favorably to a given BL at a given α -0.05 and β -0.05. to obtain a relatively accurate shape parameter estimate, sequential analysis was performed starting with the third sample.

As in table III, equation (7) yields a log-likelihood ratio R of 1.124, based on the SPRT decision rule in equation (8), the test needs to be continued. After testing a new sample, the parameters are recalculated, the log-likelihood ratio is updated, and a decision is made based on comparison with boundaries A and B. by this analogy, H is not rejected until test 8, as shown in FIG. 7(B)₀。

TABLE III

SPRT test results

It was observed that after only 8 trials, the SPRT thus saves a lot of time, when the batches were much better than BL or much worse than SPEC, the number of trials decreased much more significantly and rapidly, based on FIG. 8(a), a further conclusion can be drawn that the batches were worse than BL.

To verify the conclusions drawn by SPRT, testing was continued deliberately until all samples failed. The results are shown in FIG. 9, which concluded to match SPRT, showing that the sample lifetime is slightly worse than 10 year SPEC. This demonstrates the highest value of SPRT, especially the superior contribution in saving time and cost.

2) TDDB test.

TABLE IV

SPRT test results

Similar to the previous case, when α - β -0.05, the parameter H is assumed to be zero₀Is theta₀(100,2.5) as BL and T_0.1％As SPEC, scale and shape parameters were estimated sequentially in sequential tests, making decisions based on log-likelihood ratios (as in table IV).

As shown in FIG. 10, comparable performance was obtained in only 14 trials, where LSL was found>T_specAgain, the SPRT concluded was verified by continuing the test until all samples failed. As shown in fig. 11, the reliability performance of these samples was comparable to BL, and the applicability of SPRT was again confirmed.

3) SPRT was used for batch testing.

The most common example is the via EM test, which can withstand relatively high current densities, which requires high ambient temperatures (e.g., 350℃.) and very low current densities. Due to these special challenges, the PLR EM test must be used to evaluate via reliability.

PLR EM test boards are made of ceramic and can withstand temperatures of 350 ℃ or higher, with only 6DUTs per board. For via EM evaluation, at least 24 samples were required according to JEDEC JP001 requirements. Due in part to the limited number of test boards (only one board) and the intent to test the applicability of SPRTs, the through-hole EM test was performed using only a single test board with 6 samples at a time. In the first test run, fig. 12(a) and table V show 6 failure life data and analysis, which were temporarily inconclusive. Thus, the second test run was started with data in the lower portion of Table V. From fig. 12(b), it can be seen that, using the first 4 test data of the first and second lots, it can be concluded that the via performance is significantly different from BL., which indicates that the proposed SPRT of the present invention can also be applied to batch testing, although there may be some "waste", such as the two longest failure lifetimes in the second lot in table V are not used.

TABLEV

SPRT batch test results

4) SPRT is used for CP testing.

This explains why CP is skipped for some products, e.g., very high yield (e.g. > 99%) meets the following condition:

C_T×ASN+C_AN_A+C_FN_F＜C_P(23)

wherein

C_TSPRT unit test cost

C_AUnit cell packaging and processing costs

C_FUnit cell FT test and processing costs

C_PAverage CP per wafer test cost

N_ANumber of escaped defects detected during packaging

N_FNumber of escaped defects monitored during FT

If the FT test coverage is not high enough, equation (23) needs to include subsequent administrative costs.

However, even if CP is skipped, it is still necessary from time to check process stability on a sample basis and to confirm whether the criteria for skipping remain adequate. For such a confirmation, SPRT will be a perfect candidate-like confirmation.

The present invention provides an application of SPRT for CP testing, the data of which can be subject to normal distributions with mean of 99.5% and standard deviation of 0.2%. due to high CP yield and to follow the guidance in section IIB, set α β to 0.01, the results are shown in fig. 13, which indicates comparable BL CP performance, if α to 0.01 and β to 0.001 can be used to better protect the customer, fig. 14 can be obtained, which postpones the decision, extending from the thirtieth point to the fortieth point.

Here again, the importance of a trusted BL database that must join together legal data in an organized manner and need to be linked to an online management system to trigger early alarms when not met is emphasized.

5) SPRT is a dramatic cost savings.

Experience has shown that WLR test time is reduced by 60% under a variety of technical intersections of mass production. Using the most conservative rate of $20 per hour, 98% WLR tool utilization, and 20 test tool sets, saves over 200 ten thousand dollars per year, not to mention the benefits gained from earlier decisions, fewer probe card repairs, and better customer satisfaction with timely response. Furthermore, the proposed method proves to be of more important value in the following cases: new technologies and platform development, requiring faster data feedback; short-loop vehicles (short-loop vehicles) and on-line validation testing, mainly related to production run rates and lot/tool clearance; and time consuming tests such as TDDB evaluation of some high voltage devices.

6) Definition of LSL and USL.

In FIGS. 2,3,7(a),8(a),9,10(a) and 11, the marked LSL and USL vertical lines are based on T_0.1. Using the log-normal distribution as an example, exp (μ)_0.1％±4σ_0.1％) From practical implementation, (+/-4 σ) is used_0.1％) Especially for mass production, the opportunity to re-target a larger reliability performance is manageable, while this +/-4 sigma_0.1％The range may cover almost all data, and these performances are verified to be comparable to the benchmark.

Narrower ranges (e.g. +/-3) may be considered prior to large-scale production_0.1％) To ensure that the opportunity to make the BL database more robust is not missed.

7) Further reducing the risk of SPRT.

In addition to scientific BL management, the risk of "escape" can be further reduced by determining sufficient contact rules for the probe card by considering defect patterns As shown in FIG. 15, contact rules can be defined based on known patterns to cover most suspicious cases: wafer center (fig. 15a), top right moon (fig. 15b), wafer edge (fig. 15c), and ribbon cluster (fig. 15 d). In fig. 16, the present invention provides a test sequence for a wafer with edge defects, although defects affect only the die on the outermost ring to avoid the extreme case of testing the outer ring for two cycles with a slightly inner ring as a guard band. This arrangement not only ensures the trustworthiness of the method provided by the invention, but also ensures a shorter test time.

8) Broad application scenarios for SPRT.

The proposed SPRT can also be applied to Early Failure Rate (EFR) evaluation, with sample sizes that are typically large (> 600 samples). The EFR samples can be processed in a similar procedure by monitoring parameters (e.g., Vccmin, refresh time, access time, number of fail bits) to better describe the degradation behavior. The key point is to analyze continuous data, rather than discrete (e.g., pass/fail).

In fact, the following two trends make the method provided by the present invention suitable for cycle testing of popular HTOL (high temperature operating life) and NVM (non-volatile memory) products.

The sample density of the aged board (BIB) becomes small. Unlike >200 density memory BIBs, the density of the BIBs for most logic products is much lower, because of the high pin count and complex functionality, each BIB can be as small as only 6; this results in less "waste" of batch testing using the method provided by the present invention.

The memory capacity becomes very large; 256Gb flash memory chips have become a mainstream product. To complete the cycle evaluation of such flash memories, several months are required. The SPRT method provided by the invention can be completed in a shorter time.

9) Better results are optimally utilized to continuously improve the process.

For situations like fig. 7(a) and 8(a), appropriate action may need to be taken to check whether there is process drift, test noise, process oversight or any problem that leads to worse results, especially when the results are significantly below BL. to the contrary, which may be a very promising signal for situations like fig. 10(a), showing that there is room to further improve reliability robustness by studying the details of the sample being tested.

It will be apparent to those skilled in the art that various modifications can be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, it is intended that the present invention also include such modifications and variations.

Claims

1. A semiconductor rapid reliability evaluation method is characterized by comprising the following steps:

s32, if the shape parameter is in the acceptable range and the corresponding T is_0.1％If the estimated value of the current sample is greater than or equal to the lower bound LSL, testing the SPRT according to the sequential probability ratio, and calculating the log-likelihood ratio R of the current sample and the current reference BL;

wherein, the boundaries A and B are approximated by the formula:

where α represents a first category of errors, also referred to as producer risk, and β represents a second category of errors, also referred to as customer risk, where the lower bound LSL is given by the formula:

for a weibull distribution:

wherein,T_speccorresponding to T having a lifetime of 10 years under normal operation_0.1％，γ_0.1％Corresponding to at T_0.1％Shape parameter of (2) η_0.1％Corresponding to at T_0.1％The following scale parameters.

2. The semiconductor reliability evaluation method according to claim 1, wherein in step S321, if the current test corresponds to T_0.1％The estimated value of (1) is not more than the upper bound USL, the test results are integrated into the reference BL database, and the reference BL database is updated by Bayesian inference; if the current test corresponds to T_0.1％The estimated value of (2) is larger than the upper USL, the possible reason of the failure analysis FA is firstly confirmed, if the physical mechanism has feasibility, a larger weight factor is given and the probability is updated to the reference BL database.

Wherein the upper USL is derived from the formula:

for a lognormal distribution: USL ═ exp (μ)_0.1％+4σ_0.1％)，

Wherein, T_specCorresponding to T having a lifetime of 10 years under normal operation_0.1％，σ_0.1％Corresponding to at T_0.1％The shape parameter of_0.1％Corresponding to at T_0.1％The following scale parameters.

For a weibull distribution:

3. The method for evaluating semiconductor reliability according to claim 1, wherein in step S1, the reference database contains reasonable prior information and is continuously updated by using bayesian inference, the updating comprises first constructing a prior distribution of unknown parameters to be explored by using initial test result information, the prior distribution summarizes the initial evaluation of the possibility of the unknown parameters, and then optimizing the initial evaluation by combining the current test result through bayesian inference to obtain a first posterior distribution; and the former posterior distribution is used as the current prior distribution, the second group of data is used as the current data, the second posterior distribution is obtained by Bayesian inference, and the steps are repeated in this way and are iterated in sequence to obtain the latest posterior distribution of the current data.

4. The semiconductor reliability evaluation method of claim 1, wherein α - β.

5. The semiconductor reliability evaluation method of claim 4, wherein the selection of α and β for different failure rate levels is as follows:

failure rate >100PPM α - β -0.05

10PPM & lt & gt failure rate & lt & gt 100PPB α & lt & gt β & lt & gt 0.01 & gt

Failure rate <10PPB α ═ β ═ 0.005.

6. The semiconductor reliability evaluation method according to claim 1, wherein in step S32, it is assumed that the likelihood ratio of the nth time after the n-1 st observation value is obtained

Wherein the definition parameters are theta, H₀:θ＝θ₀，H₁:θ＝θ₁,θ₀≠θ₁，

t_iRepresents the ith failure life, λ_BL，λ_SpecRepresenting the likelihood functions of the original hypothesis and the alternative hypothesis, respectively.

7. The semiconductor reliability evaluation method according to claim 6, wherein the parameter θ may be a pair of parameters θ ≡ (dimension parameter, shape parameter).

8. The semiconductor reliability evaluation method according to claim 7, wherein when the failure distribution is a lognormal distribution, the original hypothesis H is₀And alternative hypothesis H₁The likelihood functions of (a) are:

wherein, theta₀≡(μ₁,σ₁)，θ₁≡(μ₂,σ₂)，exp(μ₁) Representing the median lifetime of the reference data, i.e. the scale parameter, σ₁Representing the logarithmic standard deviation of the reference data, i.e. the shape parameter, exp (mu)₂) Representing the median lifetime of the currently monitored data, i.e. the scale parameter, σ₂Representing the log standard deviation, i.e., shape parameter, of the current monitored data. t is t_iRepresents the ith failure life, f (t)_i) Representing the probability density function and n representing the total number of samples tested.

9. The semiconductor reliability evaluation method according to claim 7, wherein when the failure distribution is a weibull distribution, the original hypothesis H is₀And alternative hypothesis H₁The likelihood functions of (a) are:

wherein, theta₀≡(η₁，γ₁)，θ₁≡(η₂，γ₂)，η₁Characteristic lifetime, i.e. scale parameter, gamma, representing reference data₁Shape parameters representing reference data, η₂Characteristic lifetime, i.e. scale parameter, gamma, representing the current monitored data₂Shape parameter, t, representing current monitored data_iRepresents the ith failure life, f (t)_i) Representing the probability density function and n representing the total number of samples tested.

10. The semiconductor reliability evaluation method of claims 1-9, wherein the method is applicable to batch test BT, wafer level test WLR, package level test PLR, product level test PDR, system level test SLT, chip probing CP, or final test FT.