CN114064134B - Self-booting method and system suitable for embedded SPARC architecture processor - Google Patents
Self-booting method and system suitable for embedded SPARC architecture processor Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4403—Processor initialisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention provides a self-booting method and a self-booting system suitable for an embedded SPARC architecture processor, wherein the self-booting method and the self-booting system comprise the following steps: step S1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script; step S2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate, the main core and the other cores jump into addresses corresponding to the SRAM, an operating system program is operated, and the booting process is completed.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a self-booting method and a self-booting system suitable for an embedded SPARC architecture processor.
Background
SPARC is one of the RISC microprocessor architectures that is commonly used in on-board computer systems. The stability and reliability of the processor performance in the spaceborne computer system plays an important role in the stability and reliability of the whole system, and the complex space environment determines the limitation of the spaceborne resources. Different from the hot architectures such as ARM, MIPS, X and the like in the embedded field, the SPARC does not form a mature and reliable bootstrap program, on one hand, due to the fact that resources of a common satellite carrier are limited, excessive peripheral devices are not needed, and a complex bootstrap program is not needed, on the other hand, the SPARC is commonly used on an aerospace carrier, the application range is limited, and the software ecologically is inferior to a CPU of a mainstream architecture. The current boot mode of the SPARC processor is original, each CPU core is started by using a starting file, the address space and the resources of the CPU are initialized, a universal boot program is not formed, and extra workload is brought to application development engineers. In order to obtain optimal performance in a resource constrained situation, the program of the operating system needs to execute in memory, so the boot program is still required to initialize the hardware device and create a map of the memory space in order to prepare the correct software and hardware environment for the operating system kernel. For this reason, a simple, convenient, low-cost fast boot program needs to be designed for the SPARC processor in the on-board computer system, so as to facilitate maintenance and development.
Patent document CN102707952a (application number: CN 201210151037.5) discloses a parallel programming method based on user description on an embedded heterogeneous multi-core processor. The method comprises the following steps: the user carries out the description of heterogeneous multi-core processor platform and task through the graphic interface configuration wizard, the parallel mode setting, the creation and registration of primitive task, the generation of task relation graph (DAG) and the static allocation of primitive task in heterogeneous multi-core processor, and the realization of expressing the characteristics of processor platform, the parallel requirement and task assignment in the form of configuration file (XML). And embedding the primitive tasks after the configuration file is analyzed in parallel into the task labels of the heterogeneous multi-core frame codes, constructing corresponding serial source programs, and finally generating executable codes on the heterogeneous multi-core processors by calling a serial compiling tool.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a self-booting method and a self-booting system suitable for an embedded SPARC architecture processor.
The self-booting method suitable for the embedded SPARC architecture processor provided by the invention comprises the following steps:
step S1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
step S2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate, the main core and the other cores jump into addresses corresponding to the SRAM, an operating system program is operated, and the booting process is completed.
Preferably, the compiling execution address of the boot loader is the starting address of the Nor flash; the execution address of the operating system program is the address of the SRAM.
Preferably, the image parameters are automatically generated according to the information of the operating system program in the compiling process and are stored in fixed offset addresses of the image through a link script.
Preferably, the boot loader is relatively independent of the operating system program, compiled to embed in the front of the image with a pre-set segment.
Preferably, the initializing the memory and the memory controller employs:
step S2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
step S2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
step S2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
step S2.6: and setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment.
Preferably, the writing of the operating system program from the Nor flash into the address corresponding to the SRAM adopts:
step S2.7: the SPARC processor main core reads the mirror image parameters from the appointed address of the system mirror image, wherein the parameters comprise the compiling address of the operating system code and the space size of the operating system code;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
step S2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
According to the present invention, there is provided a bootstrap system adapted for an embedded SPARC architecture processor, comprising:
module M1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
module M2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate, the main core and the other cores jump into addresses corresponding to the SRAM, an operating system program is operated, and the booting process is completed.
Preferably, the compiling execution address of the boot loader is the starting address of the Nor flash; the execution address of the operating system program is the address of the SRAM;
the mirror image parameters are automatically generated according to the program information of the operating system in the compiling process and are stored in a fixed offset address of the mirror image through a link script;
the boot loader is relatively independent of the operating system program, compiled to embed in the front of the image with a preset section.
Preferably, the initializing the memory and the memory controller employs:
module M2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
module M2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
module M2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
module M2.6: and setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment.
Preferably, the writing of the operating system program from the Nor flash into the address corresponding to the SRAM adopts:
module M2.7: the SPARC processor main core reads the mirror image parameters from the appointed address of the system mirror image, wherein the parameters comprise the compiling address of the operating system code and the space size of the operating system code;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
module M2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention realizes a self-guiding method of the SPARC architecture processor, fills up the defects of the prior art and meets the existing requirements;
2. the boot program realized by the invention has the advantage of low requirement on the storage space, and the boot program occupies about 150KB of the storage space, which is far smaller than the requirement that the storage space of the main stream boot program (uboot and the like) is larger than 1M. Besides, the device has the characteristics of convenient maintenance, convenient downloading and curing and the like;
3. the invention has portability, tailorability and high flexibility, and is suitable for most embedded real-time operating systems to realize quick guidance;
4. the self-contained boot loader in the mirror image occupies a small amount of storage, namely about 150KB of storage space, so that the self-boot of the embedded multi-core processor is realized, the self-boot loader is automatically packaged with the operating system program during compiling, and a developer does not need to perceive the self-boot loader;
5. the invention realizes that the flash can be solidified after one-time downloading, and avoids the trouble that most of the bootstrap program and the operating system are separately maintained and downloaded;
6. the method is suitable for the multi-core processor with limited resources to realize convenient and low-cost rapid guidance.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a block diagram of a compiled mirror composition of the present invention.
FIG. 2 is a schematic diagram of a bootstrap system suitable for use with an embedded SPARC architecture processor.
Fig. 3 is a flow chart of the boot process of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.
Example 1
The self-booting method suitable for the embedded SPARC architecture processor provided by the invention comprises the following steps:
step S1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
step S2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate, the main core and the other cores jump into addresses corresponding to the SRAM, an operating system program is operated, and the booting process is completed.
Specifically, the compiling execution address of the boot loader is the starting address of the Nor flash; the execution address of the operating system program is the address of the SRAM.
Specifically, the image parameters are automatically generated according to the information of the operating system program in the compiling process and are stored in the fixed offset address of the image through the linking script.
Specifically, the boot loader is relatively independent of the operating system program, is compiled to be embedded into the front part of the mirror image in a preset section, and acquires information of the operating system program through mirror image parameters.
Specifically, the initialization memory and the memory controller employ:
step S2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
step S2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
step S2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
step S2.6: and setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment.
Specifically, the writing of the operating system program from the Nor flash into the address corresponding to the SRAM adopts:
step S2.7: the SPARC processor main core reads the image information from the appointed offset 0x80000 of the image, wherein the image information comprises the compiling address of the operating system code and the space size of the operating system code;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
step S2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
Specifically, the other cores except the main core of the processor are guided to start, and the process is as follows:
step S2.12: after other cores are awakened by the main core, the boot loader is executed from the address 0x00000000, the CPU debugging function is closed, the IU register and the local register of the SPARC architecture are initialized, and the processor config register is configured.
Step S2.13: the window registers are then initialized, DSU functions are set, and then exception handling and floating point functions are enabled. The interrupt flag is then cleared and the processor config register is reconfigured.
Step S2.14: initializing a floating point register, and disabling the level 1 cache and the level 2 cache.
Step S2.15: and setting sp pointers of each core, wherein the reserved size of each core stack space is 4K Byte.
Step S2.16: and the other cores of the processor jump into the SRAM address space where the compiling address of the operating system is located, and start to run operating system codes.
According to the present invention, as shown in fig. 2, a bootstrap system suitable for an embedded SPARC architecture processor includes:
module M1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
module M2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; enabling the main core of the SPARC processor to open other cores so that the other cores start to operate, jumping the main core and the other cores into addresses corresponding to the SRAM, operating an operating system program, and completing a boot process;
the SPARC processor is connected with the nonvolatile memory Nor flash through a system bus.
Specifically, the compiling execution address of the boot loader is the starting address of the Nor flash; the execution address of the operating system program is the address of the SRAM.
Specifically, the image parameters are automatically generated according to the information of the operating system program in the compiling process and are stored in the fixed offset address of the image through the linking script.
Specifically, the boot loader is relatively independent of the operating system program, is compiled to be embedded into the front part of the mirror image in a preset section, and acquires information of the operating system program through mirror image parameters.
Specifically, the initialization memory and the memory controller employ:
module M2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
module M2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
module M2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
module M2.6: and setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment.
Specifically, the writing of the operating system program from the Nor flash into the address corresponding to the SRAM adopts:
module M2.7: the SPARC processor main core reads the image information from the appointed offset 0x80000 of the image, wherein the image information comprises the compiling address of the operating system code and the space size of the operating system code;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
module M2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
Specifically, the other cores except the main core of the processor are guided to start, and the process is as follows:
module M2.12: after other cores are awakened by the main core, the boot loader is executed from the address 0x00000000, the CPU debugging function is closed, the IU register and the local register of the SPARC architecture are initialized, and the processor config register is configured.
Module M2.13: the window registers are then initialized, DSU functions are set, and then exception handling and floating point functions are enabled. The interrupt flag is then cleared and the processor config register is reconfigured.
Module M2.14: initializing a floating point register, and disabling the level 1 cache and the level 2 cache.
Module M2.15: and setting sp pointers of each core, wherein the reserved size of each core stack space is 4K Byte.
Module M2.16: and the other cores of the processor jump into the SRAM address space where the compiling address of the operating system is located, and start to run operating system codes.
Example 2
Example 2 is a preferred example of example 1
The compiling mirror structure diagram is shown in fig. 1.
The image is composed of 3 parts, a boot loader, image parameters and an operating system program. Where the boot loader compiles an address of 0x00000000, the address space actually stored in the Nor flash is also 0x00000000 from the CPU perspective, so the boot loader execution is actually performed in the flash. The compiling of the bootstrap program is separated from the operating system, the compiling is relatively independent after the compiling is completed, and the compiled bootstrap program is packaged to the forefront of the mirror image when the operating system program is compiled. The image parameters automatically generate an array according to the image size generated by the image compiling of the operating system, the initial address and other parameters, and then the image parameter array is put into the image space of the image offset 0x0007F000-0x0007FFFF through the link script. After the code of the operating system is compiled, the mirror image is placed at the offset 0x00080000 through the linking script, the compiling address of the operating system is the address of the SRAM, and the operating system determines that the operating system is self, and finally 3 parts are packed into the mirror image, and the structure is shown in figure 1.
The start-up procedure is shown in the start-up flow chart 3.
And solidifying the compiled image to the starting address 0x00000000 of the Nor flash, and starting the main core of the processor after power-on, namely starting the CPU 0. After start-up, the initialization of the core registers, config registers and floating point registers is started. Initializing a debugging serial port, initializing DDR2, setting an sp pointer to enter a C environment, acquiring parameters of an image from an address space of the image offset 0x0007F000-0x0007FFFF, and checking validity, wherein the image parameters comprise parameters such as compiling address, size and the like of an operating system image; after the mirror image information is acquired, starting to read the mirror image of the operating system from the mirror image fixed offset address 0x00080000 and writing the mirror image into an address corresponding to the SRAM; at this time, the CPU0 enables the CPU1 to the CPU3 to be turned on, and then the CPU0 jumps into an operating system code corresponding to the SRAM to give control right to the operating system. After the CPU1-CPU3 is turned on, it also starts execution from address 0x00000000, and then 3 CPUs initialize the corresponding core registers, config registers, and floating point registers, respectively. Setting a stack pointer sp of each CPU and entering a c environment, then each CPU respectively obtains the information of the operating system mirror image to obtain the initial address of the operating system in the SRAM, then jumping into the corresponding address, and giving control right to the operating system, so as to guide the starting of the multi-core processor.
Taking the multi-core processor S698PM of the boot SPARC architecture as an example, the system enters an embedded real-time operating system to complete the booting of the system. Firstly, compiling a bootstrap program and a program of an operating system, and forming a mirror image formed by the three parts. After the mirror image is obtained, the mirror image is burnt to the 0x00000000 address of the Nor flash, and then the board card of the multi-core processor S698PM is powered on. After the starting, the main core completes the initialization, then the operating system mirror image is carried from flash to SRAM, then the multi-core is enabled, the main core and other cores give control to the operating system, and finally the S698PM multi-core processor enters the embedded real-time operating system.
Those skilled in the art will appreciate that the systems, apparatus, and their respective modules provided herein may be implemented entirely by logic programming of method steps such that the systems, apparatus, and their respective modules are implemented as logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc., in addition to the systems, apparatus, and their respective modules being implemented as pure computer readable program code. Therefore, the system, the apparatus, and the respective modules thereof provided by the present invention may be regarded as one hardware component, and the modules included therein for implementing various programs may also be regarded as structures within the hardware component; modules for implementing various functions may also be regarded as being either software programs for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.
Claims (5)
1. A bootstrap method suitable for an embedded SPARC architecture processor, comprising:
step S1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
step S2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; enabling the main core of the SPARC processor to open other cores so that the other cores start to operate, jumping the main core and the other cores into addresses corresponding to the SRAM, operating an operating system program, and completing a boot process;
the boot loader is relatively independent of the operating system program, and is compiled to be embedded into the front part of the mirror image in a preset section;
the initialization memory and the memory controller employ:
step S2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
step S2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
step S2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
step S2.6: setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment;
the operating system program is written into the address corresponding to the SRAM from the Nor flash by adopting the following steps:
step S2.7: the SPARC processor main core reads the mirror image parameters from the appointed address of the system mirror image, wherein the parameters comprise the compiling address of the operating system code and the space size of the operating system code;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
step S2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
2. The bootstrapping method for an embedded SPARC architecture processor of claim 1 wherein the compiled execution address of the bootloader is a starting address of a Nor flash; the execution address of the operating system program is the address of the SRAM.
3. The method of claim 1, wherein the image parameters are automatically generated during compiling according to operating system program information and stored in a fixed offset address of the image by a linking script.
4. A bootstrap system for an embedded SPARC architecture processor, comprising:
module M1: packaging the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through a link script;
module M2: starting the SPARC processor main core from the Nor flash initial address, executing a boot loader, initializing a memory and a memory controller, acquiring information of an operating system program by the boot loader through mirror parameters, and writing the operating system program into an address corresponding to the SRAM from the Nor flash; enabling the main core of the SPARC processor to open other cores so that the other cores start to operate, jumping the main core and the other cores into addresses corresponding to the SRAM, operating an operating system program, and completing a boot process;
the boot loader is relatively independent of the operating system program, and is compiled to be embedded into the front part of the mirror image in a preset section;
the initialization memory and the memory controller employ:
module M2.1: closing a CPU debugging function, initializing a SPARC architecture, an IU register and a local register, and configuring a processor config register;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark, and reconfiguring a processor config register;
module M2.3: initializing a floating point register, disabling a level 1 cache and a level 2 cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and transmitting;
module M2.5: initializing a DDR2 controller, configuring a register of DDR2PHY until DDR2 initialization is completed;
module M2.6: setting sp pointers to memory addresses of the SRAM, and jumping into a c language environment;
the operating system program is written into the address corresponding to the SRAM from the Nor flash by adopting the following steps:
module M2.7: the SPARC processor main core reads the mirror image parameters from the appointed address of the system mirror image, wherein the parameters comprise the compiling address of the operating system code and the space size of the operating system code;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the obtained mirror image parameters are effective information, reading the mirror image of the operating system program from the mirror image fixed offset address, and writing the SRAM address space corresponding to the compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to operate;
module M2.11: the main core of the SPARC processor jumps into the SRAM address space where the compiling address of the operating system is located, and starts to run the operating system code.
5. The bootstrapping system of claim 4 adapted for an embedded SPARC architecture processor wherein the compiled execution address of the bootloader is a starting address of a Nor flash; the execution address of the operating system program is the address of the SRAM;
the mirror image parameters are automatically generated according to the program information of the operating system in the compiling process and are stored in a fixed offset address of the mirror image through a link script.
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