CN114064134A - Self-guiding method and system suitable for embedded SPARC (spatial Power control processor) architecture processor - Google Patents
Self-guiding method and system suitable for embedded SPARC (spatial Power control processor) architecture processor Download PDFInfo
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Abstract
The invention provides a self-guiding method and a system suitable for an embedded SPARC (spatial filter context) architecture processor, which comprise the following steps: step S1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script; step S2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a self-booting method and a self-booting system suitable for an embedded SPARC (spatial Power control) architecture processor.
Background
SPARC is one of the RISC microprocessor architectures that are commonly used in on-board computer systems. The stability and reliability of the performance of the processor in the satellite-borne computer system play an important role in the stability and reliability of the whole system, and the complex space environment determines the resource limitation of the satellite-borne computer system. Different from ARM, MIPS, X86 and other hot door architectures in the embedded field, SPARC does not form a mature and reliable bootstrap program, on one hand, because the resources of a common spaceborne are limited, no excessive peripheral equipment is provided, and no complex bootstrap program is needed, on the other hand, SPARC is generally used on a spaceborne, the use range is limited, and the software ecology is not as good as that of a CPU of a mainstream architecture. At present, the boot mode of the SPARC processor is relatively original, each CPU core is started by using a boot file, the address space and the resources of the CPU are initialized, a general boot program is not formed, and extra workload is brought to an application development engineer. To achieve optimal performance with limited resources, the operating system programs need to be executed in memory, and thus the boot program still needs to initialize hardware devices and create a mapping of memory space in order to prepare the correct software and hardware environment for the operating system kernel. Therefore, a simplified, convenient and low-cost quick bootstrap program needs to be designed for the SPARC processor in the on-board computer system so as to facilitate maintenance and development.
Patent document CN102707952A (application number: CN201210151037.5) discloses a parallel programming method based on user descriptions on an embedded heterogeneous multi-core processor. The method comprises the following steps: a user carries out description of a heterogeneous multi-core processor platform and tasks, parallel mode setting, primitive task creation and registration, task relation graph (DAG) generation and static allocation of the primitive tasks in the heterogeneous multi-core processor through a graphical interface configuration guide, and the characteristics of the processor platform, the parallel requirements and task assignment are expressed in a configuration file form (XML). And then embedding the elementary tasks after the configuration files are analyzed in parallel into the task tags of the heterogeneous multi-core framework codes, constructing a corresponding serial source program, and finally generating executable codes on the heterogeneous multi-core processor by calling a serial compiling tool.
Disclosure of Invention
In view of the defects in the prior art, the present invention provides a bootstrap method and system suitable for an embedded SPARC architecture processor.
The invention provides a self-booting method suitable for an embedded SPARC (processor over coax) architecture processor, which comprises the following steps:
step S1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
step S2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
Preferably, the compiling execution address of the boot loader is the starting address of Nor flash; and the execution address of the operating system program is the address of the SRAM.
Preferably, the image parameter is automatically generated according to the operating system program information in the compiling process and is stored in the fixed offset address of the image through a link script.
Preferably, the boot loader is relatively independent of the operating system program, compiled to embed the preset segment in the front of the image.
Preferably, the initialization memory and memory controller employs:
step S2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
step S2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
step S2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
step S2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
Preferably, the operating system program is written into the address corresponding to the SRAM from the Nor flash by adopting the following steps:
step S2.7: the SPARC processor main core reads mirror image parameters from a specified address of a system mirror image, wherein the mirror image parameters comprise a compiling address of an operating system code and the size of an operating system code space;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
step S2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
The invention provides a bootstrap system suitable for an embedded SPARC (spatial processor core) architecture processor, which comprises:
module M1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
module M2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
Preferably, the compiling execution address of the boot loader is the starting address of Nor flash; the execution address of the operating system program is the address of the SRAM;
the mirror image parameters are automatically generated according to the program information of the operating system in the compiling process and are stored in the fixed offset address of the mirror image through the link script;
the boot loader is relatively independent of the operating system program and is compiled to embed the preset segment in the front of the image.
Preferably, the initialization memory and memory controller employs:
module M2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
module M2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
module M2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
module M2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
Preferably, the operating system program is written into the address corresponding to the SRAM from the Nor flash by adopting the following steps:
module M2.7: the SPARC processor main core reads mirror image parameters from a specified address of a system mirror image, wherein the mirror image parameters comprise a compiling address of an operating system code and the size of an operating system code space;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
module M2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention realizes the self-guiding method of the SPARC framework processor, supplements the deficiency of the prior art and meets the prior requirement;
2. the bootstrap program realized by the invention has the advantage of low requirement on the storage space, and the storage space occupied by the bootstrap program is about 150KB and is far less than the requirement that the storage space of a main stream bootstrap program (uboot and the like) is more than 1M. In addition, the method has the characteristics of convenience in maintenance, downloading and curing and the like;
3. the invention has easy portability, tailorability and high flexibility, and is suitable for most embedded real-time operating systems to realize quick guidance;
4. the self-contained boot loader in the mirror image occupies a small amount of storage, about 150KB of storage space, so that self-booting of the embedded multi-core processor is realized, the embedded multi-core processor is automatically packaged with the operating system program during compiling, and developers do not need to sense the self-booting program;
5. the invention can be solidified to flash after downloading once, thereby avoiding the complexity of separate maintenance and separate downloading of most boot programs and an operating system;
6. the method is suitable for the multi-core processor with limited resources to realize rapid guidance with convenience and low cost.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
FIG. 1 is a block diagram of a compiled mirror composition of the present invention.
FIG. 2 is a diagram of a bootstrap system suitable for an embedded SPARC architecture processor.
FIG. 3 is a flow chart of the boot process of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
Example 1
The invention provides a self-booting method suitable for an embedded SPARC (processor over coax) architecture processor, which comprises the following steps:
step S1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
step S2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
Specifically, the compiling execution address of the boot loader is the starting address of the Nor flash; and the execution address of the operating system program is the address of the SRAM.
Specifically, the image parameters are automatically generated according to the operating system program information in the compiling process and are stored in the fixed offset address of the image through the link script.
Specifically, the boot loader is relatively independent of the operating system program, is compiled to be embedded in the front of the image in a preset segment, and the boot program acquires information of the operating system program through the image parameters.
Specifically, the initialization memory and memory controller employs:
step S2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
step S2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
step S2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
step S2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
Specifically, an operating system program is written into an address corresponding to the SRAM from the Nor flash, and the following steps are adopted:
step S2.7: the SPARC processor main core reads image information from a specified offset of 0x80000 of an image, wherein the image information comprises a compiling address of an operating system code and the size of an operating system code space;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
step S2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
Specifically, the other cores except the main core of the processor are guided to start, and the process is as follows:
step S2.12: after other cores are awakened by the main core, a boot loader is executed from the address 0x00000000, the CPU debugging function is closed, the SPARC architecture IU register and the local register are initialized, and the processor config register is configured.
Step S2.13: the window registers are then initialized, the DSU functions are set, and then exception handling and floating point functions are enabled. The interrupt flag is then cleared, and the processor config register is again configured.
Step S2.14: the floating point registers are initialized and the level 1 and level 2 caches are disabled.
Step S2.15: and setting an sp pointer of each core, wherein the reserved size of each core stack space is 4K Byte.
Step S2.16: and jumping other cores of the processor into the SRAM address space where the compiling address of the operating system is located, and starting to run the operating system code.
According to the present invention, a bootstrap system suitable for an embedded SPARC architecture processor is provided, as shown in fig. 2, including:
module M1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
module M2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a booting process;
the SPARC processor is connected with the Nor flash of the nonvolatile memory through a system bus.
Specifically, the compiling execution address of the boot loader is the starting address of the Nor flash; and the execution address of the operating system program is the address of the SRAM.
Specifically, the image parameters are automatically generated according to the operating system program information in the compiling process and are stored in the fixed offset address of the image through the link script.
Specifically, the boot loader is relatively independent of the operating system program, is compiled to be embedded in the front of the image in a preset segment, and the boot program acquires information of the operating system program through the image parameters.
Specifically, the initialization memory and memory controller employs:
module M2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
module M2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
module M2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
module M2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
Specifically, an operating system program is written into an address corresponding to the SRAM from the Nor flash, and the following steps are adopted:
module M2.7: the SPARC processor main core reads image information from a specified offset of 0x80000 of an image, wherein the image information comprises a compiling address of an operating system code and the size of an operating system code space;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
module M2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
Specifically, the other cores except the main core of the processor are guided to start, and the process is as follows:
module M2.12: after other cores are awakened by the main core, a boot loader is executed from the address 0x00000000, the CPU debugging function is closed, the SPARC architecture IU register and the local register are initialized, and the processor config register is configured.
Module M2.13: the window registers are then initialized, the DSU functions are set, and then exception handling and floating point functions are enabled. The interrupt flag is then cleared, and the processor config register is again configured.
Module M2.14: the floating point registers are initialized and the level 1 and level 2 caches are disabled.
Module M2.15: and setting an sp pointer of each core, wherein the reserved size of each core stack space is 4K Byte.
Module M2.16: and jumping other cores of the processor into the SRAM address space where the compiling address of the operating system is located, and starting to run the operating system code.
Example 2
Example 2 is a preferred example of example 1
The compiled mirror structure diagram is shown in fig. 1.
The image consists of 3 parts, a boot loader, image parameters and an operating system program. The compiled address of the boot loader starts at 0x00000000, and the address space actually stored in the Nor flash is also 0x00000000 from the CPU perspective, so that the execution of the boot loader is actually executed in the flash. The compiling of the bootstrap program is separated from the operating system, the bootstrap program is relatively independent after the compiling is completed, and the compiled bootstrap program is packed to the forefront of the mirror image when the operating system program is compiled. The mirror image parameter automatically generates an array according to the mirror image size generated by compiling the mirror image of the operating system, the initial address and other parameters, and then the mirror image parameter array is placed in the mirror image space with the mirror image offset of 0x0007F000-0x0007FFFF through the link script. After the code of the operating system is compiled, the mirror image is placed at the offset 0x00080000 through a chain pin book, the compiling address of the operating system is the address of the SRAM, the operating system determines the compiling address, and finally 3 parts are packed into one mirror image, and the structure is shown in FIG. 1.
The start-up procedure is shown in the start-up flow chart of fig. 3.
The compiled image is fixed to the Nor flash at the starting address 0x00000000, and the processor core is started first after power-on, that is, the CPU0 is started first. The initialization of the core, config and floating point registers begins after startup. Then initializing a debugging serial port, initializing DDR2, setting an sp pointer to enter a C environment, acquiring parameters of an image from an address space of the image offset 0x0007F000-0x0007FFFF and checking the legality, wherein the parameters of the image comprise parameters such as a compiling address, a size and the like of an operating system image; after acquiring the mirror image information, starting to read the mirror image of the operating system from the mirror image fixed offset address 0x00080000 and writing the mirror image of the operating system into an address corresponding to the SRAM; at this time, the CPU0 enables both the CPUs 1-3 to be turned on, and then the CPU0 jumps to the operating system code corresponding to the SRAM to give control to the operating system. CPU1-CPU3 is also turned on, starting from address 0x00000000, and then 3 CPUs initialize the corresponding core, config, and floating point registers, respectively. And then setting a stack pointer sp of each CPU and entering a c environment, then respectively acquiring information of an operating system image by each CPU to obtain a starting address of the operating system in the SRAM, then jumping in a corresponding address, and giving control right to the operating system, so as to guide and finish the starting of the multi-core processor.
Taking the guidance of the multi-core processor S698PM of the SPARC architecture as an example, the system enters an embedded real-time operating system to complete the guidance of the system. The compilation of the boot program and the program of the operating system is first completed and a three-part image is formed. After the image is obtained, the image is burned to the 0x00000000 address of the Nor flash, and then the board card of the multi-core processor S698PM is powered on and started. After starting, the main core completes initialization, then the operating system image is carried to the SRAM from the flash, then multi-core is enabled, the main core and other cores give control right to the operating system, and finally S698PM multi-core processor entering the embedded real-time operating system is completed.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (10)
1. A bootstrap method for an embedded SPARC architecture processor, comprising:
step S1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
step S2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
2. The bootstrap method for an embedded SPARC architecture processor as recited in claim 1, wherein the compiling execution address of the bootstrap loader is a start address of Nor flash; and the execution address of the operating system program is the address of the SRAM.
3. The bootstrap method for embedded SPARC architecture processor as recited in claim 1, wherein the image parameters are automatically generated during compilation process according to operating system program information and stored in fixed offset address of the image through a linking script.
4. The bootstrap method for an embedded SPARC architecture processor as recited in claim 1, wherein the bootstrap loader is relatively independent of the operating system program, compiled to be embedded in a preset segment in front of the mirror.
5. The bootstrap method for embedded SPARC architecture processor as recited in claim 1, wherein said initialization memory and memory controller employs:
step S2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
step S2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
step S2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
step S2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
step S2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
step S2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
6. The bootstrap method for embedded SPARC architecture processor as recited in claim 1, wherein writing the operating system program from Nor flash to the address corresponding to SRAM employs:
step S2.7: the SPARC processor main core reads mirror image parameters from a specified address of a system mirror image, wherein the mirror image parameters comprise a compiling address of an operating system code and the size of an operating system code space;
step S2.8: checking whether the read mirror image parameters are valid information;
step S2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
step S2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
step S2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
7. A bootstrap system for an embedded SPARC architecture processor, comprising:
module M1: packing the boot loader, the mirror image parameters and the operating system program into a system mirror image of the SPARC processor through the link script;
module M2: the SPARC processor main core is started from the Nor flash initial address, executes a boot loader, initializes the memory and the memory controller, obtains information of an operating system program through the mirror image parameters by the boot loader, and writes the operating system program into an address corresponding to the SRAM from the Nor flash; and enabling the main core of the SPARC processor to open other cores, so that the other cores start to run, jumping the main core and the other cores into addresses corresponding to the SRAM, running an operating system program, and finishing a boot process.
8. The bootstrap system for an embedded SPARC architecture processor as recited in claim 7, wherein the compilation execution address of the boot loader is a start address of Nor flash; the execution address of the operating system program is the address of the SRAM;
the mirror image parameters are automatically generated according to the program information of the operating system in the compiling process and are stored in the fixed offset address of the mirror image through the link script;
the boot loader is relatively independent of the operating system program and is compiled to embed the preset segment in the front of the image.
9. The bootstrap system for embedded SPARC architecture processor as recited in claim 7, wherein said initialization memory and memory controller employs:
module M2.1: closing the debugging function of the CPU, initializing the SPARC architecture, the IU register and the local register, and configuring a config register of the processor;
module M2.2: initializing a window register, setting a DSU function, and enabling exception handling and floating point functions; clearing the interrupt mark and reconfiguring the processor config register again;
module M2.3: initializing a floating-point register, disabling the 1-level cache and the 2-level cache, and initializing a controller of a memory;
module M2.4: initializing pin multiplexing and baud rate of a serial port, and enabling receiving and sending;
module M2.5: initializing a DDR2 controller, and configuring a register of a DDR2PHY until the DDR2 is initialized;
module M2.6: setting sp pointer to SRAM memory address, and jumping to c language environment.
10. The bootstrap system for embedded SPARC architecture processor as recited in claim 7, wherein the writing of the operating system program from Nor flash to the address corresponding to SRAM employs:
module M2.7: the SPARC processor main core reads mirror image parameters from a specified address of a system mirror image, wherein the mirror image parameters comprise a compiling address of an operating system code and the size of an operating system code space;
module M2.8: checking whether the read mirror image parameters are valid information;
module M2.9: when the acquired mirror image parameter is effective information, reading a mirror image of an operating system program from a mirror image fixed offset address, and writing the mirror image into an SRAM address space corresponding to a compiling address of the operating system;
module M2.10: the main core of the SPARC processor enables other cores to be opened, so that the other cores start to run;
module M2.11: and jumping into the SRAM address space where the compiling address of the operating system is located by the main core of the SPARC processor, and starting to run the operating system code.
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