CN114063520A - Switch, communication system and control method - Google Patents
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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Abstract
The application provides a switch, a communication system and a control method, which relate to the field of circuits, wherein the switch comprises a microcontroller, a first control chip and a plurality of second control chips; the first control chip is used for acquiring a target control signal and sending the target control signal to the microcontroller, and the microcontroller determines a target second control chip from the plurality of second control chips and controls the target second control chip to be in a working state when receiving the target control signal; the first control chip is used for acquiring first protocol data and sending the first protocol data to the target second control chip, and the target second control chip sends the first protocol data to the corresponding external terminal equipment when receiving the first protocol data so that the corresponding external terminal equipment can work according to the first protocol data. The switch can solve the problem that different slave devices on the same RS-485 bus are incompatible.
Description
Technical Field
The present application relates to the field of circuits, and in particular, to a switch, a communication system, and a control method.
Background
At present, the RS-485 serial bus standard has the advantages of good noise interference resistance, long-distance transmission, multi-machine support capability, low price and the like, so that the RS-485 serial bus standard is widely applied to communication among industrial equipment.
RS485 adopts a half-duplex working mode to support multipoint data communication. The RS485 bus network topology generally adopts a bus type structure with matched terminals, that is, one RS485 bus is adopted to connect all slave devices in series. Although the devices produced by different device manufacturers all use the RS-485 hardware protocol, the devices almost all use the customized communication protocol, or the communication protocols between different RS-485 devices of the same manufacturer are not compatible with each other, so that the devices cannot work together on the same RS-485 bus.
Disclosure of Invention
An object of the embodiments of the present application is to provide a switch, a communication system, and a control method, so as to solve the problem that different slave devices on the same bus are incompatible.
In a first aspect, the present application provides a switch, comprising: the system comprises a microcontroller, a first control chip and a plurality of second control chips;
the first control chip is connected with the microcontroller;
the plurality of second control chips are connected with the microcontroller;
each second control chip is used for connecting an external terminal device;
the first control chip is used for acquiring a target control signal and sending the target control signal to the microcontroller, and the microcontroller determines a target second control chip from the second control chips and controls the target second control chip to be in a working state when receiving the target control signal;
the first control chip is used for acquiring first protocol data and sending the first protocol data to the target second control chip, and the target second control chip sends the first protocol data to corresponding external terminal equipment when receiving the first protocol data so that the corresponding external terminal equipment can work according to the first protocol data.
The switch provided by the embodiment of the application comprises a microcontroller, a first control chip and a plurality of second control chips, wherein the target second control chip in a working state at present is determined through a target control signal sent by the microcontroller, and the external terminal equipment is controlled to work. The switch can control only one external terminal device to work in one time period, and can avoid the interference of other external terminal devices to the external terminal device during working, so that the problem that different external terminal devices on the same bus are incompatible is solved.
In an alternative embodiment, the second control chip includes a first terminal of the second control chip;
and the first end of the second control chip is connected with the first control chip and used for receiving the first protocol data.
In the above embodiment, the first end of the second control chip is connected to the first control chip, so as to facilitate transmission of the first protocol data with the first control chip.
In an optional embodiment, the second control chip further includes a second end of the second control chip;
and the second end of the second control chip is used for receiving second protocol data sent by the external terminal equipment.
In the above embodiment, the second end of the second control chip is connected to the external terminal device, so as to facilitate transmission of the second protocol data with the external terminal device.
In an optional embodiment, the switch further comprises: a transient voltage suppressor diode and a matching resistor;
the transient voltage suppression diode and the matching resistor are connected to a second end of the second control chip.
In the above embodiment, the transient voltage suppressor may implement surge protection for the second control chip, and the matching resistor may improve stability of data transmission of the second protocol.
In an optional embodiment, the second control chip further includes a third terminal of the second control chip;
and the third end of the second control chip is used for sending the second protocol data to the first control chip.
In the above embodiment, the third terminal of the second control chip is connected to the first control chip, so as to facilitate data transmission with the first control chip.
In an optional embodiment, the second control chip further includes a control terminal of the second control chip;
and the control end of the second control chip is connected with the microcontroller and used for receiving the target control signal.
In the above embodiment, the control terminal of the second control chip is connected to the microcontroller, so as to transmit the target control signal to the microcontroller.
In a second aspect, an embodiment of the present application provides a communication system, including: a plurality of terminal devices and switches;
and the plurality of terminal devices are connected with the second ends of the plurality of second control chips.
In the communication system provided in the embodiment of the present application, the plurality of terminal devices are connected to the second ends of the plurality of second control chips, so that transmission of the second protocol data is facilitated.
In an optional implementation manner, the terminal device generates second protocol data and transmits the second protocol data to the second end of the second control chip.
In the above embodiment, the terminal device generates the second protocol data, transmits the second protocol data to the second end of the second control chip, transmits the second protocol data to the first control chip, and transmits the second protocol data to the external control terminal, so that the external control terminal can conveniently acquire the working condition of the terminal device.
In a third aspect, an embodiment of the present application provides a control method, which is applied to a switch, where the switch includes: the system comprises a microcontroller, a first control chip and a plurality of second control chips, wherein the first control chip is connected with the microcontroller, and the second control chips are connected with the microcontroller; the control method comprises the following steps:
receiving a control request sent by a control terminal;
sending the control request to the microcontroller through the first control chip;
determining first protocol data and a target control signal according to the control request through the microcontroller;
determining a target second control chip in a working state at present according to the target control signal through the microcontroller;
transmitting first protocol data to the target second control chip through the first control chip;
and transmitting the first protocol data to corresponding external terminal equipment through the target second control chip so that the corresponding external terminal equipment works according to the first protocol data.
According to the control method provided by the embodiment of the application, the target second control chip in the working state at present is determined according to the control request of the control terminal, and the external terminal equipment is controlled to work. The control method can control only one external terminal device to work in one time period so as to avoid the interference of other external terminal devices to the external terminal device during working, thereby solving the problem that different external terminal devices on the same bus are incompatible.
In an optional embodiment, the target control signal comprises: receiving a signal, sending a signal and a high-impedance state signal; the second control chip includes: the first end of the second control chip, the second end of the second control chip and the control end of the second control chip; the determining, by the microcontroller and according to the target control signal, a target second control chip currently in a working state includes:
if the control end of the second control chip receives the receiving signal or the sending signal, the second control chip is the target second control chip in a working state;
and if the control end of the second control chip receives the high-resistance state signal, the second control chip is not the target second control chip in the working state.
In the above embodiment, the target second control chip determines its operating state according to the target control signal received by the target second control chip, and may be in a receiving state, a transmitting state and a high impedance state. When the external terminal works, other external terminals can be set to be in a high-impedance state, and the problem of mutual interference when different external terminal devices work simultaneously can be solved.
In an optional embodiment, the method further comprises:
and receiving an initialization signal sent by the control terminal through the microcontroller.
In the above embodiment, the control terminal sends the initialization signal to the microcontroller to initialize the working state of the microcontroller, which may facilitate the control of the working state of the switch.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a schematic structural diagram of a switch provided in an embodiment of the present application;
fig. 2 is a specific circuit diagram of a microprocessor of a switch according to an embodiment of the present application;
fig. 3 is a specific circuit diagram of a plurality of second control chips of a switch according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of a second control chip of a switch according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of a communication system according to an embodiment of the present application;
fig. 6 is a flowchart of a control method according to an embodiment of the present application;
fig. 7 is a schematic operating environment diagram of a control method according to an embodiment of the present application.
Icon: 100-a switch; 110-a microcontroller; 120-a first control chip; 130-a second control chip; 131-a first terminal of a second control chip; 132-a second terminal of the second control chip; 133-a third terminal of the second control chip; 134-control end of second control chip; 200-a communication system; 210-a terminal device; 300-control terminal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The following detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
The applicant found in the course of the study: in multi-machine communication, it is most important to ensure that communication is performed orderly, and thus a strict communication protocol and sophisticated communication software are required. The multi-machine communication system formed by the RS-485 mode adopts a master-slave mode structure: the master device controls a plurality of slave devices, and a singlechip serving as the slave device does not actively send commands or data, and all the slave devices are controlled by the master device; in a multi-machine system, only one master device is provided, and all slave devices cannot communicate with each other, and even if information is exchanged, the information must be forwarded through the master device.
Although the devices produced by different device manufacturers all use RS-485 hardware protocols, the devices almost all use self-defined communication protocols, or the communication protocols between different RS-485 devices of the same manufacturer are also possibly incompatible with each other, so that the devices cannot work on the same RS-485 bus together; the traditional RS-485 hub effectively solves the transmission problem caused by distance and potential difference in a heterogeneous network through photoelectric isolation, but generally does not consider the problem that software communication protocols among a plurality of different slave devices are incompatible.
Based on this, an embodiment of the present application provides an exchange, which includes a microcontroller, a first control chip, and a plurality of second control chips, and determines a target second control chip currently in a working state through a target control signal sent by the microcontroller, so as to control an external terminal device to work. The switch can control only one external terminal device to work in a time period so as to avoid the interference of other external terminal devices to the external terminal device during working, thereby solving the problem of mutual interference of different external terminal devices on the same bus during working. The method provided by the present application is described below by way of several examples.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a switch according to an embodiment of the present application.
The embodiment of the present application provides a switch 100, including: a microcontroller 110, a first control chip and a plurality of second control chips 130.
Alternatively, the microcontroller 110 may be an integrated circuit chip having signal processing capabilities. The microcontroller 110 may be a general-purpose Processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the Integrated Circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. Illustratively, the microcontroller 110 may be STM32F030C8T 6. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed.
Alternatively, the first control chip 120 may be an RS485 control chip for matching the levels of the control terminal 300 and the switch 100. Since the level value of the data in the 485 communication protocol is higher than that of the microcontroller, the level value of the data in the 485 communication protocol and that of the microcontroller may be matched by the first control chip 120.
Alternatively, the plurality of second control chips 130 may also be RS-485 control chips. When RS-485 selects the type of the second control chip of RS-485, the standard of RS-485 interface, the number of nodes, and half-duplex or full-duplex working mode can be considered. In one example, the second control chip 130 may be TP 8485E.
As shown in fig. 2, fig. 2 is a circuit diagram of a microcontroller of a switch according to an embodiment of the present application. As shown in fig. 3, fig. 3 is a specific circuit diagram of a plurality of second control chips of a switch according to an embodiment of the present application.
Optionally, the first control chip 120 is connected to the microcontroller 110, and a plurality of second control chips 130 are connected to the microcontroller 110, each second control chip 130 being used for connecting to an external terminal device 210.
Illustratively, the first control chip 120 is connected to the microcontroller 110, and the first control chip 120 is further connected to the second control chip 130. Therefore, the first protocol data is directly sent to the target second control chip 130 in the working state by the first control chip 120 without passing through the microcontroller, and the communication delay is reduced.
Illustratively, the second control chip 130 is connected to the microcontroller 110 at one end and to the external terminal device 210 at the other end. The microcontroller 110 sends the related instruction to the second control chip 130 to determine the working state of the second control chip 130, and if the second control chip 130 is in the sending state, the second control chip 130 sends the related data to the external terminal device 210 through the RS485 bus. The external terminal device 210 may be a different RS-485 device, and the external terminal device 210 may also be the same RS-485 device. In one example, the external terminal device 210 may be a temperature and humidity sensor, the external terminal device 210 may also be a printer, and the external terminal device 210 may also be an RS-485 camera.
Illustratively, the second control chip 130 and the external terminal device 210 may be connected by a cable, and the external terminal device 210 may communicate with the switch 100 over a long distance. The cable can adopt a shielding twisted pair, so that the data transmission line is twisted in pairs, and the outer layer adopts a shielding layer to shield external electromagnetic interference. The cable can also adopt a mode that data transmission lines are parallel to each other for near field communication.
Optionally, the first control chip 120 is configured to obtain a target control signal and send the target control signal to the microcontroller 110, and when the microcontroller 110 receives the target control signal, the target second control chip 130 is determined from the plurality of second control chips 130, and the target second control chip 130 is controlled to be in a working state.
Illustratively, the target control signal may be a signal for selecting the target second control chip 130 in an operating state, and the target control signal may be a transmission signal, a reception signal, and a high impedance state signal. In one example, the target second control chip 130 may be set to a transmitting, receiving or high impedance state according to the level of the RE pin and the DE pin, and when the second control chip 130 is in the high impedance state, all transmission signals are blocked.
Optionally, the first control chip 120 is configured to obtain first protocol data and send the first protocol data to the target second control chip 130, and when receiving the first protocol data, the target second control chip 130 sends the first protocol data to the corresponding external terminal device 210, so that the corresponding external terminal device 210 works according to the first protocol data.
Illustratively, the first protocol data may be a related instruction sent by the master RS-485 device to control the corresponding target second control chip 130 to operate, the first control chip 120 transmits the first protocol data to the target second control chip 130, the target second control chip 130 sends the related instruction to the corresponding external terminal device 210, after the external terminal device 210 may execute the related instruction, the external terminal device sends a corresponding status code to the target second control chip 130, the target second control chip 130 sends the status code to the first control chip 120, and the first control chip 120 sends the status code to the master RS-485 device, which indicates that it may continue with a next instruction.
For example, the target second control chip 130 in the sending working state may transmit the first protocol data to the corresponding external terminal device 210, and after receiving the first protocol data, the external terminal device 210 executes the work corresponding to the first protocol data. In one example, the external terminal device 210 adopts half-duplex communication in data communication, wherein half-duplex communication means that data can be transmitted in both directions, but one channel allows only one-way transmission at the same time. If the transmission direction is to be changed, a handover is required.
As shown in fig. 4, fig. 4 is a schematic structural diagram of a second control chip of a switch according to an embodiment of the present application.
Optionally, the second control chip 130 includes a first end 131 of the second control chip, and the first end 131 of the second control chip is connected to the external control terminal 300 for receiving the first protocol data.
Illustratively, the first end 131 of the second control chip may be a DI pin (data receiving port) of the second control chip 130, and receives the first protocol data transmitted by the first control chip 120.
Optionally, the second control chip 130 further includes a second end 132 of the second control chip, and the second end 132 of the second control chip is configured to receive the second protocol data of the external terminal device 210.
Illustratively, the second end 132 of the second control chip may be an a port and a B port of the second control chip 130, the a interface is not only a data receiving port but also a data output port, and the B interface is not only a data receiving port but also a data output port.
The second protocol data may be status data transmitted after the external terminal device 210 operates, and the second protocol data may be a pair of data in a differential form.
Illustratively, the data signals of the a port and the B port are a pair of differential signals, and when the first end 131 of the second control chip receives the first protocol data, the second control chip 130 converts the first protocol data into the differential signals to be output by the a port and the B port. When the a port and the B port of the second end 132 of the second control chip receive the second protocol data, the second control chip 130 converts the second protocol data in differential form into data in single-ended form.
Optionally, the switch 100 further includes a tvs and a matching resistor, which are connected to the second end 132 of the second control chip.
Illustratively, the tvs is a high-performance protection device in the form of a diode, which can protect the second control chip 130 from various surge pulses. The second control chip 130 is connected to the external terminal device 210, a surge pulse may be introduced into the external terminal device 210, the surge pulse may damage the second control chip 130, and the transient voltage suppressor diode is disposed at the second end 132 of the second control chip, so that the second control chip 130 may be effectively protected. In one example, the transient voltage suppression diode may be SMF5.0A.
Illustratively, a matching resistor is further disposed at the second end 132 of the second control chip, and the matching resistor can ensure stability of data transmitted by the second control chip 130 to the external terminal device 210. In one example, the matching resistor may have a resistance of 4.7K and the matching resistor may have a resistance of 5.1K. The person skilled in the art can select the compound according to the needs without specific limitations.
Optionally, the second control chip 130 further includes a third terminal 133 of the second control chip, and the third terminal 133 of the second control chip is configured to send the second protocol data to the first control chip 120.
Illustratively, the third terminal 133 of the second controller chip may be an RO pin (data receiving port) of the second controller chip 130, and transmits the second protocol data to the first controller chip 120.
Optionally, the second control chip 130 further includes a control terminal 134 of the second control chip, and the control terminal 134 of the second control chip is connected to the microcontroller 110 for receiving the target control signal.
Illustratively, the control terminal 134 of the second control chip may be an RE pin (control signal port) and a DE pin (control signal port) of the second control chip 130. The state of the second control chip 130 is controlled by controlling the levels of RE and DE high and low.
As shown in fig. 5, fig. 5 is a schematic structural diagram of a communication system according to an embodiment of the present application.
The embodiment of the present application provides a communication system 200, and the communication system 200 includes a plurality of terminal devices 210 and a switch 100. The plurality of terminal devices 210 are connected to the second terminals 132 of the plurality of second control chips.
Illustratively, the plurality of terminal devices 210 may be the same terminal device 210 or may be different terminal devices 210. The terminal device 210 may be any device that communicates based on the RS-485 protocol.
Optionally, the terminal device 210 generates second protocol data for transmission to the second end 132 of the second control chip.
Illustratively, the terminal device 210 receives the first protocol data, performs a corresponding action, generates second protocol data, and transmits the second protocol data to the second end 132 of the second control chip.
As shown in fig. 6, fig. 6 is a flowchart of a control method provided in the embodiment of the present application, and as shown in fig. 7, fig. 7 is a schematic operating environment diagram of a control method provided in the embodiment of the present application.
The embodiment of the present application provides a control method, which is applied to a switch 100, where the switch 100 includes: the microcontroller 110, the first control chip 120 and a plurality of second control chips 130, the first control chip 120 is connected with the microcontroller 110, and the plurality of second control chips 130 are connected with the microcontroller 110; the control method includes steps 310-350.
Illustratively, the control terminal is a master device which communicates based on the RS-485 protocol, and the control terminal can be a server, for example, a network server, a database server, and the like. The control terminal may be a terminal device such as a Personal Computer (PC).
And step 320, sending a control request to the microcontroller through the first control chip.
And step 330, determining a target control signal according to the control request through the microcontroller.
And 340, determining the target second control chip in the working state according to the target control signal through the microcontroller.
And 360, transmitting the first protocol data to the corresponding external terminal equipment through the target second control chip so that the corresponding external terminal equipment can work according to the first protocol data.
Based on the same application concept, because the principle of solving the problem of the control method in the embodiment of the present application is similar to that in the embodiment of the switch, the control method in the embodiment of the present application may refer to the description in the embodiment of the switch, and repeated descriptions are omitted.
Optionally, the target control signal comprises: receiving a signal, sending a signal and a high-impedance state signal; the second control chip includes: the first end of the second control chip, the second end of the second control chip and the control end of the second control chip. Step 340 may include step 341 and step 342.
Step 341, if the control end of the second control chip receives the receiving signal or the sending signal, the second control chip is the target second control chip in the working state.
In step 342, if the control end of the second control chip receives the high impedance state signal, the second control chip is not the target second control chip in the working state.
Illustratively, the target control signal may be controlled in the reception state by the control logic of table 1.
TABLE 1
In table 1, 0 represents low level, 1 represents high level, and X represents that the input is high level or low level does not affect the output level. The communication flow between the control terminal and different second control chips is as follows:
when DE is high level and DI is high level, the control terminal communicates with the second control chip.
When DE is high level and DI is low level, the control terminal communicates with the second control chip.
When RE is low and DE is low, the control terminal does not communicate with the second control chip.
When RE is high level and DE is low level, the control terminal does not communicate with the second control chip.
Illustratively, the target control signal may control the transmission state through the control logic of table 2.
TABLE 2
In table 2, 0 represents low level, 1 represents high level, and X represents that the input is high level or low level does not affect the output level. The communication flow between the external terminal equipment and different second control chips is as follows:
when RE is low level and DE is low level, the external terminal device communicates with the second control chip.
When RE is high level and DE is low level, the external terminal device does not communicate with the second control chip.
Optionally, the control method provided in the embodiment of the present application further includes:
and receiving an initialization signal of the control terminal through the microcontroller.
Illustratively, the control terminal sends an initialization signal to the microcontroller, which initializes the operating state of the microcontroller. The control terminal can control the switch to switch the working mode at any time, and the working efficiency of the switch is improved.
In addition, an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the computer program performs the steps of any of the methods described above.
The computer program product of the control method provided in the embodiment of the present application includes a computer-readable storage medium storing a program code, where instructions included in the program code may be used to execute the steps of the control method in the above method embodiment, which may be specifically referred to in the above method embodiment, and details are not described here again.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes. It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A switch, comprising: the system comprises a microcontroller, a first control chip and a plurality of second control chips;
the first control chip is connected with the microcontroller;
the plurality of second control chips are connected with the microcontroller;
each second control chip is used for connecting an external terminal device;
the first control chip is used for acquiring a target control signal and sending the target control signal to the microcontroller, and the microcontroller determines a target second control chip from the second control chips and controls the target second control chip to be in a working state when receiving the target control signal;
the first control chip is used for acquiring first protocol data and sending the first protocol data to the target second control chip, and the target second control chip sends the first protocol data to corresponding external terminal equipment when receiving the first protocol data so that the corresponding external terminal equipment can work according to the first protocol data.
2. The switch of claim 1, wherein the second control chip comprises a first end of the second control chip;
and the first end of the second control chip is connected with the first control chip and used for receiving the first protocol data.
3. The switch of claim 2, wherein the second control chip further comprises a second end of the second control chip;
and the second end of the second control chip is used for receiving second protocol data sent by the external terminal equipment.
4. The switch of claim 3, further comprising: a transient voltage suppressor diode and a matching resistor;
the transient voltage suppression diode and the matching resistor are connected to a second end of the second control chip.
5. The switch of claim 3, wherein the second control chip further comprises a third terminal of the second control chip;
and the third end of the second control chip is used for sending the second protocol data to the first control chip.
6. The switch of claim 1, wherein the second control chip further comprises a control terminal of the second control chip;
and the control end of the second control chip is connected with the microcontroller and used for receiving the target control signal.
7. A communication system, comprising: a plurality of end devices and the switch of any of claims 1-6;
and the plurality of terminal devices are connected with the second ends of the plurality of second control chips.
8. A control method applied to a switch, the switch comprising: the system comprises a microcontroller, a first control chip and a plurality of second control chips, wherein the first control chip is connected with the microcontroller, and the second control chips are connected with the microcontroller; the control method comprises the following steps:
receiving a control request sent by a control terminal;
sending the control request to the microcontroller through the first control chip;
determining a target control signal according to the control request through the microcontroller;
determining a target second control chip in a working state at present according to the target control signal through the microcontroller;
transmitting first protocol data to the target second control chip through the first control chip;
and transmitting the first protocol data to corresponding external terminal equipment through the target second control chip so that the corresponding external terminal equipment works according to the first protocol data.
9. The method of claim 8, wherein the target control signal comprises: receiving a signal, sending a signal and a high-impedance state signal; the second control chip includes: the first end of the second control chip, the second end of the second control chip and the control end of the second control chip; the determining, by the microcontroller and according to the target control signal, a target second control chip currently in a working state includes:
if the control end of the second control chip receives the receiving signal or the sending signal, the second control chip is the target second control chip in a working state;
and if the control end of the second control chip receives the high-resistance state signal, the second control chip is not the target second control chip in the working state.
10. The method of claim 8, further comprising:
and receiving an initialization signal sent by the control terminal through the microcontroller.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008095201A1 (en) * | 2007-02-02 | 2008-08-07 | Psimast, Inc. | Processor chip architecture having integrated high-speed packet switched serial interface |
| CN205983798U (en) * | 2016-08-12 | 2017-02-22 | 长江水利委员会长江科学院 | Sensor acquisition device based on loRa wireless module |
| CN110609801A (en) * | 2019-08-09 | 2019-12-24 | 苏州浪潮智能科技有限公司 | Adapter plate and server system |
| US20200065290A1 (en) * | 2019-08-05 | 2020-02-27 | Intel Corporation | Mechanism for device interoperability of switches in computer buses |
| CN111737186A (en) * | 2016-10-10 | 2020-10-02 | 英特尔公司 | Multi-die hardware processor and method |
| CN213934867U (en) * | 2020-11-27 | 2021-08-10 | 中国科学院声学研究所 | Embedded multi-interface data acquisition and processing device |
-
2021
- 2021-11-17 CN CN202111358928.3A patent/CN114063520B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008095201A1 (en) * | 2007-02-02 | 2008-08-07 | Psimast, Inc. | Processor chip architecture having integrated high-speed packet switched serial interface |
| CN205983798U (en) * | 2016-08-12 | 2017-02-22 | 长江水利委员会长江科学院 | Sensor acquisition device based on loRa wireless module |
| CN111737186A (en) * | 2016-10-10 | 2020-10-02 | 英特尔公司 | Multi-die hardware processor and method |
| US20200065290A1 (en) * | 2019-08-05 | 2020-02-27 | Intel Corporation | Mechanism for device interoperability of switches in computer buses |
| CN110609801A (en) * | 2019-08-09 | 2019-12-24 | 苏州浪潮智能科技有限公司 | Adapter plate and server system |
| CN213934867U (en) * | 2020-11-27 | 2021-08-10 | 中国科学院声学研究所 | Embedded multi-interface data acquisition and processing device |
Non-Patent Citations (1)
| Title |
|---|
| 田建新: "全字段加密交换机密钥管理方案设计与实现", 《计算机工程与设计》, 30 November 2007 (2007-11-30) * |
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