CN114038863A - Array substrate, preparation method thereof and display device - Google Patents

Array substrate, preparation method thereof and display device Download PDF

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Publication number
CN114038863A
CN114038863A CN202111318605.1A CN202111318605A CN114038863A CN 114038863 A CN114038863 A CN 114038863A CN 202111318605 A CN202111318605 A CN 202111318605A CN 114038863 A CN114038863 A CN 114038863A
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Prior art keywords
layer
base plate
protective
substrate
substrate base
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CN202111318605.1A
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Chinese (zh)
Inventor
程磊磊
张扬
周斌
刘军
刘宁
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to CN202111318605.1A priority Critical patent/CN114038863A/en
Publication of CN114038863A publication Critical patent/CN114038863A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The disclosure relates to the technical field of display, and discloses an array substrate, a preparation method thereof and a display device; the array substrate comprises a substrate, a first conducting layer, a protective layer, an interlayer dielectric layer and a second conducting layer; the first conducting layer is arranged on one side of the substrate and comprises a connecting part; the protective layer is arranged on one side, far away from the substrate base plate, of the first conductive layer, and a first through hole is formed in the protective layer and communicated to the connecting portion; the interlayer dielectric layer is arranged on one side of the protective layer far away from the substrate base plate, a second through hole is formed in the interlayer dielectric layer and communicated with the first through hole, and the orthographic projection of the second through hole on the substrate base plate is overlapped with the orthographic projection of the protective layer on the substrate base plate; the second conducting layer is arranged on one side, far away from the substrate base plate, of the interlayer dielectric layer and connected with the connecting portion through the first through hole and the second through hole. The array substrate is not easy to generate poor contact and has good display effect.

Description

Array substrate, preparation method thereof and display device
Technical Field
The disclosure relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device comprising the array substrate.
Background
In a large-sized OLED (Organic light emitting semiconductor) Display device, a thicker metal layer and an insulation film layer are used to achieve the purpose of uniform signal transmission; however, contact failure is likely to occur in a via hole formed in a thick insulating film layer.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to overcome the disadvantages of the prior art that contact failure is easily generated, and to provide an array substrate and a method for manufacturing the array substrate, and a display device including the array substrate, in which contact failure is not easily generated.
According to an aspect of the present disclosure, there is provided an array substrate including:
a substrate base plate;
a first conductive layer provided on one side of the substrate base, the first conductive layer including a connection portion;
the protective layer is arranged on one side, far away from the substrate base plate, of the first conducting layer, and a first through hole is formed in the protective layer and communicated to the connecting portion;
the interlayer dielectric layer is arranged on one side, far away from the substrate base plate, of the protective layer, a second through hole is formed in the interlayer dielectric layer and communicated with the first through hole, and the orthographic projection of the second through hole on the substrate base plate is overlapped with the orthographic projection of the protective layer on the substrate base plate;
the second conducting layer is arranged on one side, far away from the substrate base plate, of the interlayer dielectric layer and is connected with the connecting part through the first via hole and the second via hole.
In an exemplary embodiment of the present disclosure, the material of the protective layer is one or two of light-sensitive silicone and silicon oxide formed by exposing the light-sensitive silicone.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
the isolation layer is arranged between the protective layer and the interlayer dielectric layer, a third through hole is formed in the isolation layer, and the third through hole is communicated with the second through hole and the first through hole.
In one exemplary embodiment of the present disclosure, the first conductive layer includes:
an active layer including a channel portion and a conductor portion, the conductor portion being the connection portion;
a first data line, a portion of the first data line being the connection portion.
In an exemplary embodiment of the present disclosure, the array substrate further includes:
a light-shielding layer disposed between the substrate and the active layer;
a buffer layer disposed between the light-shielding layer and the active layer;
the gate insulating layer is arranged on one side of the active layer far away from the substrate base plate;
and the grid electrode is arranged on one side of the grid insulating layer, which is far away from the substrate base plate.
According to another aspect of the present disclosure, there is provided a method of manufacturing an array substrate, including:
providing a substrate base plate;
forming a first conductive layer on one side of the substrate base plate, the first conductive layer including a connection portion;
forming a protective material layer on one side of the first conducting layer, which is far away from the substrate base plate, and processing the protective material layer to form a protective layer;
forming an interlayer dielectric material layer on one side of the protective layer, which is far away from the substrate base plate, and carrying out patterning treatment on the interlayer dielectric material layer to form a second through hole, wherein the orthographic projection of the second through hole on the substrate base plate is overlapped with the orthographic projection of the protective layer on the substrate base plate;
patterning the protective layer to form a first via hole, wherein the first via hole is communicated to the connecting portion, and the second via hole is communicated with the first via hole;
and forming a second conducting layer on one side of the interlayer dielectric layer, which is far away from the substrate base plate, wherein the second conducting layer is connected with the connecting part through the first via hole and the second via hole.
In an exemplary embodiment of the present disclosure, the processing the protective material layer to form a protective layer includes:
and carrying out half exposure treatment on the protective material layer opposite to the connecting part, and carrying out full exposure treatment on the rest protective material layers, so that the exposed protective material layers form an isolation layer, and the unexposed protective material layers form the protective layer.
In an exemplary embodiment of the present disclosure, while the patterning process is performed on the interlayer dielectric material layer to form the second via hole, the preparation method further includes:
and patterning the isolation layer to form a third via hole, wherein the third via hole is communicated with the second via hole and the first via hole.
In an exemplary embodiment of the present disclosure, before patterning the protective layer to form the first via hole, the preparation method further includes:
and exposing the protective layer.
In an exemplary embodiment of the present disclosure, the patterning the protection layer to form the first via hole includes:
dry etching the protective layer with a mixture of a CF4 plasma and an O2 plasma forms a first via.
In an exemplary embodiment of the present disclosure, the material of the protective material layer is light-sensitive silicone, and the light-sensitive silicone forms silicon oxide after exposure.
In an exemplary embodiment of the present disclosure, the processing the protective material layer to form a protective layer further includes:
and developing the isolation layer to remove the isolation layer.
In an exemplary embodiment of the present disclosure, the patterning the protection layer to form the first via hole includes:
dry etching the protective layer with a mixture of an SF6 plasma and an O2 plasma forms a first via.
In an exemplary embodiment of the present disclosure, a material of the protective material layer is a light-sensitive silicone, and the light-sensitive silicone includes a silicone resin and a photosensitizer.
According to still another aspect of the present disclosure, there is provided a display device including: the array substrate as set forth in any one of the above.
According to the array substrate, a protective layer is arranged on one side, far away from the substrate, of the first conducting layer; on one hand, when the interlayer dielectric layer is etched to form the second via hole, the protective layer can protect the first conductive layer, so that the connecting part of the first conductive layer is prevented from being etched to generate poor etching, the connection between the connecting part and the second conductive layer is not influenced, and poor contact is not easy to generate; on the other hand, when the protective layer is etched to form the first via hole, the protective layer is thin, the etching amount is small, excessive etching cannot be generated, so that poor etching caused by etching of the connecting part of the first conducting layer cannot be generated, the connection of the connecting part and the second conducting layer cannot be influenced, and poor contact is not easy to generate; on the other hand, the protective layer has a flattening function, so that the segment difference of the film layer can be reduced, a relatively flat base surface is provided for the second conductive layer, and the formation and the conductive effect of the second conductive layer are facilitated; the array substrate can improve the display effect of the display panel.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic diagram showing the display effect of the display device when the thickness of the interlayer dielectric layer is 8000A m.
FIG. 2 is a schematic diagram showing the display effect of the display device when the thickness of the interlayer dielectric layer is 9000 angstroms.
FIG. 3 is a schematic diagram showing the display effect of the display device when the thickness of the interlayer dielectric layer is 12000 angstroms.
Fig. 4 is a schematic structural diagram of an exemplary embodiment of an array substrate according to the present disclosure.
Fig. 5 is a schematic structural diagram of another exemplary embodiment of an array substrate according to the present disclosure.
Fig. 6 is a schematic flow chart of an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure.
Fig. 7 to 13 are schematic structural diagrams of steps of an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure.
Fig. 14 to 17 are schematic structural views of steps of another exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure.
Description of reference numerals:
1. a substrate base plate; 2. a light-shielding layer; 3. a buffer layer;
4. a first conductive layer; 4a, an active layer; 41. a conductor part; 42. a channel portion; 43. a first data line; 44. a connecting portion;
5. a gate insulating layer; 6. a gate electrode;
7. a layer of protective material; 71. an isolation layer; 72. a protective layer; 73. a first via hole; 74. a third via hole;
8. an interlayer dielectric material layer; 81. an interlayer dielectric layer; 82. a second via hole;
9. a second conductive layer; 91. a source electrode; 92. a drain electrode; 93. a second data line;
10. a mask plate; 101. a semi-opaque region; 102. and (4) a full light-transmitting area.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
The inventor finds that: when the thicker insulating film layer is etched to form a via hole, a larger etching amount needs to be kept due to the difference of etching depths to achieve the etching amount of the via hole with the deepest etching depth, however, excessive etching is easily formed, the thicker the insulating film layer is, the larger the excessive etching is, the more serious the uneven etching is, the conductive layer at the via hole is easily etched to generate poor etching, the connection with the second conductive layer 9 is influenced to generate poor contact, and finally the display of the display device is influenced; referring to fig. 1-3, the display effect of the display device is schematically shown when the interlayer dielectric layers have different thicknesses, and therefore, the thicker the thickness of the insulating film layer, the less desirable the display effect.
The present disclosure example embodiments provide an array substrate, which may include a substrate 1, a first conductive layer 4, a protective layer 72, an interlayer dielectric layer 81, and a second conductive layer 9, as shown in fig. 3 and 4; the first conductive layer 4 is provided on one side of the base substrate 1, and includes a connection portion 44; the protective layer 72 is arranged on one side of the first conductive layer 4 away from the substrate base plate 1, a first through hole 73 is arranged on the protective layer 72, and the first through hole 73 is communicated to the connecting part 44; the interlayer dielectric layer 81 is arranged on one side, far away from the substrate base plate 1, of the protective layer 72, a second through hole 82 is formed in the interlayer dielectric layer 81, the second through hole 82 is communicated with the first through hole 73, and the orthographic projection of the second through hole 82 on the substrate base plate 1 is overlapped with the orthographic projection of the protective layer 72 on the substrate base plate 1; and a second conductive layer 9 provided on the interlayer dielectric layer 81 on a side away from the substrate base plate 1, the second conductive layer 9 being connected to the connection portion 44 through the first via 73 and the second via 82.
According to the array substrate, when the interlayer dielectric layer 81 is etched to form the second via 82, the protective layer 72 can protect the first conductive layer 4, so that poor etching caused by etching of the connecting part 44 of the first conductive layer 4 is avoided, connection between the connecting part 44 and the second conductive layer 9 is not affected, and poor contact is not easy to generate; when the protective layer 72 is etched to form the first via hole 73, because the protective layer 72 has a small thickness and a small etching amount, excessive etching is not generated, so that poor etching caused by etching the connection portion 44 of the first conductive layer 4 is avoided, connection between the connection portion 44 and the second conductive layer 9 is not affected, and poor contact is not easily generated; the protective layer 72 has a flattening function, so that the film segment difference can be reduced, a relatively flat base surface is provided for the second conductive layer 9, and the formation and the conductive effect of the second conductive layer 9 are facilitated; the array substrate can improve the display effect of the display panel.
In the present exemplary embodiment, the substrate base plate 1 may be a rigid base plate, for example, may be a glass base plate; the substrate 1 may be a flexible substrate, for example, a PI (polyimide) substrate.
A light-shielding layer 2 is provided on one side of the base substrate 1, and the light-shielding layer 2 may be made of metal. The orthographic projection of the thin film transistor on the substrate 1 is positioned in the orthographic projection of the light shielding layer 2 on the substrate 1. Light rays emitted from the substrate 1 can generate photon-generated carriers, so that the characteristics of the thin film transistor are greatly influenced, and the display image quality of the display device is finally influenced; the light shield layer 2 can shield light incident from the base substrate 1, thereby preventing the characteristics of the thin film transistor from being affected and preventing the display image quality of the display device from being affected.
A buffer layer 3 is disposed on a side of the light-shielding layer 2 away from the substrate 1, and the buffer layer 3 is made of an insulating material and can insulate and isolate the light-shielding layer 2 from the first conductive layer 4.
The first conductive layer 4 is disposed on a side of the buffer layer 3 away from the base substrate 1, the first conductive layer 4 may include an active layer 4a and a first data line 43, the active layer 4a may include a channel portion 42 and a conductor portion 41, and the conductor portion 41 is a connection portion 44. The conductor portion 41 may be provided in two, and the two conductor portions 41 may be provided on opposite sides of the channel portion 42. The material of the active layer 4a may be IGZO (Indium Gallium Zinc Oxide).
A portion of the first data line 43 is also the connection portion 44, and the first data line 43 may be formed with the gate electrode 6 and the gate line through a single patterning process.
A gate insulating layer 5 is arranged on the side of the first conductive layer 4 away from the substrate base plate 1, specifically, the gate insulating layer 5 is arranged on the side of the channel portion 42 away from the substrate base plate 1, the orthographic projection of the channel portion 42 on the substrate base plate 1 is positioned in the orthographic projection of the gate insulating layer 5 on the substrate base plate 1, or the orthographic projection of the channel portion 42 on the substrate base plate 1 is overlapped with the orthographic projection of the gate insulating layer 5 on the substrate base plate 1; that is, the gate insulating layer 5 covers at least the channel portion 42, but the gate insulating layer 5 may cover the entire array substrate.
A gate electrode 6 is arranged on the side of the gate insulating layer 5 away from the substrate base plate 1, and an orthographic projection of the gate electrode 6 on the substrate base plate 1 is positioned in the orthographic projection of the gate insulating layer 5 on the substrate base plate 1, or the orthographic projection of the gate electrode 6 on the substrate base plate 1 is overlapped with the orthographic projection of the gate insulating layer 5 on the substrate base plate 1. The channel portion 42 is insulated from the gate electrode 6 by the gate insulating layer 5.
Referring to fig. 4, a protective layer 72 is provided on a side of the first data line 43 away from the base substrate 1 and on a side of the conductor portion 41 away from the base substrate 1, and the protective layer 72 covers a portion of the first data line 43 and the conductor portion 41; the protective layer 72 is provided with a first via hole 73, and the first via hole 73 is communicated with the connecting portion 44, that is, the first via hole 73 is communicated with the first data line 43 and the conductor portion 41; the material of the protection layer 72 may be light-sensitive silicone, and the thickness thereof is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms. Of course, in other example embodiments of the present disclosure, the protective layer 72 may cover the entire array substrate.
Referring to fig. 5, in another open example embodiment of the present disclosure, an isolation layer 71 is disposed on a side of the protective layer 72 away from the substrate base plate 1, a third via 74 is disposed on the isolation layer 71, and the third via 74 is communicated with the second via 82 and the first via 73, that is, the third via 74 is communicated to the first data line 43 and the conductor portion 41 through the first via 73. In this exemplary embodiment, the material of the protective layer 72 and the material of the isolation layer 71 may be silicon oxide formed by exposing photosensitive silicone, but the protective layer 72 and the isolation layer 71 are not formed by the same exposure process, and as described in detail in the following preparation method, the thickness of the protective layer 72 is greater than or equal to 1000 angstroms and less than or equal to 6000 angstroms, for example, 3000 angstroms; the thickness of the isolation layer 71 is 3000 angstroms or more and 11000 angstroms or less.
Of course, in other exemplary embodiments of the present disclosure, in the case where the photosensitive silicone partially remains without being exposed or the silicon oxide is incompletely removed, the material of the protective layer 72 may be a mixture of two materials, i.e., the photosensitive silicone and the silicon oxide formed after the photosensitive silicone is exposed.
Referring to fig. 4, an interlayer dielectric layer 81 is disposed on a side of the protective layer 72 away from the substrate base plate 1, a second via 82 is disposed on the interlayer dielectric layer 81, and the second via 82 is communicated with the first via 73, that is, the second via 82 is communicated to the connecting portion 44 through the first via 73. The orthographic projection of the second via 82 on the substrate base plate 1 overlaps with the orthographic projection of the protective layer 72 on the substrate base plate 1, that is, the orthographic projection of the second via 82 on the substrate base plate 1 can be located in the orthographic projection of the protective layer 72 on the substrate base plate 1; alternatively, the orthographic projection of the second via 82 on the substrate base 1 may coincide or partially coincide with the orthographic projection of the protective layer 72 on the substrate base 1. The material of the interlayer dielectric layer 81 may be silicon oxide. Referring to fig. 5, an interlayer dielectric layer 81 is disposed on a side of the isolation layer 71 away from the base substrate 1. The structure of the interlayer dielectric layer 81 is the same as that shown in fig. 4, and is not described herein.
Referring to fig. 4 and 5, a second conductive layer 9 is disposed on a side of the interlayer dielectric layer 81 away from the substrate base plate 1, the second conductive layer 9 may include a source electrode 91, a drain electrode 92 and a second data line 93, and the source electrode 91 and the drain electrode 92 are correspondingly connected to the two conductor portions 41 through the second via 82 and the first via 73; the second data line 93 is connected with the source 91, and the second data line 93 is connected with the first data line 43 through the second via hole 82 and the first via hole 73 to form a data line, so that the data line forms a double-layer structure, the resistance of the data line can be reduced, and the display effect is improved; in addition, even when the first data line 43 or the second data line 93 is short-circuited, the display of the display panel is not affected.
The array substrate described above is a top gate array substrate; in other example embodiments of the present disclosure, the array substrate may also be a bottom gate type array substrate or a dual gate type array substrate. The first conductive layer 4 described above may include an active layer 4 a; in other example embodiments of the present disclosure, the first conductive layer 4 may further include a gate electrode 6, a source electrode 91 or a drain electrode 92, and the like.
Based on the same inventive concept, the disclosed example embodiments provide a method for manufacturing an array substrate, which may include the following steps, as shown in fig. 6:
in step S10, a substrate 1 is provided.
In step S20, a first conductive layer 4 is formed on one side of the base substrate 1, the first conductive layer 4 including the connection portion 44.
In step S30, a protective material layer 7 is formed on the first conductive layer 4 on the side away from the base substrate 1, and the protective material layer 7 is processed to form the protective layer 72.
Step S40 is to form the interlayer dielectric material layer 8 on the side of the protection layer 72 away from the substrate 1, and perform patterning process on the interlayer dielectric material layer 8 to form the second via 82, where an orthogonal projection of the second via 82 on the substrate 1 overlaps an orthogonal projection of the protection layer 72 on the substrate 1.
In step S50, the protective layer 72 is patterned to form a first via 73, the first via 73 is communicated to the connection portion 44, and the second via 82 is communicated with the first via 73.
In step S60, a second conductive layer 9 is formed on the interlayer dielectric layer 81 on the side away from the substrate base plate 1, and the second conductive layer 9 is connected to the connection portion 44 through the first via 73 and the second via 82.
According to the preparation method of the array substrate, when the interlayer dielectric layer 81 is etched to form the second via hole 82, the protective layer 72 can protect the first conductive layer 4, so that the connecting part 44 of the first conductive layer 4 is prevented from being etched to generate poor etching, the connection between the connecting part 44 and the second conductive layer 9 is not influenced, and poor contact is not easy to generate; when the protective layer 72 is etched to form the first via hole 73, because the protective layer 72 has a small thickness and a small etching amount, excessive etching cannot be generated, so that poor etching caused by etching of the connection portion 44 of the first conductive layer 4 cannot be generated, and connection between the connection portion 44 and the second conductive layer 9 cannot be influenced; the protective layer 72 has a flattening function, so that the film segment difference can be reduced, a relatively flat base surface is provided for the second conductive layer 9, and the formation and the conductive effect of the second conductive layer 9 are facilitated; the array substrate can improve the display effect of the display panel.
The respective steps of the method for manufacturing the array substrate will be described in detail below.
In step S10, a substrate 1 is provided.
In the present exemplary embodiment, referring to fig. 7, a substrate base plate 1 is provided, and the substrate base plate 1 may be a rigid base plate, for example, a glass base plate; the substrate 1 may be a flexible substrate, for example, a PI (polyimide) substrate.
A shading material layer is formed on one side of a substrate base plate 1 through processes of sputtering, evaporation, deposition and the like, patterning is carried out on the shading material layer to form a shading layer 2, the shading material layer can be made of metal, and the thickness of the shading layer 2 is about 1500 angstrom meters.
A buffer layer 3 is formed on the side of the light shielding layer 2 far away from the substrate 1 and the exposed substrate 1 through a coating process or a spin coating process, and the thickness of the buffer layer 3 is about 4000 angstroms.
Step S20 is to form a first conductive layer 4 on one side of the base substrate 1, where the first conductive layer 4 includes a connection portion 44.
In the present exemplary embodiment, as shown in fig. 7, an active material layer is formed on the buffer layer 3 on the side away from the base substrate 1 by sputtering, vapor deposition, or other processes, an active layer 4a is formed by patterning the active material layer, a conductor portion 41 is formed by conducting a partial region of the active layer 4a, and a channel portion 42 is formed as a region not conducting. One channel portion 42 is provided in one thin film transistor, and two conductor portions 41 are provided on opposite sides of the channel portion 42. The thickness of the active layer 4a is about 340 angstroms and both conductor portions 41 are connection portions 44.
A gate insulating material layer is formed on the side of the active layer 4a away from the substrate base plate 1 by a coating process or a spin coating process, and the gate insulating material layer is subjected to a patterning process to form the gate insulating layer 5, wherein an orthographic projection of the channel portion 42 on the substrate base plate 1 is positioned within an orthographic projection of the gate insulating layer 5 on the substrate base plate 1, or the orthographic projection of the channel portion 42 on the substrate base plate 1 is coincident with an orthographic projection of the gate insulating layer 5 on the substrate base plate 1. The thickness of the gate insulating layer 5 is approximately 1500 angstroms. Of course, in another example embodiment of the present disclosure, the gate insulating layer 5 may completely cover the entire array substrate.
A gate material layer is formed on one side of the gate insulating layer 5, which is far away from the substrate base plate 1, and on one side of the buffer layer 3, which is far away from the substrate base plate 1, through processes of sputtering, evaporation, deposition and the like, and patterning processing is performed on the gate material layer to form a first data line 43, a gate 6 and a gate line, namely, the first data line 43 is formed while the gate 6 is formed, the gate 6 is connected with the gate line, and the first data line 43 is not connected with the gate 6 and the gate line. A portion of the first data line 43 is also the connection portion 44. The orthographic projection of the grid electrode 6 on the substrate base plate 1 is positioned in the orthographic projection of the grid insulation layer 5 on the substrate base plate 1, or the orthographic projection of the grid insulation layer 5 on the substrate base plate 1 is superposed with the orthographic projection of the grid electrode 6 on the substrate base plate 1. The thickness of the gate 6 is approximately 8000 angstrom.
Step S30 is to form a protective material layer 7 on the side of the first conductive layer 4 away from the base substrate 1, and process the protective material layer 7 to form a protective layer 72.
In the present exemplary embodiment, referring to fig. 7, the protective material layer 7 is formed by a coating process or a spin coating process on the side of the gate electrode 6 away from the substrate 1 and the side of the conductor portion 41 away from the substrate 1, and the material of the protective material layer 7 may be a photosensitive silicone, for example, polymethylsiloxane or polydimethylsiloxane. The thickness of the protective material layer 7 is 4000 angstroms to 12000 angstroms. The protective material layer 7 made of the material has high preparation process efficiency and simple process. In order to increase the adhesion of the protective material layer 7 to the conductor portion 41, the protective material layer 7 may be subjected to oxygen plasma treatment or surface hydroxylation treatment.
Pre-curing treatment can be carried out on the protective material layer 7, wherein the curing temperature is 60-100 ℃, and the curing time is 20-120 s; of course, the curing temperature and curing time may be set according to device requirements.
Referring to fig. 8, arrows indicate light, a mask blank 10 is placed on the side of the protective material layer 7 away from the substrate board 1, and the mask blank 10 may include a plurality of full-light-transmitting regions 102 and a plurality of semi-light-transmitting regions 101, an orthographic projection of the semi-light-transmitting regions 101 on the substrate board 1 coincides with an orthographic projection of the connecting portions 44 on the substrate board 1, and an orthographic projection of the full-light-transmitting regions 102 on the substrate board 1 coincides with an orthographic projection of the rest portions on the substrate board 1. The orthographic projection of the connecting portion 44 on the substrate 1 may be located within the orthographic projection of the semi-transparent region 101 on the substrate 1. Then, the protective material layer 7 is irradiated with ultraviolet light, that is, the protective material layer 7 is exposed. The protective material layer 7 opposite to the full light transmission region 102 is completely changed to form an isolation layer 71, and the isolation layer 71 is made of silicon oxide (SiOx); the portion of the protective material layer 7 opposite to the semi-light-transmitting region 101, which is far from the substrate 1, is changed to form an isolation layer 71, the material of the isolation layer 71 is silicon oxide (SiOx), the portion close to the substrate 1 is unchanged to form a protective layer 72, and the material of the protective layer 72 may be light-sensitive silicone. So that the orthographic projection of the connecting portion 44 on the base substrate 1 is located within the orthographic projection of the protective layer 72 on the base substrate 1, or the orthographic projection of the connecting portion 44 on the base substrate 1 coincides with the orthographic projection of the protective layer 72 on the base substrate 1. Finally, the mask plate 10 is removed to form the structure shown in fig. 9.
Of course, in other exemplary embodiments of the present disclosure, the orthographic projection of the second via 82 on the substrate base 1 overlaps with the orthographic projection of the protective layer 72 on the substrate base 1, so that the protective layer 72 can protect the connection portion.
In another example embodiment of the present disclosure, referring to fig. 14, the isolation layer 71 may be developed to remove the isolation layer 71, and only the protection layer 72 of the isolation layer 71 on the side close to the substrate base plate 1 remains. The material of the protective material layer 7 in this example embodiment may be a mixture of a silicone resin and a photosensitizer, that is, the light-sensitive silicone includes a silicone resin and a photosensitizer, and the silicone resin and the photosensitizer can be removed together by development after exposure.
Step S40, forming an interlayer dielectric material layer 8 on a side of the protective layer 72 away from the substrate base plate 1, and performing patterning processing on the interlayer dielectric material layer 8 to form a second via 82, where an orthographic projection of the second via 82 on the substrate base plate 1 overlaps an orthographic projection of the protective layer 72 on the substrate base plate 1.
In the present exemplary embodiment, referring to fig. 10, the interlayer dielectric material layer 8 is formed on the side of the isolation layer 71 away from the substrate 1 by a coating process or a spin coating process, and the material of the interlayer dielectric material layer 8 may be silicon oxide (SiOx). The thickness of the interlayer dielectric material layer 8 is approximately 9000 angstroms.
And forming photoresist on the side of the interlayer dielectric material layer 8 far away from the substrate base plate 1 through a coating process, and exposing and developing the photoresist to remove the photoresist at the position where the second via hole 82 is formed. Referring to fig. 11, the second via 82 and the interlayer dielectric layer 81 are formed by dry etching the interlayer dielectric material layer 8, which may use a mixture of CF4 plasma and O2 plasma. The orthographic projection of the second via 82 on the substrate base plate 1 overlaps with the orthographic projection of the protective layer 72 on the substrate base plate 1, so that the protective layer 72 can protect the connecting part 44 when the second via 82 is formed.
The isolation layer 71 is etched while the interlayer dielectric material layer 8 is dry etched, so that a third via 74 is formed on the isolation layer 71, and the third via 74 is communicated with the second via 82.
Since the etching selection of the interlayer dielectric material layer 8 and the protective layer 72 is relatively large, for example, greater than 10; therefore, the protective layer 72 cannot be etched by this etching, so that the connection portion 44 of the first conductive layer 4 cannot be etched, and the connection portion 44 of the first conductive layer 4 is effectively protected, thereby preventing the connection portion 44 from being over-etched.
In another example embodiment of the present disclosure, referring to fig. 15, since the isolation layer 71 has been removed by development, the interlayer dielectric material layer 8 is formed by a coating process or a spin coating process on the side of the protection layer 72 away from the base substrate 1. Referring to fig. 16, since the etching selectivity of the interlayer dielectric material layer 8 and the protection layer 72 is relatively large, for example, greater than 10; therefore, only the interlayer dielectric material layer 8 is dry-etched during the etching to form the second via 82 and the interlayer dielectric layer 81. The dry etching may use a mixture of CF4 plasma and O2 plasma. When the interlayer dielectric material layer 8 is subjected to dry etching, the protective layer 72 cannot be etched, so that the connecting portion 44 of the first conductive layer 4 cannot be etched, the connecting portion 44 of the first conductive layer 4 is effectively protected, and the connecting portion 44 is prevented from being over-etched.
In step S50, the protective layer 72 is patterned to form first vias 73.
In the present exemplary embodiment, as shown in fig. 12, the arrows indicate light rays, and the resist 72 is exposed, and the entire exposure may be performed without providing the mask plate 10 in this exposure. The material of the protective layer 72 is changed from photosensitive silicone to silicon oxide, that is, the material of the protective layer 72 is changed to the same material as the isolation layer 71.
Referring to fig. 13, the protective layer 72 is dry etched to form a first via hole 73, and the first via hole 73 is communicated to the connection portion 44. The dry etching may use a mixture of CF4 plasma and O2 plasma.
In another example embodiment of the present disclosure, referring to fig. 17, the protective layer 72 may be dry etched directly using a mixture of SF6 plasma and O2 plasma without exposing the protective layer 72.
Since the thickness of the protective layer 72 is small, the etching amount is small, and excessive etching is not generated, so that poor etching due to etching of the connection portion 44 of the first conductive layer 4 is not generated, connection between the connection portion 44 and the second conductive layer 9 is not affected, and poor contact is not easily generated.
Step S60 is to form a second conductive layer 9 on a side of the interlayer dielectric layer 81 away from the substrate base plate 1, wherein the second conductive layer 9 is connected to the connection portion 44 through the first via 73 and the second via 82.
Referring to fig. 4 and 5, a second conductive material layer is formed on one side of the interlayer dielectric layer 81 away from the substrate base plate 1 by sputtering, evaporation, deposition and other processes, and is etched to form a second conductive layer 9, where the second conductive layer 9 may include a source electrode 91, a drain electrode 92, a second data line 93 and the like, and the second data line 93 is connected to the source electrode 91; the source and drain electrodes 91 and 92 are connected to the two connection portions 44 through the first via 73 and the first via 73, respectively, and the second data line 93 is connected to the first data line 43 through the first via 73 and the first via 73 to form a data line.
It is to be understood that the functions of the "source" and the "drain" may be interchanged in the case of using thin film transistors of opposite polarities, the case where the direction of current flow during circuit operation is changed, or the like. Therefore, in this specification, "source" and "drain" may be interchanged with each other.
The above-described method for manufacturing an array substrate is a method for manufacturing a top gate array substrate; in other example embodiments of the present disclosure, the array substrate may also be a bottom gate type array substrate or a dual gate type array substrate, and the preparation method thereof is not described herein again. The first conductive layer 4 described above may include an active layer 4 a; in other example embodiments of the present disclosure, the first conductive layer 4 may further include the gate electrode 6, the source electrode 91, the drain electrode 92, or the like, and the protection layer 72 may be formed on the gate electrode 6, the source electrode 91, the drain electrode 92, or the like to protect the gate electrode 6, the source electrode 91, the drain electrode 92, or the like. The thicknesses of the respective layers are merely examples and can be adjusted as necessary.
It should be noted that although the steps of the method for manufacturing the array substrate in the present disclosure are depicted in the drawings in a specific order, this does not require or imply that the steps must be performed in this specific order or that all of the depicted steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Based on the same inventive concept, example embodiments of the present disclosure provide a display device, which may include the array substrate of any one of the above. The specific structure of the array substrate has been described in detail above, and therefore, the detailed description thereof is omitted.
The specific type of the display device is not particularly limited, and any type of display device commonly used in the art may be used, such as a liquid crystal display panel, an OLED display panel; specifically, the display device may also be a mobile device such as a mobile phone, a wearable device such as a watch, a VR device, and the like, and those skilled in the art may select the display device according to the specific application, which is not described herein again.
It should be noted that the display device includes other necessary components and compositions besides the array substrate, taking a liquid crystal display panel as an example, and may further include a liquid crystal layer, a color film substrate, a backlight module, and the like; taking the OLED display panel as an example, the OLED display panel may further include an anode, a light emitting layer, a cathode, a cover plate, and the like; taking the display as an example, specifically, such as a housing, a circuit board, a power line, etc., those skilled in the art can supplement the display according to the specific requirements of the display, and the details are not repeated herein.
Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiment of the present invention are the same as those of the array substrate provided by the above exemplary embodiment, and are not repeated herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims (15)

1. An array substrate, comprising:
a substrate base plate;
a first conductive layer provided on one side of the substrate base, the first conductive layer including a connection portion;
the protective layer is arranged on one side, far away from the substrate base plate, of the first conducting layer, and a first through hole is formed in the protective layer and communicated to the connecting portion;
the interlayer dielectric layer is arranged on one side, far away from the substrate base plate, of the protective layer, a second through hole is formed in the interlayer dielectric layer and communicated with the first through hole, and the orthographic projection of the second through hole on the substrate base plate is overlapped with the orthographic projection of the protective layer on the substrate base plate;
the second conducting layer is arranged on one side, far away from the substrate base plate, of the interlayer dielectric layer and is connected with the connecting part through the first via hole and the second via hole.
2. The array substrate of claim 1, wherein the material of the protection layer is one or two of a photo-sensitive silicone and a silicon oxide formed by exposing the photo-sensitive silicone.
3. The array substrate of claim 1, further comprising:
the isolation layer is arranged between the protective layer and the interlayer dielectric layer, a third through hole is formed in the isolation layer, and the third through hole is communicated with the second through hole and the first through hole.
4. The array substrate of claim 1, wherein the first conductive layer comprises:
an active layer including a channel portion and a conductor portion, the conductor portion being the connection portion;
a first data line, a portion of the first data line being the connection portion.
5. The array substrate of claim 4, further comprising:
a light-shielding layer disposed between the substrate and the active layer;
a buffer layer disposed between the light-shielding layer and the active layer;
the gate insulating layer is arranged on one side of the active layer far away from the substrate base plate;
and the grid electrode is arranged on one side of the grid insulating layer, which is far away from the substrate base plate.
6. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate base plate;
forming a first conductive layer on one side of the substrate base plate, the first conductive layer including a connection portion;
forming a protective material layer on one side of the first conducting layer, which is far away from the substrate base plate, and processing the protective material layer to form a protective layer;
forming an interlayer dielectric material layer on one side of the protective layer, which is far away from the substrate base plate, and carrying out patterning treatment on the interlayer dielectric material layer to form a second through hole, wherein the orthographic projection of the second through hole on the substrate base plate is overlapped with the orthographic projection of the protective layer on the substrate base plate;
patterning the protective layer to form a first via hole, wherein the first via hole is communicated to the connecting portion, and the second via hole is communicated with the first via hole;
and forming a second conducting layer on one side of the interlayer dielectric layer, which is far away from the substrate base plate, wherein the second conducting layer is connected with the connecting part through the first via hole and the second via hole.
7. The method for preparing the array substrate according to claim 6, wherein the processing the protective material layer to form a protective layer comprises:
and carrying out half exposure treatment on the protective material layer opposite to the connecting part, and carrying out full exposure treatment on the rest protective material layers, so that the exposed protective material layers form an isolation layer, and the unexposed protective material layers form the protective layer.
8. The method for manufacturing the array substrate according to claim 7, wherein the patterning process is performed on the interlayer dielectric material layer to form the second via hole, and the method further comprises:
and patterning the isolation layer to form a third via hole, wherein the third via hole is communicated with the second via hole and the first via hole.
9. The method for preparing the array substrate according to claim 8, wherein before patterning the protective layer to form the first via hole, the method further comprises:
and exposing the protective layer.
10. The method for preparing the array substrate according to claim 9, wherein the patterning the protective layer to form the first via hole comprises:
dry etching the protective layer with a mixture of a CF4 plasma and an O2 plasma forms a first via.
11. The method of any one of claims 8 to 10, wherein the material of the protective material layer is a photosensitive silicone, and the photosensitive silicone forms silicon oxide after exposure.
12. The method for manufacturing the array substrate according to claim 7, wherein the processing the protective material layer to form a protective layer further comprises:
and developing the isolation layer to remove the isolation layer.
13. The method for preparing the array substrate according to claim 12, wherein the patterning the protective layer to form the first via hole comprises:
dry etching the protective layer with a mixture of an SF6 plasma and an O2 plasma forms a first via.
14. The method of claim 12 or 13, wherein the material of the protective material layer is a photosensitive silicone, and the photosensitive silicone includes a silicone resin and a photosensitizer.
15. A display device, comprising: the array substrate according to any one of claims 1 to 5.
CN202111318605.1A 2021-11-09 2021-11-09 Array substrate, preparation method thereof and display device Pending CN114038863A (en)

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Publication Number Publication Date
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