CN114038815A - Flip chip ball grid array packaging structure and chip heat dissipation performance optimization method - Google Patents
Flip chip ball grid array packaging structure and chip heat dissipation performance optimization method Download PDFInfo
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- CN114038815A CN114038815A CN202111207809.8A CN202111207809A CN114038815A CN 114038815 A CN114038815 A CN 114038815A CN 202111207809 A CN202111207809 A CN 202111207809A CN 114038815 A CN114038815 A CN 114038815A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
Abstract
The application relates to the technical field of semiconductors, and discloses a flip chip ball grid array packaging structure and a chip heat dissipation performance optimization method, wherein the packaging structure directly integrates a heat dissipation structure on a packaging shell, so that the maintenance of connection between a radiator and the packaging shell is omitted, the thermal resistance caused by the extra thickness of a radiator substrate is omitted, the heat dissipation performance is further improved, and when the flip chip ball grid array packaging structure is used for a low-power-consumption chip, the heat dissipation can be realized by depending on the heat dissipation structure of the flip chip ball grid array packaging structure; the method is used for optimizing the heat dissipation performance of the flip chip ball grid array packaging structure with the fin heat dissipation structure, the number of the heat dissipation fins, the spacing between the heat dissipation fins and the height of the heat dissipation fins are used as optimization parameters, a corresponding heat transfer model is established, and the parameter optimization value is determined through the heat dissipation effect of the heat transfer model corresponding to different optimization parameter values, so that the optimization design of the flip chip ball grid array packaging structure parameters is realized, and the heat dissipation performance optimization of the heat dissipation structure can be realized under the condition that the size requirement of the packaging structure is met.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a flip chip ball grid array packaging structure and a chip heat dissipation performance optimization method.
Background
A Flip Chip Ball Grid Array (FCBGA) is a semiconductor package having a die disposed on one side of a substrate and a ball grid array disposed on the other side of the substrate that mounts the FCBGA on a printed circuit board. The die heats up during operation and heat needs to be dissipated from the die to a fluid medium, such as air, to ensure proper operation of the FCBGA.
It is common to attach a heat spreader to the package housing of a Flip Chip Ball Grid Array (FCBGA) to dissipate heat from the die, and the gap between the heat spreader and the package housing is filled with silicone gel as a heat-dissipating conductive agent. In the heat dissipation mode, the radiator and the packaging shell are connected through the silica gel, the combination of the radiator and the packaging shell is not tight, the silica gel needs to be regularly and again filled, the maintenance is troublesome, and the heat transfer thermal resistance is additionally increased due to the fact that the substrate of the radiator has a certain thickness.
Content of application
Therefore, an object of the embodiments of the present application is to provide a flip chip ball grid array package structure and a method for optimizing heat dissipation performance of a chip, which can solve the problems of troublesome connection and maintenance between a heat sink and a package housing and large heat transfer resistance in the conventional flip chip ball grid array package structure.
In order to achieve the purpose, the technical scheme is as follows:
the application provides a flip chip ball grid array packaging structure in a first aspect, which comprises a substrate, a wafer and a packaging shell, wherein the packaging shell is arranged on the substrate to form a cavity with the substrate, the wafer is positioned in the cavity, and one side end of the wafer is connected with the substrate; the packaging shell comprises a main body part which is arranged as a heat dissipation structure, and the main body part is connected with the other side end of the wafer through a thermal interface material layer.
According to one enabling aspect of the first aspect of the invention, the body portion comprises:
a first connection portion having a bottom surface connected to the thermal interface material layer;
a heat-dissipating fin group including a plurality of heat-dissipating fins vertically extending from a top surface of the first connecting portion and arranged at intervals in a lateral direction.
According to one possible mode of the first aspect of the present invention, the main body portion includes a second connection portion, a bottom surface of the second connection portion is connected to the thermal interface material layer, and a coolant passage is provided in the second connection portion.
According to one possible implementation of the first aspect of the invention, the package housing further includes a support portion extending along a periphery of the main body portion, and a bottom of the support portion is connected to the substrate.
According to one implementation manner of the first aspect of the present invention, the thermal interface material layer is silicone grease, silicone rubber, phase change material, heat conducting glue, or a heat dissipation pad.
The invention provides a method for optimizing the heat dissipation performance of a chip, which is used for optimizing the heat dissipation performance of a flip chip ball grid array packaging structure, the flip chip ball grid array packaging structure comprises a substrate, a wafer and a packaging shell, the packaging shell is arranged on the substrate and forms a cavity with the substrate, the wafer is positioned in the cavity, and one side end of the wafer is connected with the substrate; the package shell comprises a main body part which is arranged into a heat dissipation structure, the main body part is connected with the other side end of the wafer through a thermal interface material layer, the main body part comprises a first connecting part and a heat dissipation fin group, the bottom surface of the first connecting part is connected with the thermal interface material layer, and the heat dissipation fin group comprises a plurality of heat dissipation fins which vertically extend from the top surface of the first connecting part and are arranged at intervals along the transverse direction; the method comprises the following steps:
dividing factors influencing the heat dissipation performance of the flip chip ball grid array packaging structure into parameters to be optimized and other factors, wherein the parameters to be optimized comprise the number of heat dissipation fins, the spacing of the heat dissipation fins and the height of the heat dissipation fins;
establishing a heat transfer model of the flip chip ball grid array packaging structure, keeping the other factors unchanged, setting the number of the radiating fins in the heat transfer model to be corresponding to an initial design value, changing the spacing and the height of the radiating fins within the range of the design value to obtain wafer temperature field simulation results corresponding to different spacing and heights of the radiating fins, and obtaining the spacing and the height of the radiating fins which enable the radiating performance to be optimal according to the wafer temperature field simulation results, namely obtaining the optimal value of the spacing and the optimal value of the height of the radiating fins;
and if the highest temperature displayed by the wafer temperature field simulation results corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is not higher than the rated design temperature, outputting the corresponding initial design values of the optimal value of the spacing of the radiating fins, the optimal value of the height of the radiating fins and the number of the radiating fins.
According to an implementable manner of the second aspect of the invention, the method further comprises:
if the highest temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing between the heat dissipation fins and the optimal value of the height of the heat dissipation fins is higher than the rated design temperature, keeping the rest factors unchanged, setting the spacing between the heat dissipation fins in the heat transfer model to be the optimal value of the spacing between the heat dissipation fins, keeping the height of the heat dissipation fins to be the optimal value of the height of the heat dissipation fins, gradually increasing the number of the heat dissipation fins in the heat transfer model until the highest temperature displayed by the corresponding obtained wafer temperature field simulation result is not higher than the rated design temperature or the number of the heat dissipation fins is increased to the maximum value in the range corresponding to the design value, and outputting the current number of the heat dissipation fins.
According to a manner that can be realized by the second aspect of the present invention, the gradually increasing the number of the heat dissipation fins in the heat transfer model includes:
calculating the difference between the maximum temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins and the rated design temperature;
and when the difference is not less than the preset difference threshold, gradually increasing the number of the radiating fins from a reference value of the number of the radiating fins, wherein the reference value is greater than the initial design value of the number of the radiating fins.
According to a manner enabled by the second aspect of the present invention, the reference value of the number of the heat radiating fins is determined according to the following formula:
wherein S represents a parameter adjustment ratio, TmaxThe maximum temperature T displayed by the simulation result of the wafer temperature field corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is representedCRepresenting the nominal design temperature, DTRepresenting said preset difference threshold, SminAnd representing the number of the radiating fins corresponding to an initial design value.
A third aspect of the present application provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed, the method for optimizing the chip heat dissipation performance according to any one of the above embodiments is implemented.
Compared with the prior art, the application has at least the following beneficial technical effects:
the flip chip ball grid array packaging structure provided by the embodiment of the application directly integrates the heat dissipation structure on the packaging shell of the Flip Chip Ball Grid Array (FCBGA), so that the maintenance of the connection between a heat radiator and the packaging shell is omitted, and the original welding relation between a CPU and a PCB is not influenced; the packaging structure enables a heat source to be in direct contact with the main body part, thermal resistance caused by the thickness of an extra radiator substrate is omitted, the heat dissipation performance is further improved, and when the packaging structure is used for a low-power-consumption chip, the heat dissipation can be realized by depending on a self heat dissipation structure without additionally adding a radiator; according to the method for optimizing the heat dissipation performance of the chip, the number of the heat dissipation fins, the distance between the heat dissipation fins and the height of the heat dissipation fins are used as optimization parameters, the corresponding heat transfer model is established, the parameter optimization value is determined according to the heat dissipation effect of the heat transfer model corresponding to different optimization parameter values, the optimal design of the flip chip ball grid array packaging structure parameters is achieved, and the heat dissipation performance optimization of the heat dissipation structure can be achieved under the condition that the size requirement of the packaging structure is met.
Drawings
FIG. 1 is a schematic structural view of an alternative embodiment of a flip chip ball grid array package structure provided herein;
FIG. 2 is a schematic structural view of another alternate embodiment of a flip chip ball grid array package structure provided herein;
fig. 3 is a schematic flowchart of an alternative embodiment of a method for optimizing chip heat dissipation performance according to the present application.
Reference numerals:
1. a substrate; 2. a wafer; 3. a package housing; 4. a layer of thermal interface material; 5. tin balls; 31. a body portion; 32. a support portion; 311. a first connecting portion; 312. a set of heat dissipating fins; 313. a second connecting portion; 314. a coolant channel.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
As shown in fig. 1 and fig. 2, the present application provides a flip chip ball grid array package structure, which includes a substrate 1, a die 2 and a package housing 3, wherein the package housing 3 is disposed on the substrate 1 to form a cavity with the substrate 1, the die 2 is located in the cavity, and one side end of the die is connected to the substrate 1; the package housing 3 includes a main body portion 31 configured as a heat dissipation structure, and the main body portion 31 is connected to the other side end of the die 2 through the thermal interface material layer 4 to dissipate heat of the die 2 conducted from the thermal interface material layer 4.
Wherein, the bottom of the substrate 1 is also connected with a plurality of solder balls 5.
In the embodiment of the application, the heat dissipation structure is directly integrated on the packaging shell 3 of the ball grid array (FCBGA) of the flip chip, so that the maintenance of the connection between a heat radiator and the packaging shell 3 is omitted, and the original welding relation between a CPU and a PCB is not influenced; the packaging structure enables a heat source to be in direct contact with the main body part 31, thermal resistance caused by the thickness of the extra radiator substrate 1 is omitted, heat dissipation performance is further improved, and when the packaging structure is used for a low-power-consumption chip, the extra radiator is not needed, and heat dissipation can be achieved by the aid of the self heat dissipation structure.
The thermal interface material layer 4 may be a phase change material or a thermal conductive adhesive. Wherein the package housing 3 further comprises a support portion 32 extending along the periphery of the main body portion 31, and the bottom of the support portion 32 is connected to the substrate 1.
As an alternative embodiment, the main body portion 31 is a middle portion of the package housing 3, and the supporting portion 32 is a side portion of the package housing 3, as shown in fig. 1 and 2. The connection between the supporting portion 32 of the package housing 3 and the substrate 1 may be a fixed connection manner such as welding or gluing, or a detachable connection manner such as magnetic connection or sliding connection.
In one embodiment, the main body 31 is made of a heat dissipation material and has a plate-like structure, so that the heat of the die 2 is conducted to the main body 31 through the thermal interface material layer 4 and dissipated to the outside through the main body 31.
In another embodiment, as shown in fig. 1, the body portion 31 includes:
a first connection portion 311, a bottom surface of the second connection portion 313 being connected to the thermal interface material layer 4;
a fin group 312 including a plurality of fins extending vertically from the top surface of the first connection portion 311 and arranged at intervals in the lateral direction.
In the present embodiment, the main body 31 is a heat dissipation fin structure, so that the heat of the die 2 is conducted to the first connection portion 311 through the thermal interface material layer 4, and is dissipated through the heat dissipation fin group 312.
In another embodiment, as shown in fig. 2, the main body 31 includes a second connection portion 313, a bottom surface of the second connection portion 313 is connected to the thermal interface material layer 4, a cooling fluid channel 314 is provided in the second connection portion 313, and a cooling fluid flows in from an inlet of the cooling fluid channel 314 and flows out from an outlet of the cooling fluid channel 314, so as to remove heat of the die 2 conducted from the thermal interface material layer 4.
The application also provides a method for optimizing the heat dissipation performance of a flip chip ball grid array packaging structure, which is shown in fig. 1 and comprises a substrate 1, a wafer 2 and a packaging shell 3, wherein the packaging shell 3 is arranged on the substrate 1 to form a cavity with the substrate 1, the wafer 2 is positioned in the cavity, and one side end of the wafer is connected with the substrate 1; the package housing 3 includes a main body portion 31 configured as a heat dissipation structure, the main body portion 31 is connected to the other side end of the die 2 through a thermal interface material layer 4, the main body portion 31 includes a first connection portion 311 and a heat dissipation fin group 312, a bottom surface of the first connection portion 311 is connected to the thermal interface material layer 4, and the heat dissipation fin group 312 includes a plurality of heat dissipation fins extending vertically from a top surface of the first connection portion 311 and disposed at intervals in a transverse direction.
As shown in fig. 3, the method includes:
s1: dividing factors influencing the heat dissipation performance of the flip chip ball grid array packaging structure into parameters to be optimized and other factors, wherein the parameters to be optimized comprise the number of heat dissipation fins, the spacing of the heat dissipation fins and the height of the heat dissipation fins;
s2: establishing a heat transfer model of the flip chip ball grid array packaging structure, keeping the other factors unchanged, setting the number of the radiating fins in the heat transfer model to be corresponding to an initial design value, changing the spacing and the height of the radiating fins within the range of the design value to obtain wafer temperature field simulation results corresponding to different spacing and heights of the radiating fins, and obtaining the spacing and the height of the radiating fins which enable the radiating performance to be optimal according to the wafer temperature field simulation results, namely obtaining the optimal value of the spacing and the optimal value of the height of the radiating fins;
s3: and if the highest temperature displayed by the wafer temperature field simulation results corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is not higher than the rated design temperature, outputting the corresponding initial design values of the optimal value of the spacing of the radiating fins, the optimal value of the height of the radiating fins and the number of the radiating fins.
The embodiment of the application realizes the optimal design of the flip chip ball grid array packaging structure parameters, and can realize the optimization of the heat dissipation performance of the heat dissipation structure under the condition of meeting the size requirement of the packaging structure.
The method for evaluating the heat dissipation performance comprises the following steps: and evaluating that the heat dissipation performance is good if the maximum temperature and the average temperature are low according to the maximum temperature and the average temperature displayed by the wafer temperature field simulation result, otherwise, evaluating that the heat dissipation performance is poor.
The design value range of each parameter to be optimized can be preset, and one design value is selected from the design value ranges corresponding to the number of the radiating fins to serve as a corresponding initial design value. Preferably, the minimum value in the corresponding design value range is selected as the initial design value corresponding to the number of the heat dissipation fins.
When the design value range of each parameter to be optimized is set, the maximum value of the spacing of the radiating fins can be determined according to the length of the first connecting part and the number of the radiating fins, and the maximum value of the height of the radiating fins can be determined according to the size requirement, the cost and the like of the packaging structure.
In step S2, the thermal analysis software is used to perform numerical simulation on the temperature field and the surrounding flow field of the heat transfer model with the adjusted parameters to be optimized, so as to obtain a wafer temperature field simulation result. The thermal analysis software may be any one of ANSYS, Icepak, FloTHERM, and FloEFD.
In order to obtain wafer temperature field simulation results corresponding to different cooling fin pitches and cooling fin heights, the following adjustment steps can be adopted:
s21: fixing the spacing of the radiating fins to be a corresponding initial design value, and changing the heights of the radiating fins within the range of the design value to obtain wafer temperature field simulation results corresponding to different heights of the radiating fins at the current spacing of the radiating fins;
s22: increasing the spacing of the radiating fins within a design value range, keeping the increased spacing of the radiating fins unchanged, and changing the heights of the radiating fins within the design value range to obtain wafer temperature field simulation results corresponding to different heights of the radiating fins under the current spacing of the radiating fins;
s23: step S22 is repeated until the fin pitch cannot be increased any more.
Wherein, the mode of increasing the radiating fin interval can be: the fin pitch is increased by every 0 of the fin pitch minimum. 5 times the increase is made for one gear. The present embodiment is not limited thereto.
In some embodiments, the method further comprises:
if the highest temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing between the heat dissipation fins and the optimal value of the height of the heat dissipation fins is higher than the rated design temperature, keeping the rest factors unchanged, setting the spacing between the heat dissipation fins in the heat transfer model to be the optimal value of the spacing between the heat dissipation fins, keeping the height of the heat dissipation fins to be the optimal value of the height of the heat dissipation fins, gradually increasing the number of the heat dissipation fins in the heat transfer model until the highest temperature displayed by the corresponding obtained wafer temperature field simulation result is not higher than the rated design temperature or the number of the heat dissipation fins is increased to the maximum value in the range corresponding to the design value, and outputting the current number of the heat dissipation fins.
When the parameter optimization scheme corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins cannot meet the radiating requirement, the embodiment of the invention further realizes the optimization of the radiating performance by a method for adjusting the number of the radiating fins. According to the embodiment of the invention, the minimum number of the radiating fins capable of realizing the radiating performance requirement can be obtained under the condition of meeting the size requirement of the packaging structure, and the material cost is favorably saved.
In some embodiments, said gradually increasing the number of fins in said heat transfer pattern comprises:
calculating the difference between the maximum temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins and the rated design temperature;
and when the difference is not less than the preset difference threshold, gradually increasing the number of the radiating fins from a reference value of the number of the radiating fins, wherein the reference value is greater than the initial design value of the number of the radiating fins.
The reference value of the number of the radiating fins is determined according to the following formula:
wherein S represents a parameter adjustment ratio, TmaxThe maximum temperature T displayed by the simulation result of the wafer temperature field corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is representedCRepresenting the nominal design temperature, DTRepresenting said preset difference threshold, SminAnd representing the number of the radiating fins corresponding to an initial design value.
According to the embodiment of the invention, the initial value of the quantity adjustment of the radiating fins is determined according to the difference condition of the maximum temperature and the rated design temperature, so that the efficiency of parameter optimization can be improved.
The present application also provides a computer readable storage medium having a computer program stored therein, which when executed implements a flip chip ball grid array package structure as described in any of the above embodiments.
It should be noted that the computer program includes computer program code, which may be in a source code form, an object code form, an executable file or some intermediate form, and so on. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations are also regarded as the protection scope of the present application.
Claims (10)
1. A flip chip ball grid array packaging structure is characterized in that the packaging structure comprises a substrate, a wafer and a packaging shell, wherein the packaging shell is arranged on the substrate to form a cavity with the substrate, the wafer is positioned in the cavity, and one side end of the wafer is connected with the substrate; the packaging shell comprises a main body part which is arranged as a heat dissipation structure, and the main body part is connected with the other side end of the wafer through a thermal interface material layer.
2. The flip chip ball grid array package structure of claim 1, wherein the body portion comprises:
a first connection portion having a bottom surface connected to the thermal interface material layer;
a heat-dissipating fin group including a plurality of heat-dissipating fins vertically extending from a top surface of the first connecting portion and arranged at intervals in a lateral direction.
3. The flip chip ball grid array package structure of claim 1, wherein said body portion includes a second connecting portion, a bottom surface of said second connecting portion being connected to said layer of thermal interface material, said second connecting portion having a coolant channel therein.
4. The flip chip ball grid array package structure of claim 1, wherein the package housing further comprises a support portion extending along a periphery of the body portion, a bottom portion of the support portion being connected to the substrate.
5. The flip chip ball grid array package structure of any one of claims 1-4, wherein the thermal interface material layer is a thermal conductive glue.
6. A method for optimizing the heat dissipation performance of a chip, the method for improving the heat dissipation performance of the flip chip ball grid array package structure of claim 2, the method comprising:
dividing factors influencing the heat dissipation performance into parameters to be optimized and other factors, wherein the parameters to be optimized comprise the number of the heat dissipation fins, the distance between the heat dissipation fins and the height of the heat dissipation fins;
establishing a heat transfer model of the flip chip ball grid array packaging structure, keeping the other factors unchanged, setting the number of the radiating fins in the heat transfer model to be corresponding to an initial design value, changing the spacing and the height of the radiating fins within the range of the design value to obtain wafer temperature field simulation results corresponding to different spacing and heights of the radiating fins, and obtaining the spacing and the height of the radiating fins which enable the radiating performance to be optimal according to the wafer temperature field simulation results, namely obtaining the optimal value of the spacing and the optimal value of the height of the radiating fins;
and if the highest temperature displayed by the wafer temperature field simulation results corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is not higher than the rated design temperature, outputting the corresponding initial design values of the optimal value of the spacing of the radiating fins, the optimal value of the height of the radiating fins and the number of the radiating fins.
7. The method for optimizing the heat dissipation performance of the chip according to claim 6, further comprising:
if the highest temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing between the heat dissipation fins and the optimal value of the height of the heat dissipation fins is higher than the rated design temperature, keeping the rest factors unchanged, setting the spacing between the heat dissipation fins in the heat transfer model to be the optimal value of the spacing between the heat dissipation fins, keeping the height of the heat dissipation fins to be the optimal value of the height of the heat dissipation fins, gradually increasing the number of the heat dissipation fins in the heat transfer model until the highest temperature displayed by the corresponding obtained wafer temperature field simulation result is not higher than the rated design temperature or the number of the heat dissipation fins is increased to the maximum value in the range corresponding to the design value, and outputting the current number of the heat dissipation fins.
8. The chip heat dissipation performance optimization method according to claim 7, wherein the gradually increasing the number of heat dissipation fins in the heat transfer model includes:
calculating the difference between the maximum temperature displayed by the wafer temperature field simulation result corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins and the rated design temperature;
and when the difference is not less than the preset difference threshold, gradually increasing the number of the radiating fins from a reference value of the number of the radiating fins, wherein the reference value is greater than the initial design value of the number of the radiating fins.
9. The chip heat dissipation performance optimization method according to claim 8, wherein the reference value for the number of the heat dissipation fins is determined according to the following formula:
wherein S represents a parameter adjustment ratio, TmaxThe maximum temperature T displayed by the simulation result of the wafer temperature field corresponding to the optimal value of the spacing of the radiating fins and the optimal value of the height of the radiating fins is representedCRepresenting the nominal design temperature, DTRepresenting said preset difference threshold, SminAnd representing the number of the radiating fins corresponding to an initial design value.
10. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when executed, the computer program implements the method for optimizing heat dissipation performance of a multi-chip structure according to any one of claims 6 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111207809.8A CN114038815A (en) | 2021-10-15 | 2021-10-15 | Flip chip ball grid array packaging structure and chip heat dissipation performance optimization method |
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| CN202111207809.8A CN114038815A (en) | 2021-10-15 | 2021-10-15 | Flip chip ball grid array packaging structure and chip heat dissipation performance optimization method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952764A (en) * | 2023-03-10 | 2023-04-11 | 成都明夷电子科技有限公司 | Transistor circuit for improving heat dissipation performance of amplifier chip and optimization method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952764A (en) * | 2023-03-10 | 2023-04-11 | 成都明夷电子科技有限公司 | Transistor circuit for improving heat dissipation performance of amplifier chip and optimization method |
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