CN114024643A - Accurate control method and system for execution time of each function in ATE (automatic test equipment) - Google Patents
Accurate control method and system for execution time of each function in ATE (automatic test equipment) Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0682—Clock or time synchronisation in a network by delay compensation, e.g. by compensation of propagation delay or variations thereof, by ranging
Abstract
The invention provides a method and a system for accurately controlling execution time of each function in ATE (automatic test equipment), wherein the method comprises the following steps: acquiring a synchronous clock and a synchronous trigger signal related to a certain function; in the first delay unit, counting is started by taking the clock period of the synchronous clock as a unit, and when the count value is equal to a preset first delay parameter, an enabling signal of the function is turned on or off so as to realize integral period delay of the enabling signal of the function; selecting the number of the sub-chains of the delay carry chain according to the second delay parameter, and performing micro-period delay adjustment on the starting time and the closing time of the function enabling signal to realize micro-period delay of the function enabling signal; and obtaining an enabling control signal to realize accurate control on the execution time of the function. The scheme of the invention combines the integer period delay and the micro period delay, realizes the accurate delay control of the execution time, can control the time accuracy within dozens of picoseconds, and can meet the test requirement of a high-precision chip.
Description
Technical Field
The invention relates to the field of semiconductor chip testing, in particular to a method and a system for accurately controlling execution time of each function in ATE (automatic test equipment).
Background
Ate (automatic Test equipment) is an automatic Test device, which is an aggregate of high-performance computer-controlled Test instruments, and is a Test system composed of a tester and a computer, and the computer controls Test hardware by running instructions of a tester program. Semiconductor ATE is used to test the integrity of the function and performance of an integrated circuit, and is an important device for ensuring the quality of the integrated circuit in the production and manufacturing process of the integrated circuit.
In the test execution process, the time for executing each function needs to be strictly controlled. For example, after the function a is executed, the function B is executed within a preset time, which is a relative time when the function a and the function B are executed, requiring precise control. In the prior art, the execution time control of each function in the ATE test equipment has the following disadvantages:
1. the absolute execution time of each function is not accurate, and the execution is opened and closed by the software of the main control board, so that the test requirement of a high-precision chip cannot be met
2. The relative execution time between each function is not accurately controlled, the functions are opened and closed through software, the operation progress is in a delicate level, and the test requirement of a high-precision chip cannot be met
The traditional execution time control scheme mainly depends on register implementation, and the time precision can be controlled only in microsecond level. And the high-precision chip needs time precision control in a nanosecond level or even dozens of picoseconds. The traditional ATE equipment is difficult to meet the testing requirement of a high-precision chip in the aspect of execution time control.
Therefore, there is a need for a solution to the above problem, which is related to the precise control of the execution time of each function of ATE equipment.
Disclosure of Invention
In view of this, the present invention provides a method and a system for accurately controlling execution time of each function in ATE equipment, and the specific scheme is as follows:
the method is applied to an FPGA of a service board, the FPGA comprises a plurality of function control logics, each function control logic comprises an enabling generation unit, and the enabling generation unit comprises a first delay unit and a second delay unit;
the method comprises the following steps:
acquiring a synchronous clock and a synchronous trigger signal related to a certain function, and inputting the synchronous clock and the synchronous trigger signal into the first delay unit;
in the first delay unit, a preset counter starts counting by taking a clock period of the synchronous clock as a unit after receiving a synchronous trigger signal of the function, and when a count value of the counter is equal to a preset first delay parameter, an enable signal of the function is turned on or off to realize integer period delay of the enable signal of the function;
in the second delay unit, a delay carry chain formed by connecting a plurality of sub-chains in series is configured, the number of the sub-chains of the delay carry chain is selected according to a preset second delay parameter, and on the basis of an enable signal generated by the first delay unit, the on-time and the off-time of the function enable signal are subjected to micro-period delay adjustment so as to realize micro-period delay of the function enable signal;
and taking the enabling signal after the integer period delay and the micro period delay as an enabling control signal of the function, and controlling the opening time and the closing time of the function through the enabling control signal so as to realize the accurate control of the execution time of the function.
In a specific embodiment, the obtaining process of the integer period delay specifically includes:
setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter;
inputting the count value of the counter into a preset comparator for comparison:
when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function;
and when the count value is equal to the first closing delay parameter, closing the enabling signal of the function.
In a specific embodiment, the process of acquiring the micro-period delay specifically includes:
setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter;
the preset output selector selects the number of the sub-chains of the delay carry chain according to the second starting delay parameter to obtain a second enabling starting delay time related to the starting time of the function enabling signal, and selects the number of the sub-chains of the delay carry chain according to the second closing delay parameter to obtain a second enabling closing delay time related to the closing time of the function enabling signal;
on the basis of the enable signal generated by the first delay unit, after the second enable starting delay time duration continues to be delayed, the enable signal of the function is started;
and on the basis of the enable signal generated by the first delay unit, after the second enable closing delay time duration is delayed continuously, the enable signal of the function is closed.
In a specific embodiment, when the number of the sub-chains is the largest, the delay duration of the delay carry chain is the longest, and the delay duration is greater than the clock period of the synchronous clock.
In a specific embodiment, after the counter receives the synchronous trigger signal, the counter starts counting by taking the synchronous clock period as a unit from zero;
and when the count value of the counter is greater than the first closing delay parameter, stopping counting by the counter and clearing the counter.
In a specific embodiment, in the delay carry chain, the delay duration corresponding to each sub-chain is the same;
and/or the delay time duration corresponding to each sub-chain is 31.25 picoseconds.
In a specific embodiment, the function control logic further includes a parameter configuration unit and an analog circuit control unit;
configuring the first delay parameter and the second delay parameter through the functional parameter configuration unit;
after the enabling generation unit generates an enabling control signal of a certain function, the enabling control signal controls the analog circuit control unit, so that the on-time and the off-time of the function are indirectly and accurately controlled.
An accurate control system for execution time of each function in ATE equipment is applied to an FPGA of a service board, wherein the FPGA comprises a plurality of function control logics;
the accurate control system includes:
the signal acquisition unit is used for acquiring a synchronous clock and a synchronous trigger signal related to a certain function aiming at function enabling control in each function control logic and inputting the synchronous clock and the synchronous trigger signal into a preset first delay unit;
the first time delay unit starts counting by taking the clock period of the synchronous clock as a unit after a preset counter receives the synchronous trigger signal of the function, and starts or closes the enabling signal of the function when the count value of the counter is equal to a preset first time delay parameter so as to realize the integral period time delay of the enabling signal of the function;
the second delay unit comprises a selector, an output selection controller and a delay carry chain formed by connecting a plurality of sub-chains in series, and is used for performing micro-period delay adjustment on the starting time and the closing time of the function enabling signal on the basis of the enabling signal generated by the first delay unit so as to realize the micro-period delay of the function enabling signal;
the output selection controller is used for selecting the number of the sub-chains of the delay carry chain according to a second delay parameter;
the selector is used for selecting a proper output link according to the control of the output selection controller;
a signal generation unit: and the control circuit is used for taking the enable signal after the integer period delay and the micro period delay as an enable control signal of the function, and controlling the opening time and the closing time of the function through the enable control signal, thereby realizing the accurate control of the execution time of the function.
In a specific embodiment, the first delay unit specifically includes:
setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter;
inputting the count value of the counter into a preset comparator for comparison:
when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function;
and when the count value is equal to the first closing delay parameter, closing the enabling signal of the function.
In a specific embodiment, the second delay unit specifically includes:
setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter;
the preset output selector selects the number of the sub-chains of the delay carry chain according to the second starting delay parameter to obtain a second enabling starting delay time related to the starting time of the function enabling signal, and selects the number of the sub-chains of the delay carry chain according to the second closing delay parameter to obtain a second enabling closing delay time related to the closing time of the function enabling signal;
on the basis of the enable signal generated by the first delay unit, after the second enable starting delay time duration continues to be delayed, the enable signal of the function is started;
and on the basis of the enable signal generated by the first delay unit, after the second enable closing delay time duration is delayed continuously, the enable signal of the function is closed.
Has the advantages that: the invention provides a method and a system for accurately controlling execution time of each function in ATE equipment, which combine integer period delay and micro period delay to realize accurate delay control of the execution time, the time accuracy can be controlled within dozens of picoseconds, and the test requirement of a high-precision chip can be met. In the integral period delay part, a counter and a comparator are utilized to accurately turn on and off delay at corresponding time, and large-span delay with a clock period as a unit is realized. In the micro-period delay part, the delay time length of the delay carry chain is selected according to the configured delay parameters by means of the delay carry chain, so that the small-span delay with the sub-chain as the unit is realized, and the time precision is up to tens of picoseconds. The ATE equipment has clock synchronization and trigger synchronization, so that clock periods are kept consistent in all service boards, and all function control logics synchronously receive trigger signals. The clock synchronization and the trigger synchronization can realize the accurate control of the absolute execution time, and on the basis, the accurate control of the relative execution time of each function is realized.
Drawings
FIG. 1 is a schematic flow chart illustrating a precise control method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a service board structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a complete flow of function enable control according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a clock synchronization scheme according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a trigger synchronization scheme according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a parameter configuration scheme according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an enable generation unit according to an embodiment of the present invention;
FIG. 8 is a timing diagram illustrating an accurate enable control according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an accurate control system according to an embodiment of the present invention.
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Reference numerals: 1-a signal acquisition unit; 2-a first delay unit; 3-a second delay unit; 4-a signal generation unit; 21-a counter; 22-a comparator; 31-a selector; 32-an output selection controller; 33-time delay carry chain.
Detailed Description
Hereinafter, various embodiments of the present disclosure will be described more fully. The present disclosure is capable of various embodiments and of modifications and variations therein. However, it should be understood that: there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather, the disclosure is to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the present disclosure.
The terminology used in the various embodiments of the disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the various embodiments of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of the disclosure belong. The terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein in various embodiments.
Example 1
The embodiment 1 of the invention discloses a method for accurately controlling execution time of each function in ATE (automatic test equipment), which accurately controls the execution time of the function within tens of picoseconds. The flow block diagram of the upgrading method is shown in the attached figure 1, and the specific scheme is as follows:
an accurate control method for execution time of each function in ATE equipment is suitable for the ATE equipment comprising a main control board, a back board and a service board. Each service board FPGA is configured with a plurality of function control logics, as shown in fig. 2 in the specification. And the function control logic sends a trigger signal to a function analog circuit on the chip to be tested to realize the execution of related functions.
In each function control logic, the configuration includes a parameter configuration unit, an enable generation unit, and an analog circuit control unit. And configuring relevant parameters, such as a first delay parameter, a second delay parameter and the like, in each function control logic through the parameter configuration unit. The enabling generation unit is responsible for generating a function enabling signal and sending the function enabling signal to the analog circuit control unit. The enable generation unit includes a first delay unit and a second delay unit. The analog circuit control unit sends the enabling signal of the related function to the functional analog circuit of the chip to be tested for execution, and the execution of the corresponding function is realized.
In practical application, one service board FPGA may correspond to control of a plurality of functions. Each function is provided with a function control logic circuit. Assuming that function a, function B and function C exist, the execution time of function a, function B and function C can be precisely controlled by the function control logic circuit on the FPGA.
A method for accurately controlling execution time of each function in ATE equipment comprises the following steps:
101. acquiring a synchronous clock and a synchronous trigger signal related to a certain function, and inputting the synchronous clock and the synchronous trigger signal into a preset first delay unit;
102. in the first delay unit, a preset counter starts counting by taking a clock period of a synchronous clock as a unit after receiving a synchronous trigger signal of the function, and when the count value of the counter is equal to a preset first delay parameter, an enable signal of the function is turned on or off so as to realize integer period delay of the enable signal of the function;
103. in the second delay unit, a delay carry chain formed by connecting a plurality of sub-chains in series is configured, the number of the sub-chains of the delay carry chain is selected according to a preset second delay parameter, and on the basis of an enabling signal generated by the first delay unit, the on-time and the off-time of the function enabling signal are subjected to micro-period delay adjustment so as to realize micro-period delay of the function enabling signal;
104. and taking the enabling signal after the integral period delay and the micro period delay as an enabling control signal of the function, and controlling the opening time and the closing time of the function through the enabling control signal, thereby realizing the accurate control of the execution time of the function.
In this embodiment, the function execution time is accurately delayed by setting the integer period delay and the micro period delay, so as to realize accurate control of each function execution time of the ATE device.
It should be noted that, with the accurate control method provided in this embodiment, it is necessary to ensure that clocks of all the service boards are synchronized and triggered synchronously, so that accurate control of execution time of each function can be achieved through accurate delay control. The clock synchronization and the trigger synchronization can realize the accurate control of the absolute execution time of each function, and then the accurate control of the relative execution time of each function is carried out on the basis. The complete execution time precise control process needs to be sequentially executed through configuring service parameters of each function, configuring delay parameters of each function, configuring a trigger selection register, sending a synchronous trigger signal, generating a function enabling signal according to the switch delay parameters, and executing each function according to the enabling control. The flow is shown in the attached figure 3 of the specification.
Therefore, before step 101, the method further comprises: and configuring service parameters of each function, and acquiring the execution time of each function to determine the corresponding delay time. Configuring each function delay parameter, and configuring a first delay parameter and a second delay parameter through a parameter configuration unit. And configuring a trigger selection register, and enabling each functional logic to synchronously receive the synchronous trigger signal through the trigger selection register.
Clock synchronization requires that clocks of each service board card have the same frequency and the same direction. The embodiment provides a clock synchronization scheme, clocks of all service board FPGAs are from the same constant temperature crystal oscillator on the main control board, and hardware wiring is strictly equal in length, so that the same frequency and the same phase of receiving clocks of all service board FPGAs are guaranteed. The main control board is provided with an adjustable delay clock buffer, and the adjustable delay clock buffer is controlled by the MCU. The delay compensation synchronization can be carried out on the tiny errors of the PCB wiring through the delay clock buffer. The specific structure is shown in figure 4 in the specification.
The trigger synchronization requires that each service board receives a trigger signal at the same time. The embodiment provides a synchronous triggering scheme, and fan-out selectors are arranged on a main control board and each service board. The structure of the main control board is as shown in the attached figure 5 of the specification, and a plurality of triggers are configured on the FPGA to realize synchronous fan-out of the trigger signals from the main control board. The structure of the service board is shown in the figure 2 in the specification, and the triggering selection circuit synchronously fans out the triggering signal to each service board. Because all service function synchronous trigger signals of all service board FPGAs are from the main control board FPGA, and the hardware wiring delay is strictly equal, the trigger signals received by all service board FPGAs are ensured to be strictly synchronous.
In addition, this embodiment also provides a parameter configuration scheme, in which a communication switching logic is set in the main control board FPGA to implement uniform configuration of parameters. The concrete structure is shown in figure 6 in the specification.
The execution time of the function can be accurately controlled based on clock synchronization and trigger synchronization. The synchronous clock in this embodiment refers to a clock in which the main control board and all the service boards are completely consistent after configuration, and clock cycles of the synchronous clocks are consistent in the whole ATE device. And the synchronous trigger signal is the FPGA of which the trigger signal synchronously reaches each service board.
The structure of the enable generation unit is shown in figure 7 in the specification.
In the first delay unit, a counter and a comparator are included. A synchronous trigger signal of a certain function is input into a counter, and the counter starts counting by taking the clock period of a synchronous clock as a unit. Every clock cycle, the counter increases a value, and the count value of the counter corresponds to the clock cycle. When the synchronous trigger signal starts to trigger, the counter starts to count. When the synchronous trigger signal is triggered, the counter is triggered, and the count value is cleared. The first opening delay parameter and the second opening delay parameter can be configured through the parameter configuration unit and input into the comparator.
The integer period delay obtaining process specifically includes: setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter; the count value of the counter is input into a preset comparator for comparison: when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function; and when the counting value is equal to the first closing delay parameter, closing the enabling signal of the function.
Each integer cycle delay is an integer number of clock cycles, and the time precision of the integer cycle delay is the clock cycle of the synchronous clock. The first delay unit can realize the large-span delay of the execution time, and the comparator can skillfully realize the large-span delay taking the clock period as a unit.
The second delay unit comprises a delay carry chain, a selector and an output selection controller, and the structural schematic diagram is shown in the specification and the attached figure 7. The delay carry chain is composed of a plurality of sub-chains which are sequentially connected in series, a branch circuit is led out in front of each sub-chain and connected with a selector, the number of the sub-chains corresponding to each branch circuit is different, and any branch circuit can be output through selection. The parameter configuration unit configures a second delay parameter to the output selection controller, and the output selection controller controls which branch is used by the selector for output.
The process of acquiring the micro-period delay specifically comprises the following steps: setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter; the preset output selector selects the number of the sub-chains of the delay carry chain according to the second starting delay parameter to obtain a second enabling starting delay time related to the starting time of the function enabling signal, and selects the number of the sub-chains of the delay carry chain according to the second closing delay parameter to obtain a second enabling closing delay time related to the closing time of the function enabling signal; on the basis of the enable signal generated by the first delay unit, the enable signal of the function is started after the second enable starting delay time duration is delayed continuously; and on the basis of the enable signal generated by the first delay unit, the enable signal of the function is closed after the second enable closing delay time length is delayed continuously.
The second enabling starting delay time length and the second enabling closing delay time length are time periods, and the backward delay is continued on the basis of the integral cycle delay. Due to the fact that the precision of the micro-period delay is high, the requirement of the ATE equipment for the precision of the execution time can be met.
In the description fig. 8, a timing diagram of the fine enable control is provided. Exemplary waveforms of the synchronous clock and the synchronous trigger signal are shown in fig. 8. After the start of trigger selection, when the synchronous trigger signal starts to trigger, the counter starts to count, and each count value corresponds to a clock period of the synchronous clock. And when the synchronous trigger signal is triggered, the counter stops counting and is cleared. All count values of the counter correspond to one complete cycle of the synchronization trigger signal. In fig. 8, the first on delay parameter is 5 and the first off delay parameter is 16. When the count value equals 5, the function-enabled integer period delay begins. When the count value equals 16, the function-enabled integer period delay ends. One complete integer cycle delay corresponds to 11 clock cycles.
And the micro-period is delayed to be started at the starting time of the integral period delay, and the micro-period delay is continued on the basis of the integral period delay. When the count value is equal to 5, the integer cycle delay starts, and the delay carry chain continues to delay backward for a period of time based on the time.
Preferably, the maximum delay duration of the delay-and-carry chain is greater than the clock period of the synchronous clock. And delaying the maximum delay time of the carry chain, namely selecting the branch in which all the sub chains are connected in series, wherein the maximum delay time corresponds to the branch with the largest number of the sub chains. In the delay carry chain, the delay time length corresponding to each sub-chain is the same. Further preferably, the delay time duration corresponding to each sub-chain is 31.25 picoseconds, and the second enabling opening delay time duration and the second enabling closing delay time duration are both integral multiples of 31.25 picoseconds. 31.25 picoseconds is the highest precision that can be realized by the function execution time, and can meet the time precision requirement of any high-precision chip.
After micro-period delay, a function enabling signal is generated according to the synchronous trigger signal and is sent to the analog circuit control unit.
The embodiment provides an accurate control method for execution time of each function in ATE equipment, which combines integer cycle delay and micro cycle delay to realize accurate delay control of execution time and has high time accuracy. In the integral period delay part, a counter and a comparator are utilized to accurately turn on and off delay at corresponding time, and large-span delay with a clock period as a unit is realized. In the micro-period delay part, the delay time length of the delay carry chain is selected according to the configured delay parameters by means of the delay carry chain, so that the small-span delay with the sub-chain as the unit is realized, and the time precision is up to tens of picoseconds. The ATE equipment has clock synchronization and trigger synchronization, so that clock periods are kept consistent in all service boards, and all function control logics synchronously receive trigger signals.
Example 2
The embodiment 2 of the present invention discloses an accurate control system for execution time of each function in ATE equipment, the accurate control method of the embodiment 1 is systematized, the specific structure of the system is as shown in the attached figure 4 of the specification, and the specific scheme is as follows:
an accurate control system for execution time of each function in ATE equipment is applied to an FPGA of a service board, wherein the FPGA comprises a plurality of function control logics, and the structures of the function control logics are shown in the attached drawing of the specification.
The accurate control system includes:
the signal acquisition unit 1 is used for acquiring a synchronous clock and a synchronous trigger signal related to a certain function aiming at function enabling control in each function control logic, and inputting the synchronous clock and the synchronous trigger signal into a preset first delay unit 2;
the first delay unit 2 comprises a counter 21 and a comparator 22, the counter 21 starts counting by taking the clock period of the synchronous clock as a unit, and when the count value of the counter 21 is equal to a preset first delay parameter, the enable signal of the function is turned on or off so as to realize the integer period delay of the enable signal of the function;
the second delay unit 3 comprises a selector 31, an output selection controller 32 and a delay carry chain 33 formed by connecting a plurality of sub-chains in series, and is used for performing micro-period delay adjustment on the starting time and the closing time of the function enabling signal on the basis of the enabling signal generated by the first delay unit so as to realize the micro-period delay of the function enabling signal;
an output selection controller 32, configured to select the number of sub-chains of the delay carry chain 33 according to the second delay parameter;
a selector 31 for selecting an appropriate output link according to the control of the output selection controller 32;
the signal generation unit 4: the control device is used for taking the enable signal after integer period delay and micro period delay as the enable control signal of the function, and controlling the opening time and closing time of the function through the enable control signal, so that the accurate control of the execution time of the function is realized.
The first delay unit 2 specifically includes: setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter; the count value of the counter 21 is input to the comparator 22 for comparison: when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function; and when the counting value is equal to the first closing delay parameter, closing the enabling signal of the function.
The second delay unit 3 specifically includes: setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter; the preset output selector 32 selects the number of the sub-chains of the delay carry chain 33 according to the second start delay parameter to obtain a second enable start delay time length related to the start time of the function enable signal, and selects the number of the sub-chains of the delay carry chain 33 according to the second close delay parameter to obtain a second enable close delay time length related to the close time of the function enable signal; on the basis of the enable signal generated by the first delay unit, the enable signal of the function is started after the second enable starting delay time duration is delayed continuously; and on the basis of the enable signal generated by the first delay unit, the enable signal of the function is closed after the second enable closing delay time length is delayed continuously.
This embodiment discloses an accurate control system for execution time of each function in ATE equipment, which systematizes the accurate control method of embodiment 1 to make it more practical.
The invention provides a method and a system for accurately controlling execution time of each function in ATE (automatic test equipment), which combine integer period delay and micro period delay to realize accurate delay control of the execution time and have high time precision. In the integral period delay part, a counter and a comparator are utilized to accurately turn on and off delay at corresponding time, and large-span delay with a clock period as a unit is realized. In the micro-period delay part, the delay time length of the delay carry chain is selected according to the configured delay parameters by means of the delay carry chain, so that the small-span delay with the sub-chain as the unit is realized, and the time precision is up to tens of picoseconds. The ATE equipment has clock synchronization and trigger synchronization, so that clock periods are kept consistent in all service boards, and all function control logics synchronously receive trigger signals.
Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present invention. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned invention numbers are merely for description and do not represent the merits of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present invention, however, the present invention is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present invention.
Claims (10)
1. The method for accurately controlling the execution time of each function in ATE equipment is characterized by being applied to an FPGA of a service board, wherein the FPGA comprises a plurality of function control logics, each function control logic comprises an enabling generation unit, and the enabling generation unit comprises a first delay unit and a second delay unit;
the method comprises the following steps:
acquiring a synchronous clock and a synchronous trigger signal related to a certain function, and inputting the synchronous clock and the synchronous trigger signal into the first delay unit;
in the first delay unit, a preset counter starts counting by taking a clock period of the synchronous clock as a unit after receiving a synchronous trigger signal of the function, and when a count value of the counter is equal to a preset first delay parameter, an enable signal of the function is turned on or off to realize integer period delay of the enable signal of the function;
in the second delay unit, a delay carry chain formed by connecting a plurality of sub-chains in series is configured, the number of the sub-chains of the delay carry chain is selected according to a preset second delay parameter, and on the basis of an enable signal generated by the first delay unit, the on-time and the off-time of the function enable signal are subjected to micro-period delay adjustment so as to realize micro-period delay of the function enable signal;
and taking the enabling signal after the integer period delay and the micro period delay as an enabling control signal of the function, and controlling the opening time and the closing time of the function through the enabling control signal so as to realize the accurate control of the execution time of the function.
2. The accurate control method according to claim 1, wherein the integer period delay obtaining process specifically includes:
setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter;
inputting the count value of the counter into a preset comparator for comparison:
when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function;
and when the count value is equal to the first closing delay parameter, closing the enabling signal of the function.
3. The accurate control method according to claim 2, wherein the acquiring process of the micro-period delay specifically comprises:
setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter;
the preset output selector selects the number of the sub-chains of the delay carry chain according to the second starting delay parameter to obtain a second enabling starting delay time related to the starting time of the function enabling signal, and selects the number of the sub-chains of the delay carry chain according to the second closing delay parameter to obtain a second enabling closing delay time related to the closing time of the function enabling signal;
on the basis of the enable signal generated by the first delay unit, after the second enable starting delay time duration continues to be delayed, the enable signal of the function is started;
and on the basis of the enable signal generated by the first delay unit, after the second enable closing delay time duration is delayed continuously, the enable signal of the function is closed.
4. The accurate control method according to claim 1, wherein when the number of the sub-chains is the largest, the delay time duration of the delay carry chain is the longest and is greater than the clock period of the synchronous clock.
5. The accurate control method according to claim 2, wherein after the counter receives the synchronous trigger signal, the counter starts counting in units of the synchronous clock period from zero;
and when the count value of the counter is greater than the first closing delay parameter, stopping counting by the counter and clearing the counter.
6. The accurate control method according to claim 1, wherein the delay duration corresponding to each sub-chain in the delay carry chain is the same;
and/or the delay time duration corresponding to each sub-chain is 31.25 picoseconds.
7. The accurate control method according to claim 3, characterized in that the function control logic further comprises a parameter configuration unit and an analog circuit control unit;
configuring the first delay parameter and the second delay parameter through the functional parameter configuration unit;
after the enabling generation unit generates an enabling control signal of a certain function, the enabling control signal controls the analog circuit control unit, so that the on-time and the off-time of the function are indirectly and accurately controlled.
8. The accurate control system for execution time of each function in ATE equipment is characterized by being applied to an FPGA of a service board, wherein the FPGA comprises a plurality of function control logics;
the accurate control system includes:
the signal acquisition unit is used for acquiring a synchronous clock and a synchronous trigger signal related to a certain function aiming at function enabling control in each function control logic and inputting the synchronous clock and the synchronous trigger signal into a preset first delay unit;
the first time delay unit starts counting by taking the clock period of the synchronous clock as a unit after a preset counter receives the synchronous trigger signal of the function, and starts or closes the enabling signal of the function when the count value of the counter is equal to a preset first time delay parameter so as to realize the integral period time delay of the enabling signal of the function;
the second delay unit comprises a selector, an output selection controller and a delay carry chain formed by connecting a plurality of sub-chains in series, and is used for performing micro-period delay adjustment on the starting time and the closing time of the function enabling signal on the basis of the enabling signal generated by the first delay unit so as to realize the micro-period delay of the function enabling signal;
the output selection controller is used for selecting the number of the sub-chains of the delay carry chain according to a second delay parameter;
the selector is used for selecting a proper output link according to the control of the output selection controller;
a signal generation unit: and the control circuit is used for taking the enable signal after the integer period delay and the micro period delay as an enable control signal of the function, and controlling the opening time and the closing time of the function through the enable control signal, thereby realizing the accurate control of the execution time of the function.
9. The accurate control system according to claim 8, wherein the first delay unit specifically comprises:
setting a first delay parameter, wherein the first delay parameter comprises a first opening delay parameter and a first closing delay parameter;
inputting the count value of the counter into a preset comparator for comparison:
when the counting value is equal to the first starting delay parameter, starting an enabling signal of the function;
and when the count value is equal to the first closing delay parameter, closing the enabling signal of the function.
10. The accurate control system according to claim 9, wherein the second delay unit specifically comprises:
setting a second delay parameter, wherein the second delay parameter comprises a second starting delay parameter and a second closing delay parameter;
the preset output selector selects the number of the sub-chains of the delay carry chain according to the second starting delay parameter to obtain a second enabling starting delay time related to the starting time of the function enabling signal, and selects the number of the sub-chains of the delay carry chain according to the second closing delay parameter to obtain a second enabling closing delay time related to the closing time of the function enabling signal;
on the basis of the enable signal generated by the first delay unit, after the second enable starting delay time duration continues to be delayed, the enable signal of the function is started;
and on the basis of the enable signal generated by the first delay unit, after the second enable closing delay time duration is delayed continuously, the enable signal of the function is closed.
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