CN114023256B

CN114023256B - Display panel, pixel circuit and display device

Info

Publication number: CN114023256B
Application number: CN202111211998.6A
Authority: CN
Inventors: 王宏宇; 魏现鹤; 孙光远; 孙大卫; 蔡明瀚
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2021-10-18
Filing date: 2021-10-18
Publication date: 2023-06-13
Anticipated expiration: 2041-10-18
Also published as: CN114023256A

Abstract

The application discloses a display panel, a pixel circuit and a display device. The display panel comprises a plurality of pixel units, each pixel unit comprises a plurality of color sub-pixels, each sub-pixel comprises a pixel circuit and a light-emitting element, each pixel circuit comprises an enabling module, each enabling module and each light-emitting element are connected in series between a first voltage end and a second voltage end, at least one color sub-pixel is a target sub-pixel, each target sub-pixel further comprises a first capacitor, and each first capacitor and each light-emitting element of each target sub-pixel are connected in series between each enabling module and each second voltage end. According to the embodiment of the application, the color cast problem during display of the display panel can be solved, and the display effect is improved.

Description

Display panel, pixel circuit and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel, a pixel circuit and a display device.

Background

Organic light emitting diode (Organic Light Emitting Diode, OLED) display panels can realize flexible display and large-area full-color display, and are known as the display devices with the most development potential in the industry.

However, the inventors of the present application found that the OLED display panel may have a color shift phenomenon during low-luminance display, and have a problem of poor display effect.

Disclosure of Invention

The application provides a display panel, pixel circuit and display device, simple structure can solve the color cast problem when OLED display panel shows, improves the display effect.

In a first aspect, an embodiment of the present application provides a display panel, including a plurality of pixel units, the pixel units include sub-pixels of multiple colors, the sub-pixels include a pixel circuit and a light emitting element, the pixel circuit includes an enabling module, the enabling module and the light emitting element are connected in series between a first voltage terminal and a second voltage terminal, the sub-pixel of at least one color is a target sub-pixel, the target sub-pixel further includes a first capacitor, and the first capacitor and the light emitting element of the target sub-pixel are connected in series between the enabling module and the second voltage terminal.

In a possible implementation manner of the first aspect, the light emitting element of the target subpixel includes a first electrode, a light emitting layer, and a second electrode that are stacked, where the first electrode is electrically connected to the first voltage terminal through the enabling module, and the second electrode is electrically connected to the second voltage terminal;

the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the enabling module, and the first electrode is multiplexed into at least one polar plate of the first capacitor;

And/or the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the second voltage end, and the second electrode is multiplexed into at least one polar plate of the first capacitor.

In a possible implementation manner of the first aspect, the first electrode includes at least two sub-film layers that are stacked, and one sub-film layer of any two adjacent sub-film layers is multiplexed into one plate of the first capacitor, and the other sub-film layer is multiplexed into the other plate of the first capacitor.

In a possible implementation manner of the first aspect, a dielectric layer is disposed between two plates of the first capacitor;

the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the enabling module, and the material of the dielectric layer comprises a hole-transport material;

in the case where the first capacitor is electrically connected between the light emitting element of the target subpixel and the second voltage terminal, the material of the dielectric layer includes an electron transporting material.

In a possible implementation manner of the first aspect, the display panel includes a substrate, and a dielectric layer is disposed between two plates of the first capacitor;

the front projection of the dielectric layer on the substrate overlaps with the front projection of the light-emitting layer on the substrate, an insulating layer is arranged between the two multiplexed sub-film layers, the insulating layer surrounds the dielectric layer, and the surface of the insulating layer, which is back to the substrate, is leveled with the surface of the dielectric layer, which is back to the substrate;

Preferably, the front projection of the dielectric layer onto the substrate overlaps the front projection of the light-emitting layer onto the substrate.

In a possible implementation manner of the first aspect, the thickness of the insulating layer is the same as the thickness of the dielectric layer;

preferably, the thickness of the insulating layer and the thickness of the dielectric layer are in the range of 1 nm to 10 nm.

In a possible implementation manner of the first aspect, the first capacitor is connected in series between the enabling module and the light emitting element of the target sub-pixel, and the light emitting element of the target sub-pixel includes a first electrode, a light emitting layer and a second electrode that are stacked;

the display panel further comprises a driving device layer, the enabling module and the first capacitor are arranged on the driving device layer, the light-emitting element is arranged on one side of the driving device layer, one polar plate of the first capacitor is connected with the enabling module, and the other polar plate of the first capacitor is connected with the first electrode.

In a possible implementation manner of the first aspect, the pixel unit includes a red sub-pixel and a green sub-pixel, the light emitting element includes an equivalent capacitance, and at least one of the green sub-pixel, the red sub-pixel, and the blue sub-pixel is the target sub-pixel.

In a possible implementation manner of the first aspect, the green sub-pixel is turned on synchronously with the red sub-pixel and/or the blue sub-pixel.

In a second aspect, an embodiment of the present application provides a pixel circuit, including an enable module, a light emitting element, and a first capacitor;

the enabling module, the first capacitor and the light-emitting element are connected in series between a first voltage end and a second voltage end, and the first capacitor is connected between the light-emitting element and the enabling module and/or the first capacitor is electrically connected between the light-emitting element and the second voltage end; the enabling module is used for generating driving current to drive the light-emitting element to emit light.

In a third aspect, embodiments of the present application provide a display device including a display panel as in the embodiments of the first aspect, or including a pixel circuit as in the embodiments of the second aspect.

In this embodiment of the present application, the capacitance value of the first capacitor after being connected in series with the equivalent capacitor of the light emitting element is smaller than the capacitance value of the first capacitor and the capacitance value of the equivalent capacitor, it may be understood that adding the first capacitor connected in series with the light emitting element of the target subpixel is equivalent to reducing the equivalent capacitor corresponding to the target subpixel, and the equivalent capacitor corresponding to the target subpixel and the equivalent capacitor corresponding to the subpixels of other colors tend to be consistent, so that the charging time of the target subpixel and the charging time of the subpixels of other colors tend to be consistent, thereby improving or avoiding the color cast problem. For example, in the case where the green subpixel is the target subpixel, the problem of color shift such as reddening or blueing can be avoided.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings, in which like or similar reference characters designate the same or similar features, and which are not to scale.

Fig. 1 shows an equivalent circuit schematic of an organic light emitting diode;

FIG. 2 is a schematic top view of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present application;

FIG. 4 is a schematic circuit diagram of a target sub-pixel according to an embodiment of the present application;

fig. 5 is a schematic circuit diagram of a target subpixel according to another embodiment of the present application;

FIGS. 6-15 show some cross-sectional structural schematic views in the direction A-A in FIG. 2;

fig. 16 is a schematic circuit diagram showing a circuit configuration of a pixel circuit provided in an embodiment of the present application;

fig. 17 to 18 are schematic circuit diagrams illustrating pixel circuits according to other embodiments of the present disclosure;

fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are merely configured to explain the present application and are not configured to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.

It is noted that relational terms such as target and non-target, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.

Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically describes a problem existing in the prior art:

in a phosphorescent OLED light emitting element, which includes a host molecule (host molecule is also referred to as donor molecule) and a guest molecule (guest molecule is also referred to as acceptor molecule), the host molecule transfers energy to the guest molecule by energy transfer (Forster), and since such energy transfer is non-radiative, both the host molecule and the guest molecule observe spin conservation from a ground state to an excited state, only the singlet energy of the host molecule can be transferred to the singlet energy of the guest molecule, and the energy transfer that causes spin inversion cannot be caused. This requires that the emission spectrum of the host molecule overlap well with the absorption spectrum of the guest molecule, while the host molecule must be luminescent. The energy transfer mode has negligible effect on energy transfer to the triplet state, since the guest molecules have a large absorption to facilitate energy transfer, while the molar extinction coefficient of the triplet state is usually small.

The above is the energy transfer mechanism of the OLED light emitting device, and in this process, the OLED light emitting device can be analogous to a transistor and a capacitor. As shown in fig. 1, the OLED light emitting element may be equivalently a transistor T and an equivalent capacitor Cp connected in parallel, and it is understood that the OLED light emitting element includes a transistor and an equivalent capacitor. When the OLED light-emitting element is turned on, the equivalent capacitor Cp is charged first, and the transistor T is turned on until the end voltage of the equivalent capacitor Cp is charged to the turn-on voltage of the transistor T, so that the OLED light-emitting element emits light.

In the OLED display device, the pixel unit includes a red subpixel (R subpixel), a green subpixel (G subpixel), and a blue subpixel (B subpixel). The inventors of the present application found that, in general, the opening area of the G subpixel is larger than the opening area of the R subpixel, and the turn-on voltages of the G subpixel and the R subpixel are the same, so that the capacitance value of the equivalent capacitance of the G subpixel is larger than that of the R subpixel. In addition, the opening area of the B sub-pixel is larger than the opening area of the G sub-pixel and the opening area of the R sub-pixel, but the turn-on voltage of the B sub-pixel is higher, for example, the turn-on voltage of the B sub-pixel is between 2.6V and 3.0V, the turn-on voltages of the G sub-pixel and the R sub-pixel are between 2.0V and 2.3V, that is, the turn-on sensitivity of the B sub-pixel is high, and the response of the B sub-pixel is high under the same low voltage, so that the B sub-pixel does not cause the turn-on delay problem.

At a certain aperture ratio, the required charge amount of the R sub-pixel is the smallest, so that the required charging time of the R sub-pixel is shorter, and the Lan Guangqi light sensitivity is high, so that the required charging time of the B sub-pixel is also shorter, and the required charging time of the R sub-pixel and the B sub-pixel are basically the same. The inventors of the present application have also found that, in the first frame, the R and B sub-pixels are lit first, and then the G sub-pixels are lit after two frames. It is understood that the charging time of the G subpixel is longest. The charging time is related to the charging rate, and the larger the equivalent capacitance of the sub-pixel is, the slower the charging is, so it can be understood that the capacitance value of the equivalent capacitance of the G sub-pixel is the largest and the charging time of the G sub-pixel is the longest with respect to the R sub-pixel and the B sub-pixel. Since the charging time (the charging time can be understood as the non-light emitting time) of the G sub-pixel is longest in one frame time, the brightness of the G sub-pixel is lowest, and thus, a color shift problem of red shift or blue shift occurs, for example, each color sub-pixel is lit at different times of the first frame, a red shift abnormality occurs, or a smear occurs when dragging a picture in a dark color mode, and as the gray scale level decreases, the color shift problem becomes more serious.

In view of the above findings, embodiments of the present application provide a display panel, a pixel circuit and a display device, so as to solve the color shift problem in the prior art.

The display panel may be an OLED display panel, for example. The display panel of the embodiments of the present application may be presented in various forms, some examples of which will be described below.

As shown in fig. 2 and 3, the display panel 100 provided in the embodiment of the present application includes a pixel unit PU. The number of the pixel units PU may be plural, and the plural pixel units PU are distributed in an array. Each pixel unit PU includes sub-pixels P of a plurality of colors. The pixel unit PU may include three color sub-pixels, for example. In fig. 2, each pixel unit PU is exemplarily shown to include three color sub-pixels, such as a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, which are not intended to limit the present application.

The sub-pixel P includes a pixel circuit PC and a light emitting element D. The pixel circuit PC includes an enabling module 01. The enabling module 01 and the light emitting element D are connected in series between the first voltage terminal PVDD and the second voltage terminal PVEE. The enabling module 01 is used for generating a driving current to drive the light-emitting element D to emit light. The light emitting element D may be an organic light emitting diode.

The first power source terminal PVDD may provide a positive polarity voltage, and the second power source terminal PVEE may provide a negative polarity voltage. For example, the voltage of the first power source terminal PVDD may range from 3.3V to 4.6V, for example, the voltage of the first power source terminal PVDD may be 3.3V, 4V, 4.6V, or the like. The voltage range of the second power source end PVEE can be-3.5V to-2V, for example, the voltage of the second power source end PVEE can be-2V, -3V, -3.5V, etc.

At least one color sub-pixel of the sub-pixels P of the multiple colors in the pixel unit PU is a target sub-pixel. The light emitting element D may be an OLED light emitting element, which as described above may be equivalently a transistor and an equivalent capacitor connected in parallel, it being understood that the light emitting elements D of the sub-pixels of different colors each include an equivalent capacitor. The sub-pixel with the latest brightness of the sub-pixels with multiple colors under the same gray level can be used as the target sub-pixel. For example, in the case where the green subpixel P2 is turned on the latest, the green subpixel P2 may be the target subpixel; in the case where the red subpixel P1 is turned on the latest, the red subpixel P1 may be the target subpixel; in the case where the blue subpixel P3 is turned on the latest, the blue subpixel P3 may be the target subpixel. For example, if the display panel displays a red bias, the green subpixel P2 may be set as the target subpixel; if the display panel displays greenish, the red subpixel P1 may be set as the target subpixel; if the display panel is showing a yellow bias, the blue subpixel P3 may be set as the target subpixel. In the embodiment of the present application, the green sub-pixel P2 is used as the target sub-pixel, which is not limited to the present application.

As shown in fig. 4 and 5, the target subpixel further includes a first capacitor C1, and the first capacitor C1 and the light emitting element D of the target subpixel are connected in series between the enabling module 01 and the second voltage terminal PVEE. For example, the first capacitor C1 may be connected between the enable module 01 and the light emitting element D. For another example, the first capacitor C1 may be connected between the light emitting element D and the second voltage terminal PVEE. It will be appreciated that the first capacitor C1 is disposed in series with the light emitting element D of the target subpixel, that is, the equivalent capacitor Cp of the first capacitor C1 corresponding to the target subpixel is disposed in series, and the capacitor C after the first capacitor C1 is connected in series with the equivalent capacitor Cp corresponds to the formula (1):

the capacitance value corresponding to the capacitance C after the first capacitance C1 and the equivalent capacitance Cp are connected in series is smaller than the capacitance value of the first capacitance C1 and the capacitance value of the equivalent capacitance Cp, it can be understood that adding the first capacitance C1 connected in series with the light emitting element D of the target subpixel is equivalent to reducing the equivalent capacitance corresponding to the target subpixel, and the equivalent capacitance corresponding to the target subpixel and the equivalent capacitance corresponding to the subpixels of other colors tend to be consistent, so that the charging time of the target subpixel and the charging time of the subpixels of other colors tend to be consistent, and the color cast problem is improved or avoided. For example, in the case where the green subpixel is the target subpixel, the problem of color shift such as reddening or blueing can be avoided.

In some alternative embodiments, the pixel unit PU includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, and the green sub-pixel P2 may be a target sub-pixel, so that the green sub-pixel P2 and the red sub-pixel P1 and/or the blue sub-pixel P3 can be turned on synchronously, thereby avoiding the color cast problem.

As shown in fig. 2, the pixel unit PU includes a red subpixel P1 and a green subpixel P2, and the red subpixel P1 and the green subpixel P2 each include a light emitting element, which may be equivalently a transistor and an equivalent capacitor connected in parallel as described above, and it is understood that the light emitting element includes an equivalent capacitor. For example, in the case where the capacitance value of the equivalent capacitance corresponding to the green sub-pixel P2 is larger than the capacitance value of the equivalent capacitance corresponding to the red sub-pixel P1, the green sub-pixel P2 may be the target sub-pixel. The capacitance value of the first capacitor C1 of the green sub-pixel P2 and the capacitance value of the equivalent capacitor of the green sub-pixel P2 after being connected in series are set to be equal to the capacitance value of the equivalent capacitor of the red sub-pixel, so that the equivalent capacitor corresponding to the green sub-pixel is completely consistent with the equivalent capacitor corresponding to the red sub-pixel, and the charging time of the green sub-pixel is completely consistent with the charging time of the red sub-pixel, thereby avoiding the color cast problem.

It will be appreciated that the foregoing is merely an example, and is not intended to limit the present application, and whether to set the sub-pixel of the corresponding color as the target sub-pixel may be determined according to the on-time of the sub-pixel of the respective color or according to the magnitude of the capacitance value of the equivalent capacitance corresponding to the sub-pixel of the respective color.

It will be appreciated that the target subpixel adds a first capacitance C1 to the subpixels of the other colors. Still taking the green subpixel P2 as the target subpixel, as shown in fig. 6 or 7, the display panel 100 may include a substrate 10, a driving device layer 20 disposed on one side of the substrate 10, and a light emitting functional layer 30 disposed on a side of the driving device layer 20 facing away from the substrate 10. The enabling module 01 may be disposed in the driving device layer 20, and the light emitting element D may be disposed in the light emitting functional layer 30. The light emitting element D of each color sub-pixel includes a first electrode D1, a light emitting layer D2, and a second electrode D3, which are stacked. The first electrode D1 is electrically connected to the first voltage terminal PVDD (not shown in fig. 6 or 7) through the enable module 01, and the second electrode D3 is electrically connected to the second voltage terminal PVEE (not shown in fig. 6 or 7). Illustratively, the first electrode D1 may be an anode and the second electrode D3 may be a cathode.

Referring to fig. 4 and 6 in combination, alternatively, the first capacitor C1 may be connected between the light emitting layer D2 and the enable module 01, and the first electrode D1 may be multiplexed as at least one plate of the first capacitor C1. For example, the first capacitor C1 includes a first plate C11 and a second plate C12, where the second plate C12 is located on a side of the first plate C11 facing away from the substrate 10, and in this case, the first plate C11 may also be referred to as a lower plate, and the second plate C12 may also be referred to as an upper plate. For example, the first electrode D1 may multiplex the second electrode plate c12. It should be noted that fig. 6 only illustrates that the first electrode D1 includes one film layer, it is understood that the first electrode D1 may include at least two sub-film layers stacked, and in a case that the first electrode D1 includes a plurality of sub-film layers, the first electrode D1 may also multiplex the second electrode plate c12, and additionally provide a metal block as the first electrode plate c11.

As illustrated in fig. 6, the driving device layer 20 may include an active layer B, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4 stacked, a gate insulating layer GI may be disposed between the active layer B and the first metal layer M1, a capacitor insulating layer IMD may be disposed between the first metal layer M1 and the second metal layer M2, an interlayer dielectric layer ILD may be disposed between the second metal layer M2 and the third metal layer M3, and a first planarization layer PLN1 may be disposed between the third metal layer M3 and the fourth metal layer M4. The enable module 01 may include a transistor and a storage capacitor, and the transistor and the storage capacitor in the enable module 01 may be disposed at the active layer B, the first metal layer M1, the second metal layer M2, and the third metal layer M3. In the case where the first electrode D1 is multiplexed as the second electrode C12 of the first capacitor C1, the first electrode C11 of the first capacitor C1 may be disposed on the fourth metal layer M4.

As shown in fig. 6, the driving device layer 20 may further include a second planarization layer PLN2 between the first planarization layer PLN1 and the light emitting function layer 30. The light emitting function layer 30 may include a pixel defining layer PDL having openings distributed in an array, and the light emitting layer D2 is disposed in the openings. The second electrodes D3 of the respective light emitting elements D may be connected to each other to constitute a surface electrode.

Referring to fig. 5 and 7 or 8 in combination, alternatively, the first capacitor C1 may be connected between the light emitting layer D2 and the second voltage terminal PVEE, and the second electrode D3 may be multiplexed as at least one plate of the first capacitor C1. For example, the first capacitor C1 includes a first plate C11 and a second plate C12, where the second plate C12 is located on a side of the first plate C11 facing away from the substrate 10, and in this case, the first plate C11 may also be referred to as a lower plate, and the second plate C12 may also be referred to as an upper plate. For example, as shown in fig. 7, the second electrode D3 may multiplex the first plate c11. Alternatively, as shown in fig. 8, the second electrode D3 may be multiplexed as the second electrode plate c12.

It will be appreciated that, as shown in fig. 7, the second electrode C12 may be located on a side of the second electrode D3 facing away from the substrate 10, where the second electrode D3 is multiplexed into the first electrode C11, the second electrode D3 of the target subpixel P2 and the second electrodes D3 of the other color subpixels P1 and P2 may be independent from each other, and the forward projection of the second electrode C12 of the first capacitor C1 on the substrate 10 overlaps with the forward projection of the light emitting layer D2 of the target subpixel and the second electrode D3 of the target subpixel P2 on the substrate 10, and the forward projection of the second electrode C12 of the first capacitor C1 on the substrate 10 does not overlap with the forward projection of the light emitting layer D2 of the other color subpixels other than the target subpixel, so that the target subpixel includes the first capacitor C1 and the other color subpixels other than the target subpixel do not include the first capacitor C1.

It will be appreciated that, as shown in fig. 8, the second electrode D3 may be located on a side of the first electrode plate C11 facing away from the substrate 10, where the second electrode D3 is multiplexed to form the second electrode plate C12, and where the second electrodes D3 of the light emitting elements D of each color shown in fig. 8 may also be connected to each other so as to form a surface electrode, the front projection of the first electrode plate C11 of the first capacitor C1 on the substrate 10 overlaps with the front projection of the light emitting layer D2 of the target subpixel and the second electrode D3 of the target subpixel on the substrate 10, and the front projection of the first electrode plate C11 of the first capacitor C1 on the substrate 10 does not overlap with the front projection of the light emitting layer D2 of the other color subpixels other than the target subpixel, so that the target subpixel includes the first capacitor C1, and the other color subpixels other than the target subpixel do not include the first capacitor C1.

For example, fig. 7 and 8 each show that the second electrode D3 includes only one film layer, in which case the second electrode D3 may be multiplexed as one of the plates of the first capacitor C1. It can be understood that when the second electrode D3 is laminated with a plurality of layers, one of the two adjacent layers of the second electrode D3 may be multiplexed into one plate of the first capacitor C1, and the other layer may be multiplexed into the other plate of the first capacitor C1.

In addition, in the case where the second electrode D3 is multiplexed as at least one plate of the first capacitor C1, the driving device layer 20 shown in fig. 7 and 8 is not provided with the fourth metal layer M4 and includes only one planarization layer PLN, which is merely an example and is not intended to limit the present application, and the number of metal layers may be set according to the need.

Fig. 6 is an example in which a first capacitor C1 is electrically connected between the light emitting element D of the target subpixel and the enabling module 01, and fig. 7 and 8 are an example in which a first capacitor C1 is electrically connected between the light emitting element D of the target subpixel and the second voltage terminal. For example, as shown in fig. 9, a first capacitor C1 may be electrically connected between the light emitting element D of the target subpixel and the enable module 01, and between the light emitting element D of the target subpixel and the second voltage terminal. For ease of understanding, in fig. 9, a first capacitor C1 electrically connected between the light emitting element D of the target subpixel and the enable module 01 is denoted by C1-1, a dielectric layer between two plates of the first capacitor C1-1 is denoted by C10-1, a first capacitor C1 electrically connected between the light emitting element D of the target subpixel and the second voltage terminal is denoted by C1-2, and a dielectric layer between two plates of the first capacitor C1-1 is denoted by C10-2. Further, in the case that the first capacitor C1 is electrically connected between the light emitting element D of the target subpixel and the enable module 01, and between the light emitting element D of the target subpixel and the second voltage terminal, the first electrode D1 may be multiplexed as at least one plate of the first capacitor C1-1, and the second electrode D3 may be multiplexed as at least one plate of the first capacitor C1-2. In fig. 9, the first electrode D1 is multiplexed as the second plate C12 of the first capacitor C1-1, and the second plate D3 is multiplexed as the first plate C11 of the first capacitor C1-2, which is not intended to limit the present application.

In the embodiment of the application, at least one of the first electrode and the second electrode is multiplexed into at least one polar plate of the first capacitor, so that the number of film layers of the display panel can be reduced, and the process steps are simplified.

The display panel 100 may be a top-emission display panel, the first electrode D1 may be a stacked structure, and at least one of the stacked sub-film layers may reflect light, thereby improving the light-emitting efficiency of the display panel. In some alternative embodiments, the first electrode may include at least two sub-film layers stacked, where one sub-film layer of any two adjacent sub-film layers is multiplexed into one plate of the first capacitor, and the other sub-film layer is multiplexed into the other plate of the first capacitor.

For example, fig. 10 shows that the first electrode may include three sub-film layers stacked and divided into sub-film layers D11, D12, and D13, wherein the sub-film layer D12 is located between the sub-film layer D11 and the sub-film layer D13. Illustratively, the sub-film layer D12 is reflective, e.g., the material of the sub-film layer D12 may include silver (Ag). The materials of the sub-film layer D11 and the sub-film layer D13 may include Indium-Tin Oxide (ITO). Fig. 9 illustrates that the sub-film layer D12 is multiplexed to the first plate C11 of the first capacitor C1, and the sub-film layer D13 is multiplexed to the second plate C12 of the first capacitor C1.

For example, as shown in fig. 11, the sub-film layer D11 may be multiplexed to the first plate C11 of the first capacitor C1, and the sub-film layer D12 may be multiplexed to the second plate C12 of the first capacitor C1.

In addition, in the case where two adjacent sub-film layers of the first electrode D1 are multiplexed into two plates of the first capacitor C1, respectively, the driving device layer 20 shown in fig. 10 to 12 is not provided with the fourth metal layer M4 and includes only one planarization layer PLN, which is merely an example, and is not intended to limit the present application, and the number of metal layers may be set according to the need.

In the embodiment of the application, the two adjacent sub-film layers of the first electrode are respectively multiplexed into the two polar plates of the first capacitor, so that the number of the film layers of the display panel can be further reduced, and the process steps are simplified.

For example, as shown in fig. 12, the sub-film layer D13 may be multiplexed to the first plate C11 of the first capacitor C1, and the second plate C12 of the first capacitor C1 may be disposed on a side of the sub-film layer D13 facing away from the substrate 10. Illustratively, the material of the second plate c12 may be the same as the material of the sub-film layer D13.

In some alternative embodiments, as shown in fig. 6 or fig. 7, a dielectric layer C10 is disposed between the first plate C11 and the second plate C12, so that the first plate C11 and the second plate C12 and the dielectric layer C10 together can form the first capacitor C1.

The light emitting layer D2 of the light emitting element D generally includes a hole injecting layer, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and an electron injecting layer (not shown) stacked in a direction away from the first electrode D1, holes are injected from the first electrode D1 into the hole injecting layer, holes reach the organic light emitting layer through the hole transporting layer, electrons are injected from the second electrode D3 into the electron transporting layer, electrons reach the organic light emitting layer through the electron transporting layer, and energy is generated by recombination of the holes and electrons in the organic light emitting layer, and photons are released, so that the light emitting element D emits light. It will be appreciated that the hole is transported in the direction of the first electrode D1 to the organic light-emitting layer, and the electron is transported in the direction of the second electrode D3 to the organic light-emitting layer

Alternatively, in the case where the first capacitor C1 is electrically connected between the light emitting element of the target subpixel and the enable module, the material of the dielectric layer C10 may include a hole transport type material. The hole transport type material may be understood as a material contributing to hole transport, and since the material of the dielectric layer C10 includes a material contributing to hole transport, the transport direction of holes is not changed even if the first capacitance C1 is increased, thereby avoiding an influence on the light emitting efficiency, lifetime, and the like of the light emitting element. Similarly, in the case where the first capacitor C1 is electrically connected between the light emitting element of the target subpixel and the second voltage terminal, the material of the dielectric layer C10 includes an electron transport type material. The electron transport type material may be understood as a material contributing to electron transport, and since the material of the dielectric layer C10 includes a material contributing to electron transport, the transport direction of electrons is not changed even if the first capacitance C1 is increased, thereby avoiding an influence on the light emitting efficiency, the lifetime, and the like of the light emitting element.

For example, as shown in fig. 9, in the case where the first capacitor is electrically connected between the light emitting element of the target subpixel and the enable module and between the light emitting element of the target subpixel and the second voltage terminal, the material of the dielectric layer C10-1 corresponding to the first capacitor C1-1 electrically connected between the light emitting element of the target subpixel and the enable module may include a hole transport type material, and the material of the dielectric layer C10-2 corresponding to the first capacitor C1-2 electrically connected between the light emitting element of the target subpixel and the second voltage terminal may include an electron transport type material.

For example, in case that the first capacitor C1 is electrically connected between the light emitting element of the target subpixel and the enable module, the material of the dielectric layer C10 may include HTM081. For example, the material of the dielectric layer c10 may be selected from, but not limited to, hole transport materials such as phthalocyanine derivatives such as CuPc, conductive polymers or conductive dopant-containing polymers such as polystyrene, polyaniline/dodecylbenzenesulfonic acid (Pani/DBSA), poly (3, 4-ethylenedioxythiophene)/poly (4-styrenesulfonate) (PEDOT/PSS), polyaniline/camphorsulfonic acid (Pani/CSA), polyaniline/poly (4-styrenesulfonate) (Pani/PSS), aromatic amine derivatives, and the like. For example, the dielectric layer c10 may be doped with other materials. For example, the dielectric layer C10 may be doped with a material capable of adjusting the dielectric constant, so as to adjust the dielectric constant of the first capacitor C1, thereby avoiding affecting the light emitting efficiency of the light emitting element, and the like. Alternatively, the material of dielectric layer c10 may include NDP-9. Alternatively, the material of dielectric layer c10 may include NDP-9 and HTM081.

As described above, the display panel may include the substrate 10, the driving device layer 20, and the light emitting function layer 30, with the dielectric layer C10 disposed between the two plates of the first capacitor C1. In some alternative embodiments, as shown in fig. 10, the front projection of dielectric layer c10 onto substrate 10 overlaps the front projection of light emitting layer D2 onto substrate 10. Therefore, the equivalent capacitance corresponding to the first capacitor C1 and the target sub-pixel can be easily connected in series.

Further, an insulating layer 31 may be further disposed between the two multiplexed sub-film layers, where the insulating layer 31 surrounds the dielectric layer c10, and a surface of the insulating layer 31 facing away from the substrate 10 is level with a surface of the dielectric layer c10 facing away from the substrate 10. That is, the surface of the insulating layer 31 facing away from the substrate 10 and the surface of the dielectric layer c10 facing away from the substrate 10 form a plane, so that the light-emitting layer D2 can be deposited on the plane. Illustratively, the material of the insulating layer 31 may be the same as that of the pixel defining layer PDL.

Alternatively, the front projection of the dielectric layer c10 on the substrate 10 and the front projection of the light emitting layer D2 on the substrate 10 may overlap. The capacitance value of the capacitor is related to the facing area of the two polar plates, the dielectric constant of the dielectric layer between the polar plates and the thickness of the dielectric layer, in the application, the orthographic projection of the dielectric layer C10 on the substrate 10 is overlapped with the orthographic projection of the luminescent layer D2 on the substrate 10, that is to say, the facing area of the two polar plates of the first capacitor C1 is fixed, and under the condition that the dielectric constant of the dielectric layer between the polar plates is fixed, the control of the capacitance value of the first capacitor C1 can be realized only by controlling the thickness of the dielectric layer C10.

In some alternative embodiments, the thickness of insulating layer 31 is the same as the thickness of dielectric layer c10, such that the surface of insulating layer 31 facing away from substrate 10 is level with the surface of dielectric layer c10 facing away from substrate 10.

Optionally, the thickness of the insulating layer 31 and the thickness of the dielectric layer c10 range from 1 nm to 10 nm. For example, the thickness of the insulating layer 31 and the thickness of the dielectric layer c10 are 1 nm, 5 nm, 10 nm, and the like.

In some alternative embodiments, the two plates of the first capacitor may also be provided separately, i.e. the first electrode or the second electrode is no longer multiplexed as a plate of the first capacitor. Referring to fig. 4 and 13 in combination, a first capacitor C1 may be connected in series between the enable module 01 and the light emitting element D of the target subpixel, which includes a first electrode D1, a light emitting layer D2, and a second electrode D3 that are stacked. As described above, the display panel may further include a substrate 10 and a driving device layer 20, the enabling module 01 and the first capacitor C1 may be disposed in the driving device layer 20, the light emitting element D may be disposed on a side of the driving device layer 20 facing away from the substrate 10, one electrode plate of the first capacitor C1 is connected to the enabling module 01, and the other electrode plate of the first capacitor C1 is connected to the first electrode D1.

For example, the differences between fig. 13 and fig. 6 are not repeated, and the difference is that the driving device layer 20 may further include a fifth metal layer M5, a second planarization layer PLN2 may be disposed between the fifth metal layer M5 and the fourth metal layer M4, and the driving device layer 20 may further include a third planarization layer PLN3 disposed between the second planarization layer PLN2 and the light emitting function layer 30. The first plate C11 of the first capacitor C1 may be disposed on the fourth metal layer M4, and the second plate C12 of the first capacitor C1 may be disposed on the fifth metal layer M5. The first electrode plate c11 is connected to the enable module 01, and the second electrode plate c12 is connected to the first electrode D1.

In addition, fig. 7 and 8 illustrate a case where the first capacitor C1 is electrically connected between the light emitting element D of the target subpixel and the second voltage terminal, and the second electrode D3 is multiplexed as one plate of the first capacitor C1, it is understood that when the first capacitor C1 is electrically connected between the light emitting element D of the target subpixel and the second voltage terminal, as shown in fig. 14 or 15, the second electrode D3 and the first capacitor C1 may not have a multiplexing relationship.

For example, as shown in fig. 14, the first electrode C11 and the second electrode C12 of the first capacitor C1 may be located on a side of the second electrode D3 facing away from the substrate 10, an insulating layer 40 may be disposed between the first electrode C11 and the second electrode D3 of the target subpixel, and the first electrode C11 may be connected to the second electrode D3 of the target subpixel through a via. Illustratively, the second electrode D3 of the target subpixel P2 shown in fig. 14 and the second electrodes D3 of the other color subpixels P1, P2 may be independent from each other. The front projection of the second plate C12 of the first capacitor C1 on the substrate 10 overlaps with the front projection of the light emitting layer D2 of the target subpixel and the second electrode D3 of the target subpixel P2 on the substrate 10, and the front projection of the second plate C12 of the first capacitor C1 on the substrate 10 does not overlap with the front projection of the light emitting layers D2 of the other color subpixels than the target subpixel on the substrate 10, so that the target subpixel includes the first capacitor C1 and the other color subpixels other than the target subpixel do not include the first capacitor C1.

For example, as shown in fig. 15, the first electrode C11 and the second electrode C12 of the first capacitor C1 may be located on a side of the second electrode D3 facing the substrate 10, and the first electrode C11 and the second electrode C12 of the first capacitor C1 may be located on a side of the light emitting layer D2 of the target subpixel facing away from the substrate 10, and an insulating layer 40 may be disposed between the second electrode C12 and the second electrode D3 of the target subpixel, and the second electrode C12 may be connected to the second electrode D3 of the target subpixel through a via hole. Illustratively, the second electrodes D3 of the light emitting elements D of the respective colors shown in fig. 15 may also be connected to each other so as to constitute a plane electrode, the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 10 overlaps with the orthographic projection of the light emitting layer D2 of the target subpixel and the second electrode D3 of the target subpixel on the substrate 10, and the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate 10 does not overlap with the orthographic projection of the light emitting layer D2 of the other color subpixels other than the target subpixel on the substrate 10, so that the target subpixel includes the first capacitor C1, and the other color subpixels other than the target subpixel do not include the first capacitor C1.

It should be noted that the above embodiments may be combined with each other without contradiction.

Based on the same inventive concept, as shown in fig. 16 or 17, the embodiment of the present application further provides a pixel circuit, which may include an enabling module 01, a light emitting element D, and a first capacitor C1. The enabling module 01, the first capacitor C1 and the light emitting element D are connected in series between the first voltage terminal PVDD and the second voltage terminal PVEE, and the enabling module 01 is configured to generate a driving current to drive the light emitting element D to emit light. For example, as shown in fig. 16, the first capacitor C1 may be electrically connected between the light emitting element D and the enable module 01. As another example, as shown in fig. 17, the first capacitor C1 may be electrically connected between the light emitting element D and the second voltage terminal PVEE. For another example, the number of the first capacitors C1 may include at least two, one of the first capacitors C1 may be electrically connected between the light emitting element D and the enable module 01, and the other first capacitor C1 may be electrically connected between the light emitting element D and the second voltage terminal PVEE.

It will be appreciated that the pixel circuit shown in fig. 3 does not include the first capacitance, whereas the pixel circuits shown in fig. 16 and 17 include the first capacitance.

The pixel circuit provided by the embodiment of the application can be used for driving the light-emitting element with larger capacitance value of the equivalent capacitance, for example, the light-emitting element is a green light-emitting element. The first capacitor connected in series with the light-emitting element is increased, which is equivalent to reducing the equivalent capacitor corresponding to the light-emitting element, and the equivalent capacitor corresponding to the light-emitting element with other colors tend to be consistent, so that the charging time of the light-emitting element and the charging time of the light-emitting element with other colors tend to be consistent, and the color cast problem is improved or avoided. For example, in the case where the light emitting element is a green light emitting element, a problem of color shift of reddening or blushing can be avoided.

In some alternative embodiments, taking the connection of the first capacitor C1 between the light emitting element D and the enabling module 01 as shown in fig. 18, the enabling module 01 may include a driving sub-module 11, a data writing sub-module 12, a first initializing sub-module 13, a threshold compensating sub-module 14, a first light emitting sub-module 15, a second light emitting sub-module 16, a storage sub-module 17, and a second initializing sub-module 18. The driving sub-module 11 is electrically connected to the data writing sub-module 12, the data writing sub-module 12 is used for writing data voltages into the driving sub-module 11, and the driving sub-module 11 is used for generating driving currents. The first initializing sub-module 13 is electrically connected to the control terminal of the driving sub-module 11, and the first initializing sub-module 13 is configured to initialize the control terminal of the driving sub-module 11. The threshold compensation sub-module 14 is electrically connected to the control terminal of the driving sub-module 11, and the threshold compensation sub-module 14 is used for detecting and self-compensating the threshold voltage deviation in the driving sub-module 11. The first light-emitting control sub-module 15 is connected in series between the first voltage end PVDD and the driving sub-module 11, the second light-emitting control sub-module 16 is connected in series between the driving sub-module 11 and the light-emitting element D, and the first light-emitting control sub-module 15 and the second light-emitting control sub-module 16 are used for controlling the driving current generated by the driving sub-module 11 to be transmitted to the light-emitting element D. The storage sub-module 17 is electrically connected to the control terminal of the driving sub-module 11, and the storage sub-module 17 is used for maintaining the electric potential of the control terminal of the driving sub-module 11. The second initializing sub-module 18 is used for initializing the first electrode of the light emitting element D.

Illustratively, the control terminal of the first initialization sub-module 13 may be electrically connected to the first SCAN signal terminal SCAN1, and the input terminal of the first initialization sub-module 13 may be electrically connected to the reference signal terminal VREF. The control terminal of the threshold compensation sub-module 14 may be electrically connected to the second SCAN signal terminal SCAN 2. The control terminal of the data writing sub-module 12 may be electrically connected to the second SCAN signal terminal SCAN2, and the input terminal of the data writing sub-module 12 may be electrically connected to the data signal terminal VDATA. The control end of the first light emitting control sub-module 15 and the control end of the second light emitting control sub-module 16 may be connected to the light emitting control signal end EM. The control terminal of the second initialization sub-module 18 may be electrically connected to the first SCAN signal terminal SCAN1 or the second SCAN signal terminal SCAN2, the input terminal of the second initialization sub-module 18 may be electrically connected to the reference signal terminal VREF, and the other terminal of the second initialization sub-module 18 may be electrically connected to the first plate of the first capacitor C1.

In some alternative embodiments, as shown in fig. 18, the driving sub-module 11 includes a driving transistor T1, the data writing sub-module 12 includes a second transistor T2, the first initializing sub-module 13 includes a third transistor T3, the threshold compensating sub-module 14 includes a fourth transistor T4, the first light emitting sub-module 15 includes a fifth transistor T5, the second light emitting sub-module 16 includes a sixth transistor T6, the storage sub-module 17 includes a storage capacitor Cst, and the second initializing sub-module 18 includes a seventh transistor T7. The gate of the third transistor T3 is electrically connected to the first SCAN signal terminal SCAN1, the first pole of the third transistor T3 is electrically connected to the reference signal terminal VREF, and the second pole of the third transistor T3 is electrically connected to the gate of the driving transistor T1. The gate of the fourth transistor T4 is electrically connected to the second SCAN signal terminal SCAN2, the first pole of the fourth transistor T4 is electrically connected to the second pole of the driving transistor T1, and the second pole of the fourth transistor T4 is electrically connected to the gate of the driving transistor T1. The gate of the second transistor T2 is electrically connected to the second SCAN signal terminal SCAN2, the first electrode of the second transistor T2 is electrically connected to the data signal terminal VDATA, and the second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor T1. The gate of the fifth transistor T5 is electrically connected to the emission control signal terminal EM, the first pole of the fifth transistor T5 is electrically connected to the first voltage terminal PVDD, and the second pole of the fifth transistor T5 is electrically connected to the first pole of the driving transistor T1. The gate of the sixth transistor T6 is electrically connected to the emission control signal terminal EM, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light emitting element D. The first pole of the storage capacitor Cst is electrically connected to the first voltage terminal PVDD, and the second pole of the storage capacitor Cst is electrically connected to the gate of the driving transistor T1. The gate of the seventh transistor T7 is electrically connected to the first SCAN signal terminal SCAN1 or the second SCAN signal terminal SCAN2, the first pole of the seventh transistor T7 is electrically connected to the reference signal terminal VREF, the second pole of the seventh transistor T7 is electrically connected to the first plate of the first capacitor C1, the second plate of the first capacitor C1 is electrically connected to the first electrode of the light emitting element D, and the second electrode of the light emitting element D is electrically connected to the second voltage terminal PVEE.

It is to be understood that, in fig. 18, only the first capacitor C1 is electrically connected between the light emitting element D and the enabling module 01 as an example, and the first capacitor is electrically connected between the light emitting element D and the second voltage terminal PVEE, or the first capacitor is electrically connected between the light emitting element D and the enabling module 01 and between the light emitting element D and the second voltage terminal PVEE, wherein the specific structure and connection manner of the enabling module 01 may be as shown in fig. 18.

By way of example, the types of transistors in the pixel circuit may be the same, e.g., each transistor in the pixel circuit may be a P-type transistor or an N-type transistor, or may be partially P-type and partially N-type, as not limited in this application.

The application also provides a display device, which comprises the display panel provided by the embodiment of the application or the pixel circuit provided by the embodiment of the application. It will be appreciated that where the display device includes the pixel circuit provided in the embodiments of the present application includes the first capacitor, the pixel circuit of a sub-pixel of a partial color in the display device may include the first capacitor, and the pixel circuits of sub-pixels of other colors may not include the first capacitor. In addition, in the case where the first capacitor in the pixel circuit is electrically connected between the light emitting element and the second voltage terminal, the first capacitor may be electrically connected between the light emitting element of a partial color sub-pixel and the second voltage terminal, and the first capacitor may not be provided between the light emitting element of the other color sub-pixel and the second voltage terminal.

Referring to fig. 19, fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 19 provides a display device 1000 including a display panel 100 according to any of the embodiments described above. The embodiment of fig. 19 is only an example of a mobile phone, and the display device 1000 is described, and it is to be understood that the display device provided in the embodiment of the present application may be a wearable product, a computer, a television, a vehicle-mounted display device, or other display devices with display functions, which is not particularly limited in this application. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific descriptions of the display panel in the above embodiments may be referred to specifically, and the embodiments are not repeated here.

These embodiments are not all details described in detail in accordance with the embodiments described hereinabove, nor are they intended to limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. This application is to be limited only by the claims and the full scope and equivalents thereof.

Claims

1. A display panel, comprising:

the pixel units comprise sub-pixels with multiple colors, the sub-pixels comprise pixel circuits and light emitting elements, the pixel circuits comprise enabling modules, the enabling modules and the light emitting elements are connected in series between a first voltage end and a second voltage end, the sub-pixels with at least one color are target sub-pixels, the target sub-pixels further comprise first capacitors, and the first capacitors and the light emitting elements of the target sub-pixels are connected in series between the enabling modules and the second voltage end;

the enabling module comprises a driving sub-module, the first capacitor is connected between the second end of the driving sub-module and the light emitting element of the target sub-pixel, and/or the first capacitor is connected between the light emitting element of the target sub-pixel and the second voltage end, and the second end of the driving sub-module and the control end of the driving sub-module are different ends.

2. The display panel according to claim 1, wherein the light emitting element of the target subpixel includes a first electrode, a light emitting layer, and a second electrode which are stacked, the first electrode being electrically connected to the first voltage terminal through the enabling module, the second electrode being electrically connected to the second voltage terminal;

The first capacitor is electrically connected between the light emitting element of the target subpixel and the enabling module,

and/or the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the second voltage terminal.

3. The display panel of claim 2, wherein the first capacitor is electrically connected between the light emitting element of the target subpixel and the enable module, and the first electrode is multiplexed as at least one plate of the first capacitor;

4. The display panel according to claim 2, wherein the first electrode includes at least two sub-film layers stacked, one of any adjacent two sub-film layers being multiplexed as one plate of the first capacitor, and the other sub-film layer being multiplexed as the other plate of the first capacitor.

5. The display panel according to any one of claims 2-4, wherein a dielectric layer is arranged between two plates of the first capacitor;

the first capacitor is electrically connected between the light emitting element of the target subpixel and the second voltage terminal, and the material of the dielectric layer includes an electron transport type material.

6. The display panel of claim 4, wherein the display panel comprises a substrate, a dielectric layer is disposed between two plates of the first capacitor;

the front projection of the dielectric layer on the substrate overlaps with the front projection of the light-emitting layer on the substrate, an insulating layer is further arranged between the two multiplexed sub-film layers, the insulating layer surrounds the dielectric layer, and the surface of the insulating layer, which is back to the substrate, is leveled with the surface of the dielectric layer, which is back to the substrate.

7. The display panel of claim 6, wherein an orthographic projection of the dielectric layer on the substrate overlaps an orthographic projection of the light emitting layer on the substrate.

8. The display panel of claim 6, wherein the insulating layer has a thickness that is the same as a thickness of the dielectric layer.

9. The display panel of claim 8, wherein the thickness of the insulating layer and the thickness of the dielectric layer range from 1 nm to 10 nm.

10. The display panel according to claim 1, wherein the first capacitor is connected in series between the enable module and a light emitting element of the target subpixel, the light emitting element of the target subpixel including a first electrode, a light emitting layer, and a second electrode that are stacked;

11. The display panel of claim 1, wherein the pixel unit includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel, at least one of the green sub-pixel, the red sub-pixel, and the blue sub-pixel being the target sub-pixel.

12. The display panel of claim 11, wherein the green sub-pixel is the target sub-pixel, and the green sub-pixel is turned on in synchronization with the red sub-pixel and/or the blue sub-pixel.

13. A pixel circuit, applied to the display panel according to any one of claims 1 to 12, comprising: an enable module, a light emitting element, and a first capacitor;

the enabling module, the first capacitor and the light-emitting element are connected in series between a first voltage end and a second voltage end, and the first capacitor is electrically connected between the light-emitting element and the enabling module and/or the first capacitor is electrically connected between the light-emitting element and the second voltage end; the enabling module is used for generating driving current to drive the light-emitting element to emit light;

14. A display device comprising the display panel according to any one of claims 1 to 12 or comprising the pixel circuit according to claim 13.