CN114023256A

CN114023256A - Display panel, pixel circuit and display device

Info

Publication number: CN114023256A
Application number: CN202111211998.6A
Authority: CN
Inventors: 王宏宇; 魏现鹤; 孙光远; 孙大卫; 蔡明瀚
Original assignee: Yungu Guan Technology Co Ltd
Current assignee: Yungu Guan Technology Co Ltd
Priority date: 2021-10-18
Filing date: 2021-10-18
Publication date: 2022-02-08
Anticipated expiration: 2041-10-18
Also published as: CN114023256B

Abstract

The application discloses a display panel, a pixel circuit and a display device. The display panel comprises a plurality of pixel units, each pixel unit comprises a plurality of sub-pixels of multiple colors, each sub-pixel comprises a pixel circuit and a light-emitting element, each pixel circuit comprises an enabling module, the enabling module and the light-emitting elements are connected between a first voltage end and a second voltage end in series, the sub-pixel of at least one color is a target sub-pixel, each target sub-pixel further comprises a first capacitor, and the first capacitor and the light-emitting elements of the target sub-pixels are connected between the enabling module and the second voltage ends in series. According to the embodiment of the application, the problem of color cast when the display panel displays can be solved, and the display effect is improved.

Description

Display panel, pixel circuit and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel, a pixel circuit and a display device.

Background

An Organic Light Emitting Diode (OLED) display panel is a display device that has many advantages such as flexible display and large-area full color display, and is considered to have the most potential for development.

However, the inventors of the present application have found that the OLED display panel has a color shift phenomenon during low-luminance display, and thus has a problem of poor display effect.

Disclosure of Invention

The application provides a display panel, pixel circuit and display device, simple structure can solve the colour cast problem when OLED display panel shows, improves display effect.

In a first aspect, an embodiment of the present application provides a display panel, which includes a plurality of pixel units, each pixel unit includes a plurality of color sub-pixels, each sub-pixel includes a pixel circuit and a light emitting element, each pixel circuit includes an enable module, the enable module and the light emitting element are connected in series between a first voltage terminal and a second voltage terminal, the sub-pixel of at least one color is a target sub-pixel, and the target sub-pixel further includes a first capacitor connected in series with the light emitting element of the target sub-pixel between the enable module and the second voltage terminal.

In one possible implementation manner of the first aspect, the light emitting element of the target sub-pixel includes a first electrode, a light emitting layer, and a second electrode, which are stacked, the first electrode is electrically connected to the first voltage terminal through the enabling module, and the second electrode is electrically connected to the second voltage terminal;

the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the enabling module, and the first electrode is multiplexed as at least one polar plate of the first capacitor;

and/or the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the second voltage end, and the second electrode is multiplexed as at least one polar plate of the first capacitor.

In a possible implementation manner of the first aspect, the first electrode includes at least two sub-film layers stacked, one of any two adjacent sub-film layers is reused as one plate of the first capacitor, and the other sub-film layer is reused as the other plate of the first capacitor.

In a possible implementation manner of the first aspect, a dielectric layer is arranged between two plates of the first capacitor;

under the condition that the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the enabling module, the material of the dielectric layer comprises a hole-transport type material;

the first capacitor is electrically connected between the light emitting element of the target sub-pixel and the second voltage terminal, and the material of the dielectric layer includes an electron transport type material.

In a possible implementation manner of the first aspect, the display panel includes a substrate, and a dielectric layer is disposed between two plates of the first capacitor;

the orthographic projection of the dielectric layer on the substrate is overlapped with the orthographic projection of the light-emitting layer on the substrate, an insulating layer is also arranged between the two multiplexed sub-film layers, the insulating layer surrounds the dielectric layer, and the surface of the insulating layer, which is back to the substrate, is flush with the surface of the dielectric layer, which is back to the substrate;

preferably, an orthographic projection of the dielectric layer on the substrate overlaps with an orthographic projection of the light-emitting layer on the substrate.

In a possible embodiment of the first aspect, the thickness of the insulating layer is the same as the thickness of the dielectric layer;

preferably, the thickness of the insulating layer and the thickness of the dielectric layer range from 1 nm to 10 nm.

In one possible implementation manner of the first aspect, the first capacitor is connected in series between the enabling module and the light emitting element of the target sub-pixel, and the light emitting element of the target sub-pixel comprises a first electrode, a light emitting layer and a second electrode which are arranged in a stacked manner;

the display panel further comprises a driving device layer, the enabling module and the first capacitor are arranged on the driving device layer, the light-emitting element is arranged on one side of the driving device layer, one polar plate of the first capacitor is connected with the enabling module, and the other polar plate of the first capacitor is connected with the first electrode.

In one possible implementation manner of the first aspect, the pixel unit includes a red sub-pixel and a green sub-pixel, the light emitting element includes an equivalent capacitor, and at least one of the green sub-pixel, the red sub-pixel, and the blue sub-pixel is a target sub-pixel.

In a possible implementation of the first aspect, the green sub-pixel is lit in synchronization with the red sub-pixel and/or the blue sub-pixel.

In a second aspect, an embodiment of the present application provides a pixel circuit, including an enable module, a light emitting element, and a first capacitor;

the enabling module, the first capacitor and the light-emitting element are connected in series between a first voltage end and a second voltage end, the first capacitor is connected between the light-emitting element and the enabling module, and/or the first capacitor is electrically connected between the light-emitting element and the second voltage end; the enabling module is used for generating driving current to drive the light-emitting element to emit light.

In a third aspect, an embodiment of the present application provides a display device, which includes the display panel as an embodiment of the first aspect, or includes the pixel circuit as an embodiment of the second aspect.

In the embodiment of the present application, the capacitance value of the first capacitor connected in series with the equivalent capacitor of the light emitting element is smaller than the capacitance value of the first capacitor and the capacitance value of the equivalent capacitor, and it can be understood that increasing the first capacitor connected in series with the light emitting element of the target sub-pixel is equivalent to reducing the equivalent capacitor corresponding to the target sub-pixel, so that the equivalent capacitor corresponding to the target sub-pixel and the equivalent capacitors corresponding to sub-pixels of other colors tend to be consistent, and thus the charging time of the target sub-pixel and the charging time of sub-pixels of other colors tend to be consistent, thereby improving or avoiding the color cast problem. For example, when the green sub-pixel is the target sub-pixel, the color shift problem of red shift or blue shift can be avoided.

Drawings

Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof, and which are not to scale.

Fig. 1 shows an equivalent circuit schematic of an organic light emitting diode;

FIG. 2 is a schematic top view of a display panel according to an embodiment of the present application;

FIG. 3 is a schematic circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a circuit structure of a target sub-pixel according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a target sub-pixel according to another embodiment of the present application;

FIGS. 6-15 illustrate some schematic cross-sectional configurations taken along line A-A of FIG. 2;

fig. 16 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

fig. 17 to 18 are schematic circuit diagrams of pixel circuits according to further embodiments of the present application;

fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present application.

Detailed Description

Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as target and non-target, and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

Before explaining the technical solutions provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application first specifically explains the problems existing in the prior art:

in a phosphorescent OLED light-emitting element including a host molecule (host molecule is also referred to as a donor molecule) and a guest molecule (guest molecule is also referred to as an acceptor molecule), the host molecule transfers energy to the guest molecule by energy transfer (Forster), and since the energy transfer is non-radiative and the host molecule and the guest molecule observe spin conservation from a ground state to an excited state, only singlet energy of the host molecule can be transferred to singlet energy of the guest molecule without energy transfer that causes spin inversion. This requires that the emission spectrum of the host molecule overlaps well with the absorption spectrum of the guest molecule, while the host molecule must be luminescent. The effect of energy transfer means to transfer energy to the triplet state is negligible because the guest molecule requires greater absorption to facilitate energy transfer, and the molar extinction coefficient of the triplet state is usually small.

The above is the energy transfer mechanism of the OLED light emitting device, in this process, the OLED light emitting device can be analogized to a transistor and a capacitor. As shown in fig. 1, the OLED light emitting element can be equivalently connected in parallel with a transistor T and an equivalent capacitor Cp, and it can be understood that the OLED light emitting element includes a transistor and an equivalent capacitor. When the OLED light emitting element is turned on, the equivalent capacitor Cp needs to be charged first, and the voltage across the equivalent capacitor Cp is charged until the voltage of the transistor T is turned on, so that the transistor T is turned on and the OLED light emitting element emits light.

In the OLED display device, a pixel unit includes a red sub-pixel (R sub-pixel), a green sub-pixel (G sub-pixel), and a blue sub-pixel (B sub-pixel). The inventors of the present application have found that, in general, the aperture area of the G sub-pixel is larger than that of the R sub-pixel, and the turn-on voltages of the G sub-pixel and the R sub-pixel are the same, so that the capacitance value of the equivalent capacitance of the G sub-pixel is larger than that of the R sub-pixel. In addition, the opening area of the B sub-pixel is larger than the opening area of the G sub-pixel and the opening area of the R sub-pixel, but the lighting voltage of the B sub-pixel is higher, for example, the lighting voltage of the B sub-pixel is between 2.6V and 3.0V, the lighting voltage of the G sub-pixel and the R sub-pixel is between 2.0V and 2.3V, that is, the lighting sensitivity of the B sub-pixel is high, and the response of the B sub-pixel is high under the same low voltage, so the B sub-pixel does not cause the lighting delay problem.

Under a certain aperture ratio, the charge quantity required by the R sub-pixel is minimum, so that the charging time required by the R sub-pixel is shorter, the blue light starting sensitivity is high, the charging time required by the B sub-pixel is shorter, and the charging time required by the R sub-pixel and the charging time required by the B sub-pixel are basically the same. The inventors of the present application have also found that the R and B sub-pixels are lit first for the first frame, and then the G sub-pixel is lit after two frames. It can be understood that the charging time of the G sub-pixel is longest. The charging time is related to the charging rate, and the charging is slower the larger the equivalent capacitance of the sub-pixel is, so it can be understood that the capacitance value of the equivalent capacitance of the G sub-pixel is the largest and the charging time of the G sub-pixel is the longest relative to the R sub-pixel and the B sub-pixel. Since the charging time (charging time can be understood as non-light-emitting time) of the G sub-pixel is longest in one frame time, the luminance of the G sub-pixel is the lowest, and thus, the color shift problem of red or blue may occur, for example, each color sub-pixel is turned on at different time of the first frame, red shift abnormality occurs, or in a dark color mode, a smear occurs when the picture is dragged, and the color shift problem may become more serious as the gray scale level is reduced.

In view of the above findings, embodiments of the present application provide a display panel, a pixel circuit, and a display device to solve the color shift problem in the prior art.

Illustratively, the display panel may be an OLED display panel. The display panel of the embodiments of the present application may be presented in various forms, some examples of which will be described below.

As shown in fig. 2 and fig. 3, a display panel 100 provided in the embodiment of the present application includes a pixel unit PU. The number of the pixel units PU may be multiple, and the multiple pixel units PU are distributed in an array. Each pixel unit PU includes a plurality of color sub-pixels P. Illustratively, the pixel unit PU may include three color sub-pixels. Each pixel unit PU is exemplarily shown in fig. 2 to include three color sub-pixels, for example, a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, which is not limited to the present application.

The sub-pixel P includes a pixel circuit PC and a light emitting element D. The pixel circuit PC includes an enable module 01. The enable module 01 and the light emitting element D are connected in series between a first voltage terminal PVDD and a second voltage terminal PVEE. The enabling module 01 is used for generating a driving current to drive the light emitting element D to emit light. The light emitting element D may be an organic light emitting diode.

The first power source terminal PVDD may supply a positive polarity voltage and the second power source terminal PVEE may supply a negative polarity voltage. For example, the voltage of the first power source terminal PVDD may range from 3.3V to 4.6V, and for example, the voltage of the first power source terminal PVDD may be 3.3V, 4V, 4.6V, or the like. The voltage range of the second power source terminal PVEE can be-3.5V to-2V, for example, the voltage of the second power source terminal PVEE can be-2V, -3V, -3.5V, etc.

At least one color sub-pixel in the multi-color sub-pixels P in the pixel unit PU is a target sub-pixel. The light emitting elements D may be OLED light emitting elements, which may be equivalently a transistor and an equivalent capacitor connected in parallel as described above, and it is understood that the light emitting elements D of the sub-pixels of different colors each include an equivalent capacitor. The sub-pixel with the latest brightness under the same gray scale of the sub-pixels with multiple colors can be used as the target sub-pixel. For example, in the case where the green subpixel P2 is turned on latest, the green subpixel P2 may be the target subpixel; in the case that the red subpixel P1 is turned on at the latest, the red subpixel P1 may be the target subpixel; in the case where the blue subpixel P3 is turned on at the latest, the blue subpixel P3 may be the target subpixel. For example, if the display panel displays a red-biased display, the green subpixel P2 may be set as the target subpixel; if the display panel displays greenish, the red sub-pixel P1 may be set as the target sub-pixel; if the display panel displays a yellow bias, the blue subpixel P3 may be set as the target subpixel. In the embodiment of the present application, the green sub-pixel P2 is taken as an example of a target sub-pixel, which is not intended to limit the present application.

As shown in fig. 4 and 5, the target sub-pixel further includes a first capacitor C1, and the first capacitor C1 is connected in series with the light emitting element D of the target sub-pixel between the enable module 01 and the second voltage terminal PVEE. For example, the first capacitor C1 may be connected between the enabling module 01 and the light emitting element D. For another example, the first capacitor C1 may be connected between the light emitting element D and the second voltage terminal PVEE. It can be understood that the first capacitor C1 is disposed in series with the light emitting element D of the target sub-pixel, that is, the first capacitor C1 is disposed in series with the equivalent capacitor Cp corresponding to the target sub-pixel, and the capacitor C after the first capacitor C1 is connected in series with the equivalent capacitor Cp conforms to the following formula (1):

the capacitance value of the capacitor C after the first capacitor C1 is connected in series with the equivalent capacitor Cp is smaller than the capacitance value of the first capacitor C1 and the capacitance value of the equivalent capacitor Cp, and it can be understood that the addition of the first capacitor C1 connected in series with the light emitting element D of the target sub-pixel is equivalent to the reduction of the equivalent capacitor corresponding to the target sub-pixel, so that the equivalent capacitor corresponding to the target sub-pixel and the equivalent capacitors corresponding to sub-pixels of other colors tend to be consistent, the charging time of the target sub-pixel and the charging time of sub-pixels of other colors tend to be consistent, and the color cast problem is improved or avoided. For example, when the green sub-pixel is the target sub-pixel, the color shift problem of red shift or blue shift can be avoided.

In some alternative embodiments, the pixel unit PU includes a red sub-pixel P1, a green sub-pixel P2, and a blue sub-pixel P3, and the green sub-pixel P2 may be a target sub-pixel, so that the green sub-pixel P2 and the red sub-pixel P1 and/or the blue sub-pixel P3 can be turned on synchronously to avoid the color shift problem.

Illustratively, as shown in fig. 2, the pixel unit PU includes a red sub-pixel P1 and a green sub-pixel P2, and each of the red sub-pixel P1 and the green sub-pixel P2 includes a light emitting element, and as described above, the light emitting element is equivalent to a transistor and an equivalent capacitor connected in parallel, and it can be understood that the light emitting element includes an equivalent capacitor. For example, in the case where the capacitance value of the equivalent capacitance corresponding to the green sub-pixel P2 is greater than that of the equivalent capacitance corresponding to the red sub-pixel P1, the green sub-pixel P2 may be the target sub-pixel. The capacitance value of the series connection of the first capacitor C1 of the green sub-pixel P2 and the equivalent capacitor of the green sub-pixel P2 and the capacitance value of the equivalent capacitor of the red sub-pixel can be set to be equal, so that the equivalent capacitor corresponding to the green sub-pixel and the equivalent capacitor corresponding to the red sub-pixel can be completely consistent, the charging time of the green sub-pixel and the charging time of the red sub-pixel are completely consistent, and the problem of color cast can be avoided.

It is to be understood that the above is only an example and is not intended to limit the present disclosure, and whether to set the sub-pixel of the corresponding color as the target sub-pixel may be determined according to the turn-on time of the sub-pixel of each color or according to the size of the capacitance value of the equivalent capacitance corresponding to the sub-pixel of each color.

It will be appreciated that the target sub-pixel has an increased first capacitance C1 relative to the sub-pixels of the other colors. Still taking the green sub-pixel P2 as an example as the target sub-pixel, as shown in fig. 6 or fig. 7, the display panel 100 may include a substrate 10, a driving device layer 20 disposed on one side of the substrate 10, and a light emitting function layer 30 disposed on one side of the driving device layer 20 opposite to the substrate 10. The enable module 01 may be disposed in the driving device layer 20, and the light emitting element D may be disposed in the light emitting function layer 30. The light emitting element D of the sub-pixel of each color includes a first electrode D1, a light emitting layer D2, and a second electrode D3, which are stacked. The first electrode D1 is electrically connected to a first voltage terminal PVDD (not shown in fig. 6 or 7) through the enable module 01, and the second electrode D3 is electrically connected to a second voltage terminal PVEE (not shown in fig. 6 or 7). For example, the first electrode D1 may be an anode, and the second electrode D3 may be a cathode.

Referring to fig. 4 and 6 in combination, optionally, a first capacitor C1 may be connected between the light emitting layer D2 and the enabling module 01, and the first electrode D1 may be multiplexed into at least one plate of the first capacitor C1. For example, the first capacitor C1 includes a first plate C11 and a second plate C12, the second plate C12 is located on a side of the first plate C11 opposite to the substrate 10, in which case, the first plate C11 may also be referred to as a lower plate, and the second plate C12 may also be referred to as an upper plate. For example, the first electrode D1 may multiplex the second plate c 12. It should be noted that fig. 6 only illustrates that the first electrode D1 includes one film layer, and it is understood that the first electrode D1 may include at least two sub-film layers arranged in a stacked manner, and in the case that the first electrode D1 includes a plurality of sub-film layers, the first electrode D1 may also multiplex the second electrode c12, and additionally dispose a metal block as the first electrode c 11.

For example, as shown in fig. 6, the driving device layer 20 may include an active layer B, a first metal layer M1, a second metal layer M2, a third metal layer M3, and a fourth metal layer M4, which are stacked, a gate insulating layer GI may be disposed between the active layer B and the first metal layer M1, a capacitor insulating layer IMD may be disposed between the first metal layer M1 and the second metal layer M2, an interlayer dielectric layer ILD may be disposed between the second metal layer M2 and the third metal layer M3, and a first planarizing layer PLN1 may be disposed between the third metal layer M3 and the fourth metal layer M4. The enable module 01 may include a transistor and a storage capacitor, and the transistor and the storage capacitor in the enable module 01 may be disposed on the active layer B, the first metal layer M1, the second metal layer M2, and the third metal layer M3. In the case that the first electrode D1 is reused as the second plate C12 of the first capacitor C1, the first plate C11 of the first capacitor C1 may be disposed on the fourth metal layer M4.

As shown in fig. 6, the driving device layer 20 may further include a second planarization layer PLN2 between the first planarization layer PLN1 and the light emitting function layer 30. The light emitting function layer 30 may include a pixel defining layer PDL having openings arranged in an array, and the light emitting layer D2 is disposed in the openings. The second electrodes D3 of the light emitting elements D may be connected to each other to constitute surface electrodes.

Referring to fig. 5 and 7 or 8 in combination, alternatively, the first capacitor C1 may be connected between the light emitting layer D2 and the second voltage terminal PVEE, and the second electrode D3 may be multiplexed as at least one plate of the first capacitor C1. For example, the first capacitor C1 includes a first plate C11 and a second plate C12, the second plate C12 is located on a side of the first plate C11 opposite to the substrate 10, in which case, the first plate C11 may also be referred to as a lower plate, and the second plate C12 may also be referred to as an upper plate. For example, as shown in fig. 7, the second electrode D3 may multiplex the first pad c 11. Alternatively, as shown in fig. 8, the second electrode D3 may be multiplexed into the second plate c 12.

It is understood that, as shown in fig. 7, the second plate C12 may be located on a side of the second electrode D3 facing away from the substrate 10, in a case where the second electrode D3 is multiplexed as the first plate C11, the second electrode D3 of the target subpixel P2 and the second electrodes D3 of the other color subpixels P1 and P2 may be independent of each other, an orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate 10 overlaps with the light emitting layer D2 of the target subpixel and an orthogonal projection of the second electrode D3 of the target subpixel P2 on the substrate 10, and an orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate 10 does not overlap with the light emitting layer D2 of the other color subpixels than the target subpixel on the substrate 10, so that the target subpixel includes the first capacitor C1, and the other color subpixels than the target subpixel do not include the first capacitor C1.

It is to be understood that, as shown in fig. 8, the second electrode D3 may be located on a side of the first plate C11 facing away from the substrate 10, and in a case where the second electrode D3 is multiplexed as the second plate C12, the second electrodes D3 of the light emitting elements D of the respective colors shown in fig. 8 may also be connected to each other to constitute a planar electrode, an orthogonal projection of the first plate C11 of the first capacitor C1 on the substrate 10 overlaps with the light emitting layer D2 of the target sub-pixel and an orthogonal projection of the second electrode D3 of the target sub-pixel on the substrate 10, and an orthogonal projection of the first plate C11 of the first capacitor C1 on the substrate 10 does not overlap with an orthogonal projection of the light emitting layer D2 of the sub-pixel of the other color than the target sub-pixel on the substrate 10, so that the target sub-pixel includes the first capacitor C1, and the sub-pixel of the other color than the target sub-pixel does not include the first capacitor C1.

For example, fig. 7 and 8 each illustrate that the second electrode D3 includes only one film layer, in which case the second electrode D3 may be reused as one of the plates of the first capacitor C1. It is understood that when the second electrode D3 includes a plurality of film layers stacked, one of the adjacent two film layers of the second electrode D3 may be reused as one plate of the first capacitor C1, and the other film layer may be reused as the other plate of the first capacitor C1.

In addition, in the case where the second electrode D3 is multiplexed as at least one plate of the first capacitor C1, the driving device layer 20 shown in fig. 7 and 8 is not provided with the fourth metal layer M4 and includes only one planarization layer PLN, which is merely an example and is not intended to limit the present application, and the number of metal layers may be provided as required.

Fig. 6 illustrates an example in which a first capacitor C1 is electrically connected between the light emitting element D of the target sub-pixel and the enabling module 01, and fig. 7 and 8 illustrate an example in which a first capacitor C1 is electrically connected between the light emitting element D of the target sub-pixel and the second voltage terminal. Illustratively, as shown in fig. 9, a first capacitor C1 may be electrically connected between the light emitting element D of the target sub-pixel and the enabling module 01, and between the light emitting element D of the target sub-pixel and the second voltage terminal. For convenience of understanding, in fig. 9, the first capacitor C1 electrically connected between the light emitting element D of the target sub-pixel and the enabling module 01 is denoted by C1-1, the dielectric layer between the two plates of the first capacitor C1-1 is denoted by C10-1, the first capacitor C1 electrically connected between the light emitting element D of the target sub-pixel and the second voltage terminal is denoted by C1-2, and the dielectric layer between the two plates of the first capacitor C1-1 is denoted by C10-2. Further, under the condition that the first capacitor C1 is electrically connected between the light emitting element D of the target sub-pixel and the enabling module 01, and between the light emitting element D of the target sub-pixel and the second voltage terminal, the first electrode D1 can be reused as at least one plate of the first capacitor C1-1, and the second electrode D3 can be reused as at least one plate of the first capacitor C1-2. In fig. 9, the first electrode D1 is multiplexed as the second plate C12 of the first capacitor C1-1, and the second plate D3 is multiplexed as the first plate C11 of the first capacitor C1-2, which is not limited to the present application.

In the embodiment of the application, at least one of the first electrode and the second electrode is multiplexed as at least one polar plate of the first capacitor, so that the number of film layers of the display panel can be reduced, and the process steps are simplified.

The display panel 100 may be a top emission display panel, and the first electrode D1 may have a stacked structure, and at least one of the stacked sub-film layers may reflect light, thereby improving the light extraction efficiency of the display panel. In some alternative embodiments, the first electrode may include at least two sub-film layers stacked, one of any two adjacent sub-film layers is reused as one plate of the first capacitor, and the other sub-film layer is reused as the other plate of the first capacitor.

For example, fig. 10 shows that the first electrode may include three sub-film layers arranged in a stack, which are divided into sub-film layers D11, D12 and D13, wherein the sub-film layer D12 is located between the sub-film layer D11 and the sub-film layer D13. Illustratively, the sub-film layer D12 is capable of reflecting light, for example, the material of the sub-film layer D12 may include silver (Ag). The materials of the sub-film layers D11 and D13 may include Indium-Tin Oxide (ITO). Fig. 9 shows that the sub-film D12 is multiplexed as the first plate C11 of the first capacitor C1, and the sub-film D13 is multiplexed as the second plate C12 of the first capacitor C1.

For example, as shown in fig. 11, it may also be configured that the sub-film layer D11 is multiplexed as the first plate C11 of the first capacitor C1, and the sub-film layer D12 is multiplexed as the second plate C12 of the first capacitor C1.

In addition, in the case where two adjacent sub-film layers of the first electrode D1 are respectively multiplexed as two plates of the first capacitor C1, the driving device layer 20 shown in fig. 10 to 12 is not provided with the fourth metal layer M4 and includes only one planarization layer PLN, which is merely an example and is not intended to limit the present application, and the number of metal layers may be set as required.

In the embodiment of the application, two adjacent sub-film layers of the first electrode are respectively multiplexed into two electrode plates of the first capacitor, so that the number of film layers of the display panel can be further reduced, and the process steps are simplified.

For example, as shown in fig. 12, it may also be configured that the sub-film layer D13 is reused as the first plate C11 of the first capacitor C1, and the second plate C12 of the first capacitor C1 is disposed on the side of the sub-film layer D13 facing away from the substrate 10. For example, the material of the second plate c12 may be the same as the material of the sub-film layer D13.

In some alternative embodiments, as shown in fig. 6 or fig. 7, a dielectric layer C10 is disposed between the first plate C11 and the second plate C12, so that the first plate C11 and the second plate C12 together with the dielectric layer C10 can form a first capacitor C1.

The light-emitting layer D2 of the light-emitting element D generally includes a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer (not shown in the figure) stacked in a direction away from the first electrode D1, holes are injected from the first electrode D1 into the hole injection layer, the holes reach the organic light-emitting layer through the hole transport layer, electrons are injected from the second electrode D3 into the electron transport layer, the electrons reach the organic light-emitting layer through the electron transport layer, and the holes and the electrons recombine in the organic light-emitting layer to generate energy and release photons, so that the light-emitting element D emits light. It is understood that the hole is transported from the first electrode D1 to the organic light emitting layer, and the electron is transported from the second electrode D3 to the organic light emitting layer

Alternatively, in the case where the first capacitor C1 is electrically connected between the light emitting element of the target sub-pixel and the enable block, the material of the dielectric layer C10 may include a hole transport type material. The hole transport type material may be understood as a material contributing to hole transport, and since the material of the dielectric layer C10 includes a material contributing to hole transport, even if the first capacitance C1 is increased, the transport direction of holes is not changed, thereby avoiding affecting the light emitting efficiency, lifetime, and the like of the light emitting element. Similarly, in the case where the first capacitor C1 is electrically connected between the light emitting element of the target sub-pixel and the second voltage terminal, the material of the dielectric layer C10 includes an electron transport type material. The electron transport type material may be understood as a material contributing to electron transport, and since the material of the dielectric layer C10 includes a material contributing to electron transport, even if the first capacitor C1 is added, the transport direction of electrons is not changed, thereby preventing the light emitting efficiency, the lifetime, and the like of the light emitting element from being affected.

Illustratively, as shown in fig. 9, in the case where the first capacitors are electrically connected between the light emitting element of the target sub-pixel and the enabling module and between the light emitting element of the target sub-pixel and the second voltage terminal, the material of the dielectric layer C10-1 corresponding to the first capacitor C1-1 electrically connected between the light emitting element of the target sub-pixel and the enabling module may include a hole transport type material, and the material of the dielectric layer C10-2 corresponding to the first capacitor C1-2 electrically connected between the light emitting element of the target sub-pixel and the second voltage terminal may include an electron transport type material.

For example, in a case where the first capacitor C1 is electrically connected between the light emitting element of the target sub-pixel and the enable block, the material of the dielectric layer C10 may include the HTM 081. For example, the material of the dielectric layer c10 may be selected from, but not limited to, phthalocyanine derivatives such as CuPc, conductive polymers or polymers containing conductive dopants such as polyphenylenevinylene, polyaniline/dodecylbenzene sulfonic acid (Pani/DBSA), poly (3, 4-ethylenedioxythiophene)/poly (4-styrenesulfonate) (PEDOT/PSS), polyaniline/camphorsulfonic acid (Pani/CSA), polyaniline/poly (4-styrenesulfonate) (Pani/PSS), aromatic amine derivatives, and other hole transport type materials. Illustratively, dielectric layer c10 may also be doped with other materials. For example, the dielectric layer C10 may be doped with a material capable of adjusting the dielectric constant, so as to adjust the dielectric constant of the first capacitor C1, and avoid affecting the light emitting efficiency of the light emitting element. Optionally, the material of dielectric layer c10 may include NDP-9. Optionally, the material of dielectric layer c10 may include NDP-9 and HTM 081.

As described above, the display panel may include the substrate 10, the driving device layer 20, and the light emitting function layer 30, with the dielectric layer C10 disposed between the two plates of the first capacitor C1. In some alternative embodiments, as shown in FIG. 10, the orthographic projection of dielectric layer c10 on substrate 10 overlaps the orthographic projection of light-emitting layer D2 on substrate 10. This makes it easier to implement the equivalent capacitance of the series first capacitor C1 and the target sub-pixel.

Further, an insulating layer 31 may be further disposed between the two reused sub-film layers, where the insulating layer 31 surrounds the dielectric layer c10, and a surface of the insulating layer 31 facing away from the substrate 10 is flush with a surface of the dielectric layer c10 facing away from the substrate 10. That is, the surface of the insulating layer 31 facing away from the substrate 10 and the surface of the dielectric layer c10 facing away from the substrate 10 together constitute a plane, so that the light-emitting layer D2 can be vapor-deposited on the plane. Illustratively, the material of the insulating layer 31 may be the same as that of the pixel defining layer PDL.

Alternatively, the orthographic projection of the dielectric layer c10 on the substrate 10 and the orthographic projection of the light-emitting layer D2 on the substrate 10 may overlap. The capacitance value of the capacitor is related to the facing area of the two polar plates, the dielectric constant of the dielectric layer between the polar plates and the thickness of the dielectric layer, in this application, the orthographic projection of the dielectric layer C10 on the substrate 10 is overlapped with the orthographic projection of the luminescent layer D2 on the substrate 10, that is, the facing area of the two polar plates of the first capacitor C1 is fixed, and under the condition that the dielectric constant of the dielectric layer between the polar plates is fixed, the capacitance value of the first capacitor C1 can be controlled only by controlling the thickness of the dielectric layer C10.

In some alternative embodiments, the thickness of insulating layer 31 is the same as the thickness of dielectric layer c10, so that the surface of insulating layer 31 facing away from substrate 10 is flush with the surface of dielectric layer c10 facing away from substrate 10.

Optionally, the thickness of the insulating layer 31 and the thickness of the dielectric layer c10 range from 1 nm to 10 nm. For example, the thickness of the insulating layer 31 and the thickness of the dielectric layer c10 are all 1 nm, 5 nm, 10 nm, and the like.

In some alternative embodiments, the two plates of the first capacitor may be separately disposed, that is, the first electrode or the second electrode is not reused as the plate of the first capacitor. Referring to fig. 4 and 13 in combination, a first capacitor C1 may be connected in series between the enable module 01 and the light emitting element D of the target sub-pixel, which includes a first electrode D1, a light emitting layer D2, and a second electrode D3, which are stacked. As described above, the display panel may further include the substrate 10 and the driving device layer 20, the enable module 01 and the first capacitor C1 may be disposed in the driving device layer 20, the light emitting element D may be disposed on a side of the driving device layer 20 opposite to the substrate 10, one plate of the first capacitor C1 is connected to the enable module 01, and the other plate of the first capacitor C1 is connected to the first electrode D1.

For example, the same points as those in fig. 13 and fig. 6 are not repeated, except that the driving device layer 20 may further include a fifth metal layer M5, a second planarization layer PLN2 may be disposed between the fifth metal layer M5 and the fourth metal layer M4, and the driving device layer 20 may further include a third planarization layer PLN3 disposed between the second planarization layer PLN2 and the light emitting function layer 30. The first plate C11 of the first capacitor C1 may be disposed on the fourth metal layer M4, and the second plate C12 of the first capacitor C1 may be disposed on the fifth metal layer M5. The first plate c11 is connected to the enable module 01, and the second plate c12 is connected to the first electrode D1.

In addition, fig. 7 and 8 illustrate a case where the first capacitor C1 is electrically connected between the light emitting element D of the target sub-pixel and the second voltage terminal, and the second electrode D3 is multiplexed as one plate of the first capacitor C1, it is understood that when the first capacitor C1 is electrically connected between the light emitting element D of the target sub-pixel and the second voltage terminal, as shown in fig. 14 or 15, the second electrode D3 and the first capacitor C1 may not have a multiplexing relationship.

For example, as shown in fig. 14, the first plate C11 and the second plate C12 of the first capacitor C1 may be both located on a side of the second electrode D3 facing away from the substrate 10, an insulating layer 40 may be disposed between the first plate C11 and the second electrode D3 of the target sub-pixel, and the first plate C11 is connected to the second electrode D3 of the target sub-pixel through a via hole. For example, the second electrode D3 of the target sub-pixel P2 shown in fig. 14 and the second electrodes D3 of the other color sub-pixels P1 and P2 may be independent of each other. An orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate 10 overlaps with an orthogonal projection of the luminescent layer D2 of the target sub-pixel and the second electrode D3 of the target sub-pixel P2 on the substrate 10, and an orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate 10 does not overlap with an orthogonal projection of the luminescent layer D2 of the other color sub-pixels except the target sub-pixel on the substrate 10, so that the target sub-pixel includes the first capacitor C1, and the other color sub-pixels except the target sub-pixel do not include the first capacitor C1.

For another example, as shown in fig. 15, the first plate C11 and the second plate C12 of the first capacitor C1 may be both located on the side of the second electrode D3 facing the substrate 10, the first plate C11 and the second plate C12 of the first capacitor C1 are located on the side of the luminescent layer D2 of the target sub-pixel facing away from the substrate 10, the insulating layer 40 may be disposed between the second plate C12 and the second electrode D3 of the target sub-pixel, and the second plate C12 is connected to the second electrode D3 of the target sub-pixel through a via hole. For example, the second electrodes D3 of the light emitting elements D of the respective colors shown in fig. 15 may also be connected to each other to constitute a planar electrode, an orthogonal projection of the first plate C11 of the first capacitor C1 on the substrate 10 overlaps with the luminescent layer D2 of the target sub-pixel and an orthogonal projection of the second electrode D3 of the target sub-pixel on the substrate 10, and an orthogonal projection of the first plate C11 of the first capacitor C1 on the substrate 10 does not overlap with an orthogonal projection of the luminescent layer D2 of the sub-pixel of the other colors than the target sub-pixel on the substrate 10, so that the target sub-pixel includes the first capacitor C1 and the sub-pixel of the other colors than the target sub-pixel does not include the first capacitor C1.

It should be noted that the above embodiments may be combined with each other without contradiction.

Based on the same inventive concept, as shown in fig. 16 or 17, the embodiment of the present application further provides a pixel circuit, and the pixel circuit may include an enable module 01, a light emitting element D, and a first capacitor C1. The enabling module 01, the first capacitor C1 and the light emitting device D are connected in series between the first voltage terminal PVDD and the second voltage terminal PVEE, and the enabling module 01 is configured to generate a driving current to drive the light emitting device D to emit light. For example, as shown in fig. 16, the first capacitor C1 may be electrically connected between the light emitting element D and the enabling module 01. For another example, as shown in fig. 17, the first capacitor C1 may be electrically connected between the light emitting element D and the second voltage terminal PVEE. For another example, the number of the first capacitors C1 may include at least two, wherein one of the first capacitors C1 may be electrically connected between the light emitting element D and the enabling module 01, and the other one of the first capacitors C1 may be electrically connected between the light emitting element D and the second voltage terminal PVEE.

It is to be understood that the pixel circuit shown in fig. 3 does not include the first capacitance, whereas the pixel circuits shown in fig. 16 and 17 include the first capacitance.

The pixel circuit provided by the embodiment of the application can be used for driving a light-emitting element with a larger capacitance value of an equivalent capacitor, for example, the light-emitting element is a green light-emitting element. The first capacitor connected with the light-emitting element in series is increased, namely the equivalent capacitor corresponding to the light-emitting element is reduced, so that the equivalent capacitor corresponding to the light-emitting element and the equivalent capacitors corresponding to the light-emitting elements of other colors tend to be consistent, the charging time of the light-emitting element and the charging time of the light-emitting elements of other colors tend to be consistent, and the problem of color cast is improved or avoided. For example, when the light emitting element is a green light emitting element, the problem of color shift of red or blue can be avoided.

In some alternative embodiments, taking the first capacitor C1 connected between the light emitting element D and the enabling module 01 as an example, specifically as shown in fig. 18, the enabling module 01 may include a driving sub-module 11, a data writing sub-module 12, a first initialization sub-module 13, a threshold compensation sub-module 14, a first light emitting control sub-module 15, a second light emitting control sub-module 16, a storage sub-module 17, and a second initialization sub-module 18. The driving sub-module 11 is electrically connected to the data writing sub-module 12, the data writing sub-module 12 is configured to write a data voltage into the driving sub-module 11, and the driving sub-module 11 is configured to generate a driving current. The first initialization submodule 13 is electrically connected to the control end of the driving submodule 11, and the first initialization submodule 13 is configured to initialize the control end of the driving submodule 11. The threshold compensation submodule 14 is electrically connected to the control terminal of the driving submodule 11, and the threshold compensation submodule 14 is configured to detect and self-compensate for a threshold voltage deviation in the driving submodule 11. The first light-emitting control sub-module 15 is connected in series between the first voltage terminal PVDD and the driving sub-module 11, the second light-emitting control sub-module 16 is connected in series between the driving sub-module 11 and the light-emitting element D, and the first light-emitting control sub-module 15 and the second light-emitting control sub-module 16 are used for controlling the driving current generated by the driving sub-module 11 to be transmitted to the light-emitting element D. The storage submodule 17 is electrically connected to the control terminal of the driving submodule 11, and the storage submodule 17 is configured to maintain the potential of the control terminal of the driving submodule 11. The second initialization sub-module 18 is used to initialize the first electrode of the light emitting element D.

For example, the control terminal of the first initialization sub-module 13 may be electrically connected to the first SCAN signal terminal SCAN1, and the input terminal of the first initialization sub-module 13 may be electrically connected to the reference signal terminal VREF. The control terminal of the threshold compensation submodule 14 may be electrically connected to the second SCAN signal terminal SCAN 2. The control terminal of the data write submodule 12 may be electrically connected to the second SCAN signal terminal SCAN2, and the input terminal of the data write submodule 12 may be electrically connected to the data signal terminal VDATA. The control terminal of the first lighting control sub-module 15 and the control terminal of the second lighting control sub-module 16 may be connected to the lighting control signal terminal EM. The control terminal of the second initialization sub-module 18 may be electrically connected to the first SCAN signal terminal SCAN1 or the second SCAN signal terminal SCAN2, the input terminal of the second initialization sub-module 18 may be electrically connected to the reference signal terminal VREF, and the other terminal of the second initialization sub-module 18 may be electrically connected to the first plate of the first capacitor C1.

In some alternative embodiments, as shown in fig. 18, the driving sub-module 11 includes a driving transistor T1, the data writing sub-module 12 includes a second transistor T2, the first initialization sub-module 13 includes a third transistor T3, the threshold compensation sub-module 14 includes a fourth transistor T4, the first lighting control sub-module 15 includes a fifth transistor T5, the second lighting control sub-module 16 includes a sixth transistor T6, the storage sub-module 17 includes a storage capacitor Cst, and the second initialization sub-module 18 includes a seventh transistor T7. The gate of the third transistor T3 is electrically connected to the first SCAN signal terminal SCAN1, the first pole of the third transistor T3 is electrically connected to the reference signal terminal VREF, and the second pole of the third transistor T3 is electrically connected to the gate of the driving transistor T1. A gate electrode of the fourth transistor T4 is electrically connected to the second SCAN signal terminal SCAN2, a first electrode of the fourth transistor T4 is electrically connected to the second electrode of the driving transistor T1, and a second electrode of the fourth transistor T4 is electrically connected to the gate electrode of the driving transistor T1. A gate electrode of the second transistor T2 is electrically connected to the second SCAN signal terminal SCAN2, a first electrode of the second transistor T2 is electrically connected to the data signal terminal VDATA, and a second electrode of the second transistor T2 is electrically connected to the first electrode of the driving transistor T1. A gate of the fifth transistor T5 is electrically connected to the emission control signal terminal EM, a first pole of the fifth transistor T5 is electrically connected to the first voltage terminal PVDD, and a second pole of the fifth transistor T5 is electrically connected to the first pole of the driving transistor T1. A gate of the sixth transistor T6 is electrically connected to the emission control signal terminal EM, a first pole of the sixth transistor T6 is electrically connected to the second pole of the driving transistor T1, and a second pole of the sixth transistor T6 is electrically connected to the first electrode of the light emitting element D. A first pole of the storage capacitor Cst is electrically connected to the first voltage terminal PVDD, and a second pole of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T1. A gate of the seventh transistor T7 is electrically connected to the first SCAN signal terminal SCAN1 or the second SCAN signal terminal SCAN2, a first electrode of the seventh transistor T7 is electrically connected to the reference signal terminal VREF, a second electrode of the seventh transistor T7 is electrically connected to a first plate of the first capacitor C1, a second plate of the first capacitor C1 is electrically connected to a first electrode of the light emitting device D, and a second electrode of the light emitting device D is electrically connected to the second voltage terminal PVEE.

It can be understood that fig. 18 only illustrates that the first capacitor C1 is electrically connected between the light emitting element D and the enabling module 01, and the specific structure and connection manner of the enabling module 01 can be as shown in fig. 18 in the case that the first capacitor is electrically connected between the light emitting element D and the second voltage terminal PVEE, or the first capacitor is electrically connected between the light emitting element D and the enabling module 01 and the first capacitor is electrically connected between the light emitting element D and the second voltage terminal PVEE.

For example, the transistors in the pixel circuit may be all P-type transistors or all N-type transistors, or partially P-type transistors and partially N-type transistors, which is not limited in this application.

The application also provides a display device which comprises the display panel or the pixel circuit provided by the embodiment of the application. It is to be understood that, in the case where the display device includes the pixel circuit provided in the embodiment of the present application including the first capacitor, the pixel circuit which may be a sub-pixel of a part of colors in the display device includes the first capacitor, and the pixel circuit of a sub-pixel of another color may not include the first capacitor. In addition, in the case where the first capacitor in the pixel circuit is electrically connected between the light emitting element and the second voltage terminal, the first capacitor may be electrically connected between the light emitting element of a part of the color sub-pixels and the second voltage terminal, and the first capacitor may not be provided between the light emitting element of its color sub-pixel and the second voltage terminal.

Referring to fig. 19, fig. 19 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 19 provides a display device 1000 including the display panel 100 according to any of the above embodiments of the present application. The display device 1000 is described in the embodiment of fig. 19 by taking a mobile phone as an example, but it should be understood that the display device provided in the embodiment of the present application may be other display devices having a display function, such as a wearable product, a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, comprising:

the pixel circuit comprises an enabling module, the enabling module and the light-emitting element are connected between a first voltage end and a second voltage end in series, the sub-pixel of at least one color is a target sub-pixel, and the target sub-pixel further comprises a first capacitor which is connected between the enabling module and the second voltage end in series with the light-emitting element of the target sub-pixel.

2. The display panel according to claim 1, wherein the light-emitting element of the target sub-pixel includes a first electrode, a light-emitting layer, and a second electrode, which are stacked, the first electrode being electrically connected to the first voltage terminal through the enable module, the second electrode being electrically connected to the second voltage terminal;

the first capacitor is electrically connected between the light emitting element of the target sub-pixel and the enabling module,

and/or the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the second voltage end;

preferably, the first capacitor is electrically connected between the light emitting element of the target sub-pixel and the enabling module, and the first electrode is multiplexed as at least one plate of the first capacitor;

3. The display panel according to claim 2, wherein the first electrode comprises at least two sub-film layers arranged in a stacked manner, one of any two adjacent sub-film layers is reused as one plate of the first capacitor, and the other sub-film layer is reused as the other plate of the first capacitor.

4. The display panel according to claim 2 or 3, wherein a dielectric layer is disposed between two plates of the first capacitor;

the dielectric layer is made of an electron-transporting material under the condition that the first capacitor is electrically connected between the light-emitting element of the target sub-pixel and the second voltage terminal.

5. The display panel according to claim 3, wherein the display panel comprises a substrate, and a dielectric layer is arranged between two plates of the first capacitor;

the orthographic projection of the dielectric layer on the substrate is overlapped with the orthographic projection of the light emitting layer on the substrate, an insulating layer is further arranged between the two multiplexed sub-film layers, the insulating layer surrounds the dielectric layer, and the surface of the insulating layer, which faces away from the substrate, is flush with the surface of the dielectric layer, which faces away from the substrate;

6. The display panel according to claim 5, wherein the insulating layer has the same thickness as the dielectric layer;

preferably, the thickness of the insulating layer and the thickness of the dielectric layer range from 1 nanometer to 10 nanometers.

7. The display panel according to claim 1, wherein the first capacitor is connected in series between the enable module and the light emitting element of the target sub-pixel, and the light emitting element of the target sub-pixel comprises a first electrode, a light emitting layer, and a second electrode which are stacked;

8. The display panel of claim 1, wherein the pixel unit comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and at least one of the green sub-pixel, the red sub-pixel, and the blue sub-pixel is the target sub-pixel;

preferably, the green sub-pixel is the target sub-pixel, and the green sub-pixel is turned on synchronously with the red sub-pixel and/or the blue sub-pixel.

9. A pixel circuit, comprising: the circuit comprises an enabling module, a light-emitting element and a first capacitor;

the enabling module, the first capacitor and the light emitting element are connected in series between a first voltage terminal and a second voltage terminal, and the first capacitor is electrically connected between the light emitting element and the enabling module, and/or the first capacitor is electrically connected between the light emitting element and the second voltage terminal; the enabling module is used for generating a driving current to drive the light-emitting element to emit light.

10. A display device comprising the display panel according to any one of claims 1 to 8 or comprising the pixel circuit according to claim 9.