CN111477188A - Pixel driving circuit, pixel driving method and display device - Google Patents
Pixel driving circuit, pixel driving method and display device Download PDFInfo
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- CN111477188A CN111477188A CN202010391695.6A CN202010391695A CN111477188A CN 111477188 A CN111477188 A CN 111477188A CN 202010391695 A CN202010391695 A CN 202010391695A CN 111477188 A CN111477188 A CN 111477188A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
Abstract
The embodiment of the application discloses a pixel driving circuit, a pixel driving method and a display device, wherein the pixel driving circuit comprises: the device comprises a first control unit, a second control unit and a signal source; the first control unit is connected with the pixel array and outputs a first control signal, and the first control signal is used for gating M rows of pixels from M rows of pixels of the pixel array, wherein M and M are integers more than 1; the second control unit outputs a second control signal, and the second control signal is used for gating N columns of pixels from N columns of pixels of the m rows of pixels when the m rows of pixels are gated, so that the signal source charges the gated N columns of pixels at the same time, wherein N and N are integers larger than 0. Therefore, the simultaneous charging of multiple rows of pixels at the same time can be realized, the charging time is prolonged, the high-refresh-rate display of the display screen is realized, and the problems of abnormal display, color cast and the like are further solved.
Description
Technical Field
The present disclosure relates to display technologies, and in particular, to a pixel driving circuit, a pixel driving method, and a display device.
Background
With the continuous development of the Display technology of liquid Crystal Display (L liquid Crystal Display, L CD), the requirements of the Display quality and performance of the Display become higher and higher, and an important factor determining the Display performance of the Display is the circuit design and arrangement of the pixels inside the Display.
In the existing pixel driving circuit design scheme, every three pixels (R, G, B pixels) in a row of pixels share the same Source signal in a time-sharing manner, R, G, B pixels are charged in one gating time, each pixel charging time is about 1/3 of one gating time, and for high-frequency display, display abnormality easily caused by insufficient pixel charging is caused, so that the problem of insufficient pixel charging in L CD needs to be solved urgently.
Disclosure of Invention
In order to solve the above technical problem, embodiments of the present application are directed to providing a pixel driving circuit, a pixel driving method and a display device.
The technical scheme of the application is realized as follows:
in a first aspect, the present application provides a pixel driving circuit comprising: the device comprises a first control unit, a second control unit and a signal source;
the first control unit is connected with the pixel array and outputs a first control signal, the first control signal is used for gating M rows of pixels from M rows of pixels of the pixel array, and both M and M are integers greater than 1;
the second control unit outputs a second control signal, and the second control signal is used for gating N columns of pixels from N columns of pixels of the m rows of pixels when the m rows of pixels are gated, so that the signal source charges the gated N columns of pixels at the same time, wherein N and N are both integers greater than 0.
In a second aspect, the present application provides a pixel driving method for driving the aforementioned pixel driving circuit, the method comprising:
outputting a first control signal through the first control unit;
gating M rows of pixels from M rows of pixels of the pixel array based on the first control signal, wherein M and M each take an integer greater than 1;
outputting a second control signal by the second control unit;
when the m rows of pixels are strobed, N columns of pixels are strobed from N columns of pixels of the m rows of pixels based on the second control signals;
and simultaneously charging the gated N columns of pixels by using a signal source, wherein N and N are integers which are more than 0.
In a third aspect, the present application provides a display device, which is characterized by comprising a pixel array and the aforementioned pixel driving circuit.
The embodiment of the application provides a pixel driving circuit, a pixel driving method and a display device, wherein the pixel driving circuit comprises: the device comprises a first control unit, a second control unit and a signal source; the first control unit is connected with the pixel array and outputs a first control signal, the first control signal is used for gating M rows of pixels from M rows of pixels of the pixel array, and both M and M are integers greater than 1; the second control unit outputs a second control signal, and the second control signal is used for gating N columns of pixels from N columns of pixels of the m rows of pixels when the m rows of pixels are gated, so that the signal source charges the gated N columns of pixels at the same time, wherein N and N are both integers greater than 0. Therefore, the pixels of multiple rows can be charged at the same time, the charging time is prolonged, the display screen can display at a high refresh rate, and the problems of abnormal display, color cast and the like caused by insufficient charging are further solved.
Drawings
FIG. 1 is a schematic diagram of a first theoretical structure of a pixel driving circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a second theoretical structure of a pixel driving circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a third theoretical structure of a pixel driving circuit according to an embodiment of the present disclosure;
FIG. 4 is a diagram illustrating a fourth theoretical structure of a pixel driving circuit according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a fifth theoretical structure of a pixel driving circuit in an embodiment of the present application;
FIG. 6 is a flowchart illustrating a pixel driving method according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a display device in an embodiment of the present application.
Detailed Description
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
The embodiment of the present application provides a pixel driving circuit, and fig. 1 is a schematic diagram of a first theoretical structure of the pixel driving circuit in the embodiment of the present application, and as shown in fig. 1, the pixel driving circuit: a first control unit 11, a second control unit 12 and a signal source 13;
the first control unit 11 is connected to the pixel array 14, and the first control unit 11 outputs a first control signal, where the first control signal is used to gate M rows of pixels from M rows of pixels in the pixel array 14, where M and M are both integers greater than 1, and M is less than or equal to M;
the second control unit 12 outputs a second control signal, where the second control signal is used to gate N columns of pixels from N columns of pixels in the M rows of pixels when the M rows of pixels are gated, so that the signal source 13 charges the gated N columns of pixels at the same time, where N and N are both integers greater than 0, and N is less than or equal to M.
In the embodiment of the present application, the pixel array includes M × N pixels, i.e., M rows of pixels and N columns of pixels, where M and N may be equal or different, the pixel array includes at least one pixel, each of which is used to absorb optical signals with different wavelengths, where the same column of pixels includes the same or different pixels, here, the pixel array may be composed of one or more of R, G, B three pixels, and the arrangement of R, G, B may be a bayer array or other array.
Here, the M rows of pixels are selected from M rows of pixels, and the M rows of pixels may be adjacent rows of pixels, or non-adjacent M rows of pixels selected according to a preset selection mode, where each row of pixels is equally spaced or unequally spaced when not adjacent. The N columns of pixels are selected from the N columns of pixels, the N columns of pixels can be adjacent columns of pixels, or non-adjacent N columns of pixels can be selected according to a preset selection mode, and when the N columns of pixels are not adjacent, each column of pixels are equally spaced or unequally spaced.
Here, the signal source is connected to the pixel array for charging pixels in the pixel array.
In some embodiments, the signal source may charge a plurality of pixels simultaneously, for example, the signal source includes at least one sub-signal source. A plurality of pixels correspond to one sub-signal source, namely, the plurality of pixels can be charged simultaneously by using one sub-signal source. Under the condition, the display scenes of a plurality of pixels are required to be the same, so that the power consumption and the charging condition of the pixels are also the same, the pixels can be simultaneously charged by adopting one signal source, the number of sub-signal sources can be saved, and the cost of the display device can be saved.
For example, the signal source comprises m × N sub signal sources, which respectively correspond to each pixel in the gated m rows of pixels, or the signal source comprises m × N sub signal sources, the m × N sub signal sources respectively correspond to m × N pixels in the gated N columns of pixels, and the m × N sub signal sources can be multiplexed by other non-gated columns of pixels.
Specifically, the driving circuit further includes a switch unit, wherein a first end of the switch unit is connected to each pixel in the pixel array, a second end of the switch unit is connected to the signal source, and a control end of the switch unit is connected to the second control unit; the second control unit controls the on and off of the subswitches in the switch unit through the control end so as to enable the charging path between the signal source and the n columns of pixels to be on.
Here, the switching unit is provided to time-division multiplex the same sub-signal source by the plurality of column pixels, thereby reducing the number of sub-signal sources and saving the cost of the display device.
In some embodiments, the switch unit includes N switch groups, each switch group includes m sub-switches, and each switch group corresponds to a column of pixels; the first ends of the m sub-switches in each switch group are respectively connected with the m pixels in a corresponding column of pixels.
That is, the sub-switch connected to the pixel is used to gate the charging path, the charging path is turned on when the sub-switch is closed, the sub-signal source connected to the pixel charges the sub-signal source, the charging path is turned off when the sub-switch is closed, and the sub-signal source connected to the pixel does not charge the sub-signal source.
In some embodiments, the control terminals of all the sub-switches in the n switch groups corresponding to every n columns of pixels in the pixel array are connected to one signal output terminal of the second control unit; the second control signals output by the different signal output ends are used for controlling the conduction of the connected n switch groups so as to gate the corresponding n columns of pixels.
That is to say, the P second control signals output by the P signal output terminals at different time intervals respectively control the corresponding n different switch groups to be turned on at different time intervals, so that the signal source charges the n columns of pixels connected to the n different switch groups.
In some embodiments, the signal source includes n signal source groups, each signal source group corresponds to one column of pixels, and each signal source group includes m sub-signal sources respectively corresponding to m pixels in one column of pixels; when the switch group corresponding to the same column of pixels is connected with the signal source group, the second ends of the m subswitches in the switch group are respectively connected with the m subswitches in the signal source group; when the gated n columns of pixels are charged, the second control unit controls the conduction of the n switch groups corresponding to the n columns of pixels, so that the corresponding n signal source groups simultaneously charge the corresponding pixels in the n columns of pixels.
That is to say, N signal source groups are multiplexed to every N columns of pixels in the N columns of pixels, and m sub-signal sources in each signal source group respectively charge m pixels in the corresponding column of pixels.
Therefore, the pixel driving circuit can charge multiple rows of pixels at the same time, so that the charging time is prolonged, the display screen can realize high-refresh-rate display, and the problems of abnormal display, color cast and the like caused by insufficient charging are further solved.
Fig. 2 is a schematic diagram of a second theoretical structure of a pixel driving circuit in an embodiment of the present application, and as shown in fig. 2, assuming that a signal source group is multiplexed for every two columns of pixels, for example, two kinds of pixels of red and green are included in m rows of pixels, when the m rows of pixels are gated by a first control signal (Gate1), 2 switch groups are controlled to be turned on by second control signals (CKH1 and CKH2), where m is 3, and the sub-switch 1, the sub-switch 2, and the sub-switch 3 included in the first switch group, and the sub-switch 4, the sub-switch 5, and the sub-switch 6 included in the second switch group are respectively controlled to be turned on. The signal source group comprises a sub-signal source S1, a sub-signal source S2 and a sub-signal source S3. The Gate1 signal is a row driving signal for controlling the charging switch of each pixel in a certain row, the CKH signal is a control signal of a switch group, a control Source signal can be input to the electrode of the corresponding pixel, and the S signal represents the data voltage output by the driving IC and is input to the corresponding pixel by the switch group through time division multiplexing.
For the pixels marked in fig. 2, when the voltage of Gate1 is high, the other Gate signals are low, CKH1 is high, CKH2 and CKH3 are low, the sub-switches 1, 2 and 3 are turned off, S1, S2 and S3 charge the red pixels in the rows 1, 2 and 3 in the first column respectively, and the red pixels in the same column are charged simultaneously.
Similarly, when the voltage of the Gate1 is high, the other Gate signals are low, the CKH2 is high, the CKH1 and the CKH3 are low, the sub-switches 4, 5 and 6 are turned off, the sub-switches S1, the sub-switches S2 and the sub-switches S3 respectively charge the green pixels in the rows 1, 2 and 3 in the second column, and the green pixels in the same column are charged simultaneously.
Fig. 3 is a schematic diagram of a third theoretical structure of a pixel driving circuit in an embodiment of the present application, where fig. 3 is a schematic diagram of a column of blue pixels added to fig. 2, that is, one signal source group is multiplexed every three columns of pixels, when m rows of pixels are gated by a first control signal (Gate1), 3 switch groups are controlled to be turned on by second control signals (CKH1, CKH2, and CKH3), where m is 3, a sub-switch 1, a sub-switch 2, and a sub-switch 3 included in the first switch group, a sub-switch 4, a sub-switch 5, and a sub-switch 6 included in the second switch group, and a sub-switch 7, a sub-switch 8, and a sub-switch 9 included in the third switch group. The three pixels of red, green and blue correspond to a signal source group, and the signal source group comprises a sub signal source S1, a sub signal source S2 and a sub signal source S3. The Gate1 signal is a row driving signal for controlling the charging switch of each pixel in a certain row, the CKH signal is a control signal of a switch group, a control Source signal can be input to the electrode of the corresponding pixel, and the S signal represents the data voltage output by the driving IC and is input to the corresponding pixel by the switch group through time division multiplexing.
For the pixels marked in fig. 3, when the voltage of Gate1 is high, the other Gate signals are low, CKH3 is high, CKH1 and CKH2 are low, the sub-switches 7, 8 and 9 are closed, S1, S2 and S3 charge the blue pixels in the rows 1, 2 and 3 in the third column, and the blue pixels in the same column are charged simultaneously.
It should be noted that, multiple columns of pixels may be selected to multiplex one signal source group according to actual situations, or one signal source group may be set for each column of pixels.
It should be noted that each column of pixels corresponds to a switch group, at least two columns of pixels multiplex a signal source group, fig. 2 and 3 schematically show pixel driving circuits of two columns of m rows and three columns of m rows for the sake of explanation, and other pixels have the same principle. Fig. 2 and fig. 3 only show schematic diagrams of the sub-switches, and any device capable of implementing a switch control function in practical applications can be applied to the pixel driving circuit of the present application.
In some embodiments, the sub-switches are data selectors. For example, the sub-switch is a field effect transistor, a drain of the field effect transistor is connected with the pixel, a source of the field effect transistor is connected with the sub-signal source, and a gate of the field effect transistor is connected with the second control unit.
Here, the fet is a Metal Oxide Semiconductor (MOS) fet, and when the gate of the fet is at a high level, the fet is turned on, the sub-signal source charges the pixel, and when the gate of the fet is at a high level, the fet is turned off. In practical application, the P-type field effect transistor can be selected as a switching device according to an actual signal source and the voltage of the second control unit.
Fig. 4 is a schematic diagram of a fourth theoretical structure of a pixel driving circuit in an embodiment of the present application, as shown in fig. 4, in which every three rows of pixels are multiplexed with a signal source set, a pixel array includes M rows and N columns, for example, only six rows and six columns are taken out, the Gate signal is a row driving signal and controls the charging switch of each pixel of a certain row, the Gate1 gates the 1 st to 3 rd rows, the Gate2 gates the 4 th to 6 th rows, in this way, CKH (including CKH1, CKH2, and CKH3) signals are control signals of the switch group, and are respectively used for gating the red pixel column, the green pixel column, and the blue pixel column to realize time-division multiplexing of the signal Source group, the second control signal controls the Source signal to be input to the electrode of the corresponding pixel by controlling a data selector (MUX), and the Source signal represents the data voltage output by the driving IC and is input to the corresponding pixel by time-division multiplexing of the MUX switch.
When the first three rows of pixels are gated through the Gate1, the switching groups are controlled to be turned on through the CKH1, CKH2 and CKH3, the pixels in the 1 st to 3 rd columns correspond to the signal source group 1, the signal source group 1 comprises the sub-signal source S1, the sub-signal source S2 and the sub-signal source S3, the pixels in the 4 th to 6 th columns correspond to the signal source group 2, and the signal source group 2 comprises the sub-signal source S4, the sub-signal source S5 and the sub-signal source S6.
When the voltage of the Gate1 is high, the other Gate signals are low, the CKH1 is high, the CKH2 and the CKH3 are low, the sub MUX switches 1, 2, 3, 10, 11 and 12 are turned off, the S1, the S2 and the S3 charge the red pixels in the rows 1, 2 and 3 in the first column, and the S4, the S5 and the S6 charge the red pixels in the rows 1, 2 and 3 in the fourth column.
Similarly, when the voltage of the Gate1 is high, the other Gate signals are low, the CKH2 is high, and the CKH1 and CKH3 are low, the sub-MUX switches 4, 5, 6, 13, 14 and 15 are turned off, the S1, the S2 and the S3 charge the green pixels in the 1 st, 2 nd and 3 rd rows in the second column, and the S4, the S5 and the S6 charge the green pixels in the 1 st, 2 nd and 3 rd rows in the fifth column, respectively.
Similarly, when the voltage of the Gate1 is high, the other Gate signals are low, the CKH3 is high, and the CKH1 and CKH2 are low, the sub-MUX switches 7, 8, 9, 16, 17 and 18 are turned off, the S1, the S2 and the S3 charge the blue pixels in the rows 1, 2 and 3 in the third column, and the S4, the S5 and the S6 charge the blue pixels in the rows 1, 2 and 3 in the sixth column, respectively.
When the voltage of the Gate2 is at a high level and the other Gate signals are at a low level, the gating modes of the CKH1, the CKH2 and the CKH3 for controlling the row pixels are the same as the gating modes of the Gate1, and the description thereof is omitted.
It should be noted that the arrangement of R, G, B may be in the form of a bayer array or other arrays, fig. 5 is a schematic diagram of a fifth theoretical structure of a pixel driving circuit in the embodiment of the present application, and as shown in fig. 5, the pixel array is a bayer array.
When the first three rows of pixels are gated through the Gate1, the switching groups are controlled to be turned on through the CKH1, CKH2 and CKH3, the pixels in the 1 st to 3 rd columns correspond to the signal source group 1, the signal source group 1 comprises the sub-signal source S1, the sub-signal source S2 and the sub-signal source S3, the pixels in the 4 th to 6 th columns correspond to the signal source group 2, and the signal source group 2 comprises the sub-signal source S4, the sub-signal source S5 and the sub-signal source S6.
When the voltage of the Gate1 is high, the other Gate signals are low, the CKH1 is high, the CKH2 and the CKH3 are low, the sub MUX switches 1, 2, 3, 10, 11 and 12 are turned off, the sub MUX switches S1, S2 and S3 charge the pixels in the rows 1, 2 and 3 in the first column, and the sub MUX switches S4, S5 and S6 charge the pixels in the rows 1, 2 and 3 in the fourth column.
Similarly, when the voltage of the Gate1 is high, the other Gate signals are low, the CKH2 is high, and the CKH1 and CKH3 are low, the sub-MUX switches 4, 5, 6, 13, 14 and 15 are turned off, the S1, the S2 and the S3 charge the pixels in the 1 st, 2 nd and 3 rd rows in the second column, and the S4, the S5 and the S6 charge the pixels in the 1 st, 2 nd and 3 rd rows in the fifth column, respectively.
Similarly, when the voltage of the Gate1 is high, the other Gate signals are low, the CKH3 is high, and the CKH1 and CKH2 are low, the sub-MUX switches 7, 8, 9, 16, 17 and 18 are turned off, the S1, the S2 and the S3 charge the pixels in the 1 st, 2 nd and 3 rd rows in the third column, and the S4, the S5 and the S6 charge the pixels in the 1 st, 2 nd and 3 rd rows in the sixth column, respectively.
When the voltage of the Gate2 is at a high level and the other Gate signals are at a low level, the gating modes of the CKH1, the CKH2 and the CKH3 for controlling the row pixels are the same as the gating modes of the Gate1, and the description thereof is omitted.
In the prior art, the charging time of each row of pixels is proportional to (1/F)/G, wherein F represents the display refresh frame rate, G represents the number of gates, and 1/F is the charging time of one frame of picture, the charging time is sufficient for 60Hz at present, but the charging time is seriously insufficient for 90Hz/120 Hz.
In the application, under the condition that the charging time of one frame of picture is not changed, because m rows of pixels are charged simultaneously, the Gate gating time can be prolonged by m times, m rows of pixels are charged simultaneously within one Gate time, the charging time of each row of pixels is proportional to (m/F)/G, and for each pixel, the charging time is prolonged by m times, so that the problem of insufficient charging during high-frequency display is solved.
Therefore, the pixel driving circuit can charge multiple rows of pixels at the same time, so that the charging time is prolonged, the display screen can realize high-refresh-rate display, and the problems of abnormal display, color cast and the like caused by insufficient charging are further solved.
Based on the pixel driving circuit, an embodiment of the present application further provides a pixel driving method, where the pixel driving method is used to drive the pixel driving circuit, fig. 6 is a schematic flow chart of the pixel driving method in the embodiment of the present application, and as shown in fig. 6, the method includes:
step 601: controlling the first control unit to output a first control signal;
step 602: gating M rows of pixels from M rows of pixels of the pixel array based on the first control signal, wherein M and M each take an integer greater than 1;
step 603: controlling the second control unit to output a second control signal;
step 604: when the m rows of pixels are strobed, N columns of pixels are strobed from N columns of pixels of the m rows of pixels based on the second control signals;
step 605: and simultaneously charging the gated N columns of pixels by using a signal source, wherein N and N are integers which are more than 0.
In the embodiment of the present application, the pixel array includes M × N pixels, i.e., M rows of pixels and N columns of pixels, where M and N may be equal or different, the pixel array includes at least one pixel, each of which is used to absorb optical signals with different wavelengths, where the same column of pixels includes the same or different pixels, here, the pixel array may be composed of one or more of R, G, B three pixels, and the arrangement of R, G, B may be a bayer array or other array.
Here, the pixel driving circuit includes: the device comprises a first control unit, a second control unit and a signal source; the first control unit is connected with the pixel array, and the signal source is connected with each pixel electrode in the pixel array through the switch unit.
Here, the driving circuit further includes a switch unit, wherein a first terminal of the switch unit is connected to each pixel in the pixel array, a second terminal of the switch unit is connected to the signal source, and a control terminal of the switch unit is connected to the second control unit; the second control unit controls the on and off of the subswitches in the switch unit through the control end so as to enable the charging path between the signal source and the n columns of pixels to be on.
In some embodiments, the switch unit includes N switch groups, each switch group includes m sub-switches, and each switch group corresponds to a column of pixels; the first ends of the m sub-switches in each switch group are respectively connected with the m pixels in a corresponding column of pixels.
In some embodiments, the second control unit includes P signal output terminals for outputting P second control signals, where N is P × N, the control terminals of all the sub-switches in the N switch groups corresponding to every N columns of pixels in the pixel array are connected to one signal output terminal of the second control unit, and the second control signals output by different signal output terminals are used for controlling the N connected switch groups to be turned on so as to gate the corresponding N columns of pixels.
In some embodiments, the signal source includes n signal source groups, each signal source group corresponds to one column of pixels, and each signal source group includes m sub-signal sources respectively corresponding to m pixels in one column of pixels; when the switch group corresponding to the same column of pixels is connected with the signal source group, the second ends of the m subswitches in the switch group are respectively connected with the m subswitches in the signal source group; when the gated n columns of pixels are charged, the second control unit controls the conduction of the n switch groups corresponding to the n columns of pixels, so that the corresponding n signal source groups simultaneously charge the corresponding pixels in the n columns of pixels.
In some embodiments, the sub-switches are data selectors. For example, the sub-switch is a field effect transistor, a drain of the field effect transistor is connected with the pixel, a source of the field effect transistor is connected with the sub-signal source, and a gate of the field effect transistor is connected with the second control unit.
In some embodiments, the M rows of pixels include at least one pixel, each for absorbing a different wavelength of light signal.
In some embodiments, the first control unit comprises Q signal outputs for outputting Q first control signals, wherein M is Q × M;
every m rows of pixels in the pixel array are connected with one signal output end of the first control unit, wherein first control signals output by different signal output ends are used for gating the corresponding m rows of pixels.
By adopting the pixel driving method, the simultaneous charging of multiple rows of pixels at the same time can be realized, so that the charging time is prolonged, the high-refresh-rate display of the display screen is realized, and the problems of abnormal display, color cast and the like caused by insufficient charging are further solved.
Based on the pixel driving circuit, an embodiment of the present application further provides a display device, as shown in fig. 7, the display device includes: a pixel array 71 and a pixel driving circuit 72, wherein the pixel driving circuit is any of the pixel driving circuits described above.
In practical application, the display device number comprises: a processor 73 and a memory 74 configured to store a computer program capable of running on the processor; wherein the processor 73 is configured to execute the steps of the pixel driving method in the previous embodiments when running the computer program.
In practice, of course, the various components of the display device are coupled together by a bus system 75, as shown in FIG. 7. It will be appreciated that the bus system 75 is used to enable connected communication between these components. The bus system 75 includes, in addition to the data bus, a power bus, a control bus, and a status signal bus. For clarity of illustration, however, the various buses are labeled as bus system 75 in fig. 7.
In practical applications, the processor may be at least one of an Application Specific Integrated Circuit (ASIC), a Digital Signal Processing Device (DSPD), a Programmable logic Device (P L D, a Programmable L ic Device), a Field-Programmable Gate Array (FPGA), a controller, a microcontroller, and a microprocessor.
The Memory may be a volatile Memory (volatile Memory), such as a Random-Access Memory (RAM); or a non-volatile Memory (non-volatile Memory), such as a Read-Only Memory (ROM), a flash Memory (flash Memory), a Hard Disk (HDD), or a Solid-State Drive (SSD); or a combination of the above types of memories and provides instructions and data to the processor.
The technical solutions described in the embodiments of the present application can be arbitrarily combined without conflict.
In the several embodiments provided in the present application, it should be understood that the disclosed embodiments of the first control unit, the second control unit and the signal source are only illustrative to describe the implementation principle of the pixel driving circuit of the present application, and do not limit the actual implementation circuit, and the actual circuit may also be implemented in other ways. The pixel driving circuit implemented on the basis of the above basic principles of the present application shall be covered by the protection scope of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application.
Claims (10)
1. A pixel driving circuit, comprising: the device comprises a first control unit, a second control unit and a signal source;
the first control unit is connected with the pixel array and outputs a first control signal, the first control signal is used for gating M rows of pixels from M rows of pixels of the pixel array, and both M and M are integers greater than 1;
the second control unit outputs a second control signal, and the second control signal is used for gating N columns of pixels from N columns of pixels of the m rows of pixels when the m rows of pixels are gated, so that the signal source charges the gated N columns of pixels at the same time, wherein N and N are both integers greater than 0.
2. The pixel driving circuit according to claim 1, further comprising a switching unit, wherein,
the first end of the switch unit is connected with each pixel in the pixel array, the second end of the switch unit is connected with the signal source, and the control end of the switch unit is connected with the second control unit;
the second control unit controls the on and off of the subswitches in the switch unit through the control end so as to enable the charging path between the signal source and the n columns of pixels to be on.
3. The pixel driving circuit according to claim 2, wherein the switch unit comprises N switch groups, each switch group comprises m sub-switches, and each switch group corresponds to a column of pixels;
the first ends of the m sub-switches in each switch group are respectively connected with the m pixels in a corresponding column of pixels.
4. The pixel driving circuit according to claim 3, wherein the second control unit comprises P signal output terminals for outputting P second control signals, wherein N is P × N;
the control ends of all the sub-switches in the n switch groups corresponding to every n columns of pixels in the pixel array are connected with one signal output end of the second control unit; the second control signals output by the different signal output ends are used for controlling the conduction of the connected n switch groups so as to gate the corresponding n columns of pixels.
5. The pixel driving circuit according to claim 4, wherein the signal source comprises n signal source groups, each signal source group corresponds to one column of pixels, and each signal source group comprises m sub-signal sources respectively corresponding to m pixels in one column of pixels;
when the switch group corresponding to the same column of pixels is connected with the signal source group, the second ends of the m subswitches in the switch group are respectively connected with the m subswitches in the signal source group;
when the gated n columns of pixels are charged, the second control unit controls the conduction of the n switch groups corresponding to the n columns of pixels, so that the corresponding n signal source groups simultaneously charge the corresponding pixels in the n columns of pixels.
6. The pixel driving circuit according to claim 3, wherein the sub-switches are field effect transistors, the drains of the field effect transistors are connected to the pixels, the sources are connected to the sub-signal sources, and the gates are connected to the second control unit.
7. The pixel driving circuit according to claim 1, wherein the M rows of pixels comprise at least one pixel, each pixel for absorbing light signals of different wavelengths.
8. The pixel driving circuit according to claim 1, wherein the first control unit comprises Q signal outputs for outputting Q first control signals, wherein M is Q × M;
every m rows of pixels in the pixel array are connected with one signal output end of the first control unit, wherein first control signals output by different signal output ends are used for gating the corresponding m rows of pixels.
9. A pixel driving method for driving the pixel driving circuit according to any one of claims 1 to 8, the method comprising:
controlling the first control unit to output a first control signal;
gating M rows of pixels from M rows of pixels of the pixel array based on the first control signal, wherein M and M each take an integer greater than 1;
controlling the second control unit to output a second control signal;
when the m rows of pixels are strobed, N columns of pixels are strobed from N columns of pixels of the m rows of pixels based on the second control signals;
and simultaneously charging the gated N columns of pixels by using a signal source, wherein N and N are integers which are more than 0.
10. A display device comprising an array of pixels and a pixel drive circuit as claimed in any one of claims 1 to 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023256A (en) * | 2021-10-18 | 2022-02-08 | 云谷（固安）科技有限公司 | Display panel, pixel circuit and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783128A (en) * | 2010-04-02 | 2010-07-21 | 福州华映视讯有限公司 | Method for driving liquid crystal display |
| CN102236223A (en) * | 2010-04-20 | 2011-11-09 | 友达光电股份有限公司 | Displayer and display panel thereof |
| US20170148404A1 (en) * | 2015-05-26 | 2017-05-25 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel, display device, and driving method |
| CN108279539A (en) * | 2018-02-24 | 2018-07-13 | 惠科股份有限公司 | A kind of array substrate and display device |
| CN109637414A (en) * | 2018-12-28 | 2019-04-16 | 厦门天马微电子有限公司 | A kind of display panel, drive circuit and its driving method, display device |
-
2020
- 2020-05-11 CN CN202010391695.6A patent/CN111477188A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101783128A (en) * | 2010-04-02 | 2010-07-21 | 福州华映视讯有限公司 | Method for driving liquid crystal display |
| CN102236223A (en) * | 2010-04-20 | 2011-11-09 | 友达光电股份有限公司 | Displayer and display panel thereof |
| US20170148404A1 (en) * | 2015-05-26 | 2017-05-25 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Liquid crystal display panel, display device, and driving method |
| CN108279539A (en) * | 2018-02-24 | 2018-07-13 | 惠科股份有限公司 | A kind of array substrate and display device |
| CN109637414A (en) * | 2018-12-28 | 2019-04-16 | 厦门天马微电子有限公司 | A kind of display panel, drive circuit and its driving method, display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114023256A (en) * | 2021-10-18 | 2022-02-08 | 云谷（固安）科技有限公司 | Display panel, pixel circuit and display device |
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