CN114019339B - Calibration method and calibration device for programmable Josephson junction array bias driver - Google Patents
Calibration method and calibration device for programmable Josephson junction array bias driver Download PDFInfo
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Abstract
The invention discloses a calibration method and a calibration device of a programmable Josephson junction array bias driver, and the calibration device of the programmable Josephson junction array bias driver comprises the following steps: the error acquisition module is used for acquiring error values of output voltages of all driving channels of the PJVS array bias driver; the multi-way switch module is used for controlling the error acquisition module to work on each driving channel of the PJVS array bias driver; the calibration control module generates error correction parameters of all driving channels of the PJVS array bias driver based on the error values of all driving channels acquired by the error acquisition module; the calibration control module includes: a digital control module and a DAC output control module. The invention has the beneficial effects that: the correction parameters are used for correcting the output voltage of each output channel of the PJVS junction array driver, so that errors from the DAC and the resistor network are eliminated integrally, the complexity of independent calibration is avoided, and the calibration precision is ensured.
Description
Technical Field
The invention relates to the field of programmable Josephson junction array bias drivers, in particular to a calibration method and a calibration device of a programmable Josephson junction array bias driver.
Background
The programmable Josephson junction array bias driver (abbreviated as PJVS junction array bias driver hereinafter) is an important component for synthesizing quantum voltage signals, when the programmable Josephson junction array chip is driven by using the bias driver, voltage difference is formed at two ends of the sub-junction array through two adjacent channels, and bias current required for driving each section of sub-junction array is generated after buffering, so that the bias state of each section of sub-junction array is controlled; however, as the DAC voltage output and the resistor of each channel have certain instability, the current value can drift along with time, and the accuracy is reduced, so that the actual driving requirement cannot be met; therefore, a calibration device is needed to calibrate the output current of the PJVS junction array bias driver.
The PJVS array bias driver is provided with a plurality of expandable output channels, and the channels are related to each other; and the current output of the PJVS junction array bias driver is converted by the DAC digital-to-analog conversion module and the resistor network, so that the error of the current output is derived from the DAC digital-to-analog conversion module and the resistor network. Because of the large number of channels and the relatively complex resistor network, if all sources of error are calibrated individually to achieve calibration of the output current, the actual resistance error is difficult to estimate and introduces unnecessary errors, resulting in reduced accuracy of the current calibration.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention aims to provide a self-calibration method and a self-calibration device of a PJVS (pulse-width modulation) junction array bias driver, which are used for solving the problems of complex calculation caused by inter-channel correlation in the actual calibration process and new errors introduced in the independent calibration of error sources.
In order to achieve the above object, the present invention provides a calibration device of a programmable josephson junction array bias driver, for calibrating a PJVS junction array bias driver, the PJVS junction array bias driver including a plurality of driving channels, the driving channels including a digital-to-analog conversion module, one of the driving channels being set as a reference channel, and the other channels being non-reference channels, the calibration device comprising:
the error acquisition module is used for acquiring error values of output voltages of all driving channels of the PJVS array bias driver;
a multi-way switch module; the driving channels are used for controlling the error acquisition module to work on the PJVS array bias driver;
a calibration control module; generating error correction parameters of each driving channel of the PJVS array bias driver based on the error values of each driving channel acquired by the error acquisition module; the calibration control module includes:
the digital control module is used for controlling the conduction state of the multi-way switch module;
the DAC output control module is used for controlling the output voltage value of the digital-to-analog conversion module;
the input end of the calibration control module is electrically connected with the output end of the error acquisition module, the output end of the calibration control module is electrically connected with the input end of the PJVS array bias driver, the input end of the error acquisition module is electrically connected with the output end of the multi-way switch module, the control end of the multi-way switch module is electrically connected with the output end of the digital control module, and the input end of the multi-way switch module is electrically connected with a plurality of output channels of the PJVS array bias driver; the input end of the DAC output control module is electrically connected with the output end of the error acquisition module, and the output end of the DAC output control module is electrically connected with the input end of the PJVS array bias driver.
Further, the error acquisition module includes:
standard resistor R S The method comprises the steps that any one channel in all driving channels of a PJVS array bias driver and a reference channel form a loop, and the reference channel is any one channel selected in the PJVS array bias driver;
differential amplifier module for measuring standard resistance R S The voltage values at both ends;
the reference voltage source module is used for outputting reference voltage;
the subtracter module is used for comparing the voltage value output by the differential amplifier module with the reference voltage value output by the reference voltage source module and outputting a voltage difference value between the voltage value output by the differential amplifier module and the reference voltage value output by the reference voltage source module, and comprises a first input end and a second input end;
an operational amplifier module; the voltage difference value output by the subtracter module is amplified;
an AD sampling module; the voltage difference value acquisition module is used for acquiring the voltage difference value output by the operational amplifier module and performing analog-to-digital conversion, and outputting error data of each driving channel of the PJVS array bias driver.
Further, the reference voltage source module includes:
a reference voltage source;
a single pole double throw switch S2 comprising a first stationary terminal S A Second stationary end S B The dynamic end D and the signal control end;
wherein, the first stationary end S of the single pole double throw switch A The output end of the reference voltage output module is electrically connected with the second stationary end S of the single-pole double-throw switch B The signal control end of the single-pole double-throw switch is electrically connected with the output end of the digital control module, and the movable end of the single-pole double-throw switch is electrically connected with the second input end of the subtracter module.
Further, the multiple switch module includes a multiple switch S1, and the multiple switch S1 includes a plurality of signal input terminals (S 1A 、S 2A ……S NA ) The signal output end of the multi-path selection switch S1 is electrically connected with the standard resistor R S One end of (1) standard resistor R S The other end of the (b) is electrically connected with the output end of the reference channel of the PJVS array bias driver.
Further, the error acquisition module further includes:
and the storage module is used for storing the error value of each driving channel of the PJVS array bias driver output by the AD sampling module.
Based on the above object of the present invention, the present invention also provides a calibration method of a programmable josephson junction array bias driver, for calibrating a PJVS junction array bias driver, the PJVS junction array bias driver including a plurality of driving channels, the driving channels including a digital-to-analog conversion module, an output voltage of the driving channels being controlled by an input code value of the digital-to-analog conversion module, comprising the steps of:
setting a driving channel in the PJVS array bias driver as a reference channel, setting other channels as non-reference channels, setting DAC input code values of the reference channels as fixed values, and setting the non-reference channels as channels to be calibrated;
using a standard resistor R S Sequentially communicating the reference channel and each channel to be calibrated to form a loop;
sequentially collecting first error values when DAC input code values of all channels to be calibrated are identical to input code values of a reference channel;
sequentially collecting second error values of DAC input code values of all channels to be calibrated relative to a reference channel when the DAC input code values of all channels to be calibrated are maximum;
generating an error curve based on the first error value and the second error value;
and generating error correction parameters based on the error curve, and correcting the input code value x of the digital-to-analog conversion module by the error correction parameters.
Further, the error correction parameter includes a gain coefficient k i And bias parameter b i Gain coefficient k i Set as the slope of the error curve, bias parameter b i Set as the intercept of the error curve.
Further, the DAC input code value x of each channel to be calibrated is corrected asWherein x is the original input code value when not calibrated, V min And j is the bit number of the digital-to-analog conversion module for the minimum output voltage of each channel to be calibrated.
Further, the error measurement method includes:
setting the DAC input code value of the channel to be calibrated to be the same as the DAC input code value of the reference channel;
collecting standard resistor R S The voltage values at the two ends obtain a first error value;
setting the DAC input code value of the channel to be calibrated as the maximum value;
collecting standard resistor R S The difference between the voltage values at two ends and a reference voltage is a second error value, R is the reference voltage when the channel to be calibrated has no error S Voltage values across the terminals.
Further, the DAC input code value of the reference channel is set to a minimum value.
Compared with the prior art, the invention has the beneficial effects that:
the standard resistor is introduced, the measured current error is converted into the voltage error on the measured standard resistor, an error curve is generated by measuring the error values in two states, and correction parameters are obtained according to the error curve, so that the output voltage of each output channel of the PJVS junction array bias driver is corrected by the correction parameters, errors from the DAC and the resistor network are eliminated integrally, the complexity of independent calibration is avoided, and the calibration precision is ensured;
the error collection and the error calibration of a plurality of channels are realized through the states of the multi-channel switch modules, so that the calibration device and the calibration method can be suitable for the PJVS array bias driver with expandable output channels.
Drawings
Fig. 1 is a circuit block diagram of a calibration device according to an embodiment of the present invention.
FIG. 2 is a flow chart of a calibration method according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a multiple switch module according to an embodiment of the invention.
FIG. 4 is a schematic diagram of an error curve according to an embodiment of the present invention.
Wherein, the reference numerals are as follows:
100. a calibration control module; 101. a digital control module; 102. a DAC output control module; 110. a PJVS array bias driver; 120. a multi-way switch module; 130. an error acquisition module; 132. a differential amplifier module; 133. a subtracter module; 134. an operational amplifier module; 135. an AD sampling module; 136. a storage module; 140. a reference voltage source module; 141. a reference voltage source.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. Embodiments of the present invention are described below with reference to the accompanying drawings.
As shown in FIG. 1, a calibration device for a PJVS array bias driver 110 is provided for calibrating the PJVS array bias driver 110, wherein the PJVS array bias driver comprises a plurality of driving channels, the driving channels comprise digital-to-analog converters (DACs) and buffer resistors, one of the driving channels is set as a reference channel, and the embodiment uses the DAC 1 And a buffer resistor R 1 The first driving channel that constitutes is the reference channel, and other channels are non-reference channel, and calibrating device includes: an error acquisition module 130, a multi-way switch module 120 and a calibration control module 100; the error acquisition module 130 is used for acquiring error values of driving currents output by all driving channels of the PJVS array bias driver; a multi-way switch module 120; the error acquisition module 130 is used for controlling each driving channel of the PJVS array bias driver to work; a calibration control module 100; generating error correction parameters of each driving channel of the PJVS array bias driver based on the error values of each driving channel acquired by the error acquisition module 130; the calibration control module 100 includes: the digital control module 101 and the DAC output control module 102, the digital control module 101 is used for controlling the conduction state of the multi-way switch module 120; the DAC output control module 102 is configured to control an output voltage value of the digital-to-analog conversion module. Wherein, the input end of the calibration control module 100 is electrically connected with the output end of the error acquisition module 130, the output end of the calibration control module 100 is electrically connected with the input end of the PJVS array bias driver 110, the input end of the error acquisition module 130 is electrically connected with the output end of the multi-way switch module 120, the control end of the multi-way switch module 120 is electrically connected with the output end of the digital control module 101, and the input end of the multi-way switch module 120 is electrically connected with the PJVS array bias driverA plurality of output channels of the actuator 110; the input end of the DAC output control module 102 is electrically connected with the output end of the error acquisition module 130, and the output end of the DAC output control module 102 is electrically connected with the input end of the PJVS array bias driver 110.
As shown in fig. 1, the error acquisition module 130 includes: standard resistor Rs, differential amplifier module 132, reference voltage source module 140, subtractor module 133, operational amplifier module 134, memory module 136, and AD sampling module 135. The standard resistor Rs is used for forming a loop between any one channel in each driving channel of the PJVS array bias driver and a reference channel, wherein the reference channel is any one channel selected in the PJVS array bias driver; a differential amplifier module 132 for measuring the voltage value across the standard resistor Rs; a reference voltage source module 140 for outputting a reference voltage; the subtractor module 133 is configured to compare the voltage value output by the differential amplifier module 132 with the reference voltage value output by the reference voltage source module 140, and output a voltage difference between the voltage value output by the differential amplifier module 132 and the reference voltage value output by the reference voltage source module 140, and includes a first input terminal and a second input terminal; an operational amplifier module 134; for amplifying the voltage difference output by the subtractor module 133; an AD sampling module 135; the storage module 136 is used for collecting the voltage difference value output by the operational amplifier module 134 and performing analog-to-digital conversion, outputting error data of each driving channel of the PJVS array bias driver 110, and storing the error value of each driving channel of the PJVS array bias driver 110 output by the AD sampling module 135.
As one implementation, the reference voltage source module 140 includes: reference voltage source 141 and single pole double throw switch S2, single pole double throw switch S2 comprising a first stationary terminal S A Second stationary end S B The dynamic end D and the signal control end; wherein the first stationary end S of the single pole double throw switch S2 A The output end of the reference voltage output module is electrically connected with the second stationary end S of the single-pole double-throw switch S2 B The signal control end of the single-pole double-throw switch S2 is electrically connected to the output end of the digital control module 101, and the moving end of the single-pole double-throw switch S2 is electrically connected to the second input end of the subtractor module 133.
As an implementation manner, the multiple switch module 120 includes a multiple switch S1, where the multiple switch S1 includes several signal inputs (S 1A 、S 2A ……S NA ) The signal output end of the multi-path selection switch S1 is electrically connected with one end of a standard resistor Rs, and the other end of the standard resistor Rs is electrically connected with the output end of the reference channel of the PJVS array bias driver 110.
Based on the above object of the present invention, the present invention further provides a calibration method of a PJVS node bias driver 110, for calibrating the PJVS node bias driver 110, where the PJVS node bias driver 110 includes a plurality of driving channels, the driving channels include a digital-to-analog conversion module and a buffer module, and an output voltage of the driving channels is controlled by an input code value of the digital-to-analog conversion module, and the method includes the following steps:
setting a driving channel in the PJVS array bias driver 110 as a reference channel, setting other channels as non-reference channels, setting DAC input code values of the reference channels as fixed values, and setting the non-reference channels as channels to be calibrated;
a standard resistor Rs is used for sequentially connecting the reference channel and each channel to be calibrated to form a loop;
sequentially collecting first error values when DAC input code values of all channels to be calibrated are identical to input code values of a reference channel;
sequentially collecting second error values of DAC input code values of all channels to be calibrated relative to a reference channel when the DAC input code values of all channels to be calibrated are maximum;
generating an error curve based on the first error value and the second error value;
generating an error correction parameter based on the error curve, the error correction parameter including a gain coefficient k i And bias parameter b i Gain coefficient k i Set as the slope of the error curve, bias parameter b i Set as the intercept of the error curve; correcting the input code value x of the digital-to-analog conversion module by error correction parameters, and inputting the code value x into the DAC of each channel to be calibratedIs modified asWherein x is the original input code value when not calibrated, V min And j is the bit number of the digital-to-analog conversion module for the minimum output voltage of each channel to be calibrated.
The error measurement method of the first error value and the second error value comprises the following steps:
setting the DAC input code value of the channel to be calibrated to be the same as the DAC input code value of the reference channel;
acquiring voltage values at two ends of a standard resistor Rs to obtain a first error value;
setting the DAC input code value of the channel to be calibrated as the maximum value;
collecting the difference value between the voltage values at two ends of the standard resistor Rs and a reference voltage as a second error value, wherein the reference voltage is R when the channel to be calibrated has no error S The voltage values across the terminals (as calculated theoretically).
The following further describes embodiments of the present invention using 14-channel PJVS array bias driver 110 as an example:
step 1: the digital control module 101 sends an instruction to control the multi-way switch module 120 to conduct a loop i, wherein the loop i is composed of a channel 1, a channel m and a standard resistor Rs in the error acquisition module 130, the total number of the channels is 14, namely, the channels 1, the channel 2, the channel 14, the m initial value is 2, the m is not less than 2 and not more than 14, the i initial value is 1, the i is not less than 1 and not more than 13, namely, the channel 1 is taken as a reference channel, the channel 2-channel 14 is taken as a channel to be calibrated, and the channel 1 and the channel 2-channel 14 sequentially form a loop and calibrate each channel to be calibrated.
Step 2: the DAC output control module 102 controls the reference channel to output the minimum voltage value corresponding to the minimum range value, and simultaneously, the channel m to be calibrated also outputs the minimum voltage value corresponding to the minimum range value, and the reference voltage source module 140 outputs the reference voltage V 0 '＝0。
Step 3-1: the differential amplifier module 132 converts the differential voltage signal across the standard resistor into a single-ended voltage signal V 0 I.e. the actual voltage value V across the reference resistor Rs is measured by the differential amplifier module 132 0 。
Step 3-2: the actual voltage V across the reference resistor Rs is compared by the subtractor module 133 0 With reference voltage V 0 ' output the first error value DeltaU 0 。
Step 3-3: the operational amplification module amplifies the first error voltage output by the subtractor module 133 by n times, and the AD sampling module 135 collects the first error value DeltaU of the analog signal 0 And performing analog-to-digital conversion to obtain a first error value DeltaU 0 To convert the first error value DeltaU into a digital signal 0 Is stored in the memory module 136 to form error data.
Step 4-1: maintaining the output voltage value of the reference channel unchanged, and switching the movable end of the single-pole double-throw switch S2 of the reference voltage source module 140 to S by changing the DAC input code value of the channel m to be calibrated to enable the channel m to be calibrated to output the voltage value corresponding to the maximum range value A At the end, even if the reference voltage source module 140 outputs the voltage of the reference voltage source 141, the output voltage value V of the reference voltage source 141 1 ' set to R when there is no error in both the channel to be calibrated m and the reference channel S Theoretical voltage difference (calculated value) across.
Step 4-2: measuring the actual voltage difference V across the reference resistor Rs by the differential amplifier module 132 1 Comparing the actual voltage value V 1 And reference voltage V 1 ' and outputs a second error value DeltaU 1 。
Step 4-3: after the operational amplification module amplifies the second error voltage output by the subtractor module 133 by n times, the AD sampling module 135 collects the second error value DeltaU of the analog signal 1 And performing analog-to-digital conversion to obtain a second error value DeltaU 1 To convert the second error value DeltaU into a digital signal 1 Is stored in the memory module 136 to form error data.
Step 5-1: the first error value DeltaU 0 And a second error value DeltaU 1 Is retrieved from the memory module 136 and sent to the calibration control module 100.
Step 5-2: the calibration control module 100 restores, converts voltage errors to current errors,obtaining real error data, and processing the real error data to obtain an error curve y=k of the loop i i x+b i Wherein k is i As gain coefficient, b i Is a bias parameter.
Step 6: if i is less than 13, continuing to acquire error data of the next loop i, enabling i=i+1 and m=m+1 to enter step 2, otherwise, ending self-calibration, and completing all loop calibration.
To sum up, the PJVS array bias driver calibration method and calibration device of the present application is implemented by introducing a standard resistor R S The measured current error is converted into a voltage error on a measurement standard resistor, an error curve is generated by measuring error values of two output states of a channel to be calibrated, correction parameters are obtained according to the error curve, and then the output voltage of each output channel of the PJVS junction array bias driver is corrected by the correction parameters, so that errors from a DAC and a resistor network are eliminated integrally, the complexity of independent calibration is avoided, and the calibration precision is ensured;
the error collection and the error calibration of a plurality of channels are realized through the states of the multi-channel switch modules, so that the calibration device and the calibration method of the invention can be suitable for a PJVS (pulse-width modulation) array bias driver with expandable output channels
While the invention has been described in conjunction with specific embodiments, it should be understood that the foregoing description is intended to illustrate the invention and should not be construed in any way as a limitation on the scope of the invention. Other embodiments of the invention, or equivalents thereof, will suggest themselves to those skilled in the art without undue burden from the present disclosure, based on the explanations herein.
Claims (8)
1. A calibration apparatus for a programmable josephson junction array bias driver for calibrating a PJVS junction array bias driver, the PJVS junction array bias driver comprising a plurality of drive channels, the drive channels comprising a digital-to-analog conversion module, one of the drive channels being set as a reference channel and the remaining channels being non-reference channels, comprising:
the error acquisition module is used for acquiring error values of driving currents output by all driving channels of the PJVS array bias driver;
a multi-way switch module; the error acquisition module is used for controlling the error acquisition module to work in each driving channel of the PJVS array bias driver;
a calibration control module; generating error correction parameters of all driving channels of the PJVS array bias driver based on the error values of all driving channels acquired by the error acquisition module; the calibration control module includes:
the digital control module is used for controlling the conduction state of the multi-way switch module;
the DAC output control module is used for controlling the output voltage value of the digital-to-analog conversion module;
the input end of the calibration control module is electrically connected with the output end of the error acquisition module, the output end of the calibration control module is electrically connected with the input end of the PJVS array bias driver, the input end of the error acquisition module is electrically connected with the output end of the multi-way switch module, the control end of the multi-way switch module is electrically connected with the output end of the digital control module, and the input end of the multi-way switch module is electrically connected with a plurality of output channels of the PJVS array bias driver;
the input end of the DAC output control module is electrically connected with the output end of the error acquisition module, and the output end of the DAC output control module is electrically connected with the input end of the PJVS array bias driver;
the error acquisition module comprises:
standard resistor R S The circuit is used for forming a loop between any one channel in each driving channel of the PJVS array bias driver and a reference channel, wherein the reference channel is any one channel selected in the PJVS array bias driver;
a differential amplifier module for measuring the standard resistance R S The voltage values at both ends;
the reference voltage source module is used for outputting reference voltage;
the subtracter module is used for comparing the voltage value output by the differential amplifier module with the reference voltage value output by the reference voltage source module and outputting a voltage difference value between the voltage value output by the differential amplifier module and the reference voltage value output by the reference voltage source module, and comprises a first input end and a second input end;
an operational amplifier module; the voltage difference value output by the subtracter module is amplified;
an AD sampling module; the voltage difference value acquisition module is used for acquiring the voltage difference value output by the operational amplifier module and performing analog-to-digital conversion, and outputting error data of each driving channel of the PJVS array bias driver.
2. The calibration device of claim 1, wherein the reference voltage source module comprises:
a reference voltage source;
a single pole double throw switch comprising a first stationary end S A Second stationary end S B The dynamic end D and the signal control end;
wherein, the first stationary end S of the single-pole double-throw switch A The second stationary end S of the single-pole double-throw switch is electrically connected with the output end of the reference voltage output module B And the signal control end of the single-pole double-throw switch is electrically connected with the output end of the digital control module, and the movable end of the single-pole double-throw switch is electrically connected with the second input end of the subtracter module.
3. The calibration device of a programmable josephson junction bias driver according to claim 1, wherein said multiplexing switch module comprises a multiplexing switch S1, said multiplexing switch S1 comprising a plurality of signal inputs (S 1A 、S 2A ……S NA ) The signal output end of the multi-path selection switch S1 is electrically connected with the standard resistor R S Is provided with a pair of grooves formed in the outer surface of the base,standard resistor R S The other end of the reference channel is electrically connected with the output end of the reference channel of the PJVS array bias driver.
4. The calibration device of claim 1, wherein the error acquisition module further comprises:
and the storage module is used for storing the error value of each driving channel of the PJVS array bias driver output by the AD sampling module.
5. A method for calibrating a programmable josephson array bias driver for calibrating a PJVS array bias driver, the PJVS array bias driver comprising a plurality of drive channels, the drive channels comprising a digital-to-analog conversion module, an output voltage of the drive channels being controlled by a DAC input code value of the digital-to-analog conversion module, comprising the steps of:
setting a driving channel in the PJVS array bias driver as a reference channel, setting other channels as non-reference channels, setting DAC input code values of the reference channels as fixed values, and setting the non-reference channels as channels to be calibrated;
using a standard resistor R S Sequentially communicating the reference channel and each channel to be calibrated to form a loop;
sequentially collecting first error values when DAC input code values of all channels to be calibrated are identical to input code values of a reference channel;
sequentially collecting second error values of DAC input code values of all channels to be calibrated relative to a reference channel when the DAC input code values of all channels to be calibrated are maximum;
generating an error curve based on the first error value and the second error value;
generating error correction parameters based on the error curve, and inputting code values of the digital-to-analog conversion module by the error correction parametersxCorrecting;
the error measurement method comprises the following steps:
setting the DAC input code value of the channel to be calibrated to be the same as the DAC input code value of the reference channel;
standard resistor for collectionR S The voltage values at the two ends obtain a first error value;
setting the DAC input code value of the channel to be calibrated as the maximum value;
collecting standard resistor R S The difference between the voltage values at two ends and a reference voltage is a second error value, and the reference voltage is R when the channel to be calibrated has no error S Voltage values across the terminals.
6. The method of calibrating a programmable josephson matrix bias driver according to claim 5, wherein the error correction parameters include a gain coefficient ki and a bias parameter bi, the gain coefficient ki being set to the slope of the error curve, the bias parameter bi being set to the intercept of the error curve.
7. The method for calibrating a programmable josephson matrix bias driver according to claim 6, wherein the DAC input code values of each channel to be calibratedxIs modified as，
Wherein,xthe code value is input for the original DAC before unmodified,V min and j is the bit number of the digital-to-analog conversion module for the minimum output voltage of each channel to be calibrated.
8. The method of calibrating a programmable josephson matrix bias driver according to claim 5, wherein the DAC input code value of the reference channel is set to a minimum value.
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| CN115167597B (en) * | 2022-07-25 | 2023-10-13 | 国网陕西省电力有限公司营销服务中心(计量中心) | Self-calibration method and device for bias driver in PJVS system |
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