CN114019338A - Wafer test method of discrete device - Google Patents
Wafer test method of discrete device Download PDFInfo
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- CN114019338A CN114019338A CN202111249965.0A CN202111249965A CN114019338A CN 114019338 A CN114019338 A CN 114019338A CN 202111249965 A CN202111249965 A CN 202111249965A CN 114019338 A CN114019338 A CN 114019338A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
Abstract
The invention discloses a wafer test method of a discrete device, which comprises the following steps: the method comprises the following steps that firstly, a chip is formed on a wafer, the same chip comprises a plurality of discrete device modules, each discrete device module is provided with more than one test pad, and probes on a probe card are arranged according to all the test pads on the chip; secondly, a switch module is arranged on the test channel corresponding to each probe, and the switch module controls the conduction or the disconnection of the test channel; and step three, during testing, the probes of the probe card are contacted with all the test pads on the chip, and the switch module is controlled to select the discrete device module to be tested for testing. The invention can improve the test efficiency of the discrete device.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing process, and more particularly, to a wafer test method for discrete devices.
Background
In the field of semiconductor chip testing, discrete devices such as IGBTs typically have three electrode terminals, namely a gate, an emitter, and a collector, for wafer testing of the discrete devices. The corresponding project test can be completed only by connecting the three ends. As shown in fig. 1, which is a top view of a test pad of a conventional discrete device having 3 test pads, in fig. 1, 3 test pads 101 and three test pads 101 are further marked by G and E, for an IGBT, the test pad 101 corresponding to G indicates the test pad 101 corresponding to a gate, the test pads 101 corresponding to two E are test pads corresponding to an emitter, and a collector is a back electrode, so that the collector is located on the back of the wafer, and thus, the test pad is not arranged on the front of the wafer, and a probe and a collector contact are not required. When there is only one IGBT in the product and only 3 test pads 101 as shown in fig. 1, only one probe card is needed to complete the test.
With market demand, product integration, and testing of discrete devices has become complicated. For example, resistors, diodes, temperature sensors, etc. are integrated in a discrete device IGBT product wafer, and the distribution of the test pads 101 is shown in fig. 2, compared with fig. 1, the number of the test pads 101 in fig. 2 is increased by 2, and the 2 increased test pads 101 are further respectively marked by T1 and T2. Therefore, the number of pads of the chip on the final wafer may exceed 2, and may be 3, 4 or even more.
In actual testing, since different discrete devices need to be tested with different items and functions, a plurality of probe cards need to be manufactured to test different items or functions. For example, when testing the resistor, a probe card for testing the resistor needs to be installed for testing; when the IGBT function is tested, the other probe card is replaced for testing. It can be seen that such testing can affect testing efficiency.
Disclosure of Invention
The invention aims to provide a wafer testing method of a discrete device, which can improve the testing efficiency.
In order to solve the above technical problem, the wafer testing method of the discrete device provided by the invention comprises the following steps:
firstly, a chip is formed on a wafer, a plurality of discrete device modules are arranged on the same chip, each discrete device module is provided with more than one test pad, and probes on a probe card are arranged according to all the test pads on the chip, so that the test pads of the discrete device modules on the chip can be contacted through the corresponding probes on the same probe card.
And secondly, a plurality of test channels are arranged between the probe card and the tester, a switch module is arranged on the test channel corresponding to each probe, and the switch module controls the on/off of the test channels.
And step three, during testing, the probes of the probe card are contacted with all the test pads on the chip, the switch module is controlled according to the discrete device module to be tested, so that the test channels connected with the test pads of the discrete device module to be tested are conducted and the test channels connected with the test pads of the discrete device module not to be tested are disconnected, and then the discrete device module to be tested is tested.
In a further refinement, the discrete device module comprises an IGBT, a MOSFET, a diode, a resistor, or a temperature sensor.
In a further refinement, the IGBT comprises a super junction IGBT.
In a further refinement, the MOSFET comprises a super junction MOSFET.
In a further development, the switching module is realized by hardware.
In a further improvement, the control of the switch module is realized by the sending of instructions by the tester.
In a further improvement, in step three, the test of each discrete device module is controlled by a test program.
The further improvement is that in the test program, when testing different functions, test modules corresponding to different functions are adopted.
In a further improvement, the IGBT test pads comprise 3 test pads corresponding to a grid electrode, an emitter electrode and a collector electrode respectively. The testing pad of the collector is positioned on the back side of the wafer.
The further improvement is that the test pads of the MOSFET comprise 3 test pads corresponding to a grid electrode, a source electrode and a drain electrode respectively; the testing pad of the drain electrode is positioned on the front side or the back side of the wafer.
In a further improvement, the test pad of the resistor comprises 2.
In a further improvement, in the third step, under the condition that the probes of the probe card are ensured to be in contact with all the test pads on the chip, the switch module is controlled to switch, so that the discrete device modules are sequentially tested.
In a further improvement, in the second step, the test channel is formed by connecting a probe card channel and a tester channel.
In a further refinement, the switch modules are disposed on the probe card channels of the probe card.
In a further improvement, in the second step, the switch module is disposed on an interface board connecting the probe card channel and the tester channel.
The invention can test the discrete devices of different types by adopting the same probe card, and can test all the discrete device modules by only switching control the switch module and selecting the corresponding test program under the condition of ensuring the connection of the probe card and all the test pads on the chip, so the invention can test the chip product formed by integrating the discrete devices of different types by only using one probe card for one-time test, thereby greatly improving the test efficiency of the discrete devices.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a top view of a test pad of a prior art discrete device having 3 test pads;
FIG. 2 is a top view of a prior art test pad having discrete devices larger than 3 test pads;
FIG. 3 is a flow chart of a wafer testing method for discrete devices in accordance with an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a wafer testing method for discrete devices according to an embodiment of the present invention; the wafer test method of the discrete device comprises the following steps:
firstly, a chip is formed on a wafer, a plurality of discrete device modules are included on the same chip, each discrete device module is provided with more than one test pad 101, and probes on a probe card are arranged according to all the test pads 101 on the chip, so that the test pads 101 of the discrete device modules on the chip can be contacted through the corresponding probes on the same probe card. A distribution diagram of the test pads 101 of the chip with more than one test pad 101 is shown in fig. 2.
In an embodiment of the invention, the discrete device module comprises an IGBT, a MOSFET, a diode, a resistor or a temperature sensor.
The IGBT comprises a super junction IGBT. The MOSFET comprises a super junction MOSFET.
The test pads 101 of the IGBT include 3 test pads 101 corresponding to a gate, an emitter, and a collector, respectively. The testing pad of the collector is positioned on the back side of the wafer.
In fig. 2, the test pad 101 corresponding to G indicates the test pad 101 corresponding to the gate of the IGBT, and the test pads 101 corresponding to two E are both test pads of the emitter of the IGBT.
The test pads 101 of the MOSFET include 3 test pads 101 corresponding to a gate, a source, and a drain, respectively. When the channel of the MOSFET is in a transverse structure, the test pad of the drain electrode is positioned on the front surface of the wafer; when the channel of the MOSFET is of a vertical structure, the test pad of the drain electrode is positioned on the back surface of the wafer.
The test pad 101 of the resistor includes 2.
And secondly, a plurality of test channels are arranged between the probe card and the tester, a switch module is arranged on the test channel corresponding to each probe, and the switch module controls the on/off of the test channels.
In the embodiment of the invention, the switch module is realized by hardware.
And the control of the switch module is realized by sending instructions by the tester.
The test channel is formed by connecting a probe card channel and a tester channel.
The switch module is disposed on the probe card channel of the probe card. Or the switch module is arranged on an interface board which is connected with the probe card channel and the tester channel.
Step three, during testing, the probes of the probe card are contacted with all the test pads 101 on the chip, the switch module is controlled according to the discrete device module to be tested, so that the test channels connected with the test pads 101 of the discrete device module to be tested are all conducted and the test channels connected with the test pads 101 of the discrete device module not to be tested are all disconnected, and then the discrete device module to be tested is tested.
In the embodiment of the invention, the test of each discrete device module is controlled by a test program. In the test program, when testing different functions, test modules corresponding to the different functions are adopted.
Under the condition that the probes of the probe card are ensured to be in contact with all the test pads 101 on the chip, the switch module is controlled to switch, so that the discrete device modules are sequentially tested.
The embodiment of the invention can realize the test of the discrete device modules of different types by adopting the same probe card and only switching control the switch module and selecting the corresponding test program under the condition of ensuring the connection of the probe card and all test pads 101 on the chip, so that the embodiment of the invention can realize the test of the chip product formed by integrating the discrete devices of different types by only using one probe card and carrying out one-time test, thereby greatly improving the test efficiency of the discrete devices.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A wafer test method of discrete devices is characterized by comprising the following steps:
firstly, a chip is formed on a wafer, a plurality of discrete device modules are arranged on the same chip, each discrete device module is provided with more than one test pad, and probes on a probe card are arranged according to all the test pads on the chip, so that the test pads of the discrete device modules on the chip can be contacted through the corresponding probes on the same probe card;
secondly, a plurality of test channels are arranged between the probe card and the tester, a switch module is arranged on the test channel corresponding to each probe, and the switch module controls the on/off of the test channels;
and step three, during testing, the probes of the probe card are contacted with all the test pads on the chip, the switch module is controlled according to the discrete device module to be tested, so that the test channels connected with the test pads of the discrete device module to be tested are conducted and the test channels connected with the test pads of the discrete device module not to be tested are disconnected, and then the discrete device module to be tested is tested.
2. The wafer test method for discrete devices as recited in claim 1, wherein: the discrete device module includes an IGBT, a MOSFET, a diode, a resistor, or a temperature sensor.
3. The wafer test method for discrete devices as recited in claim 2, wherein: the IGBT comprises a super junction IGBT.
4. The wafer test method for discrete devices as recited in claim 2, wherein: the MOSFET comprises a super junction MOSFET.
5. The wafer test method for discrete devices as recited in claim 1, wherein: the switch module is realized by hardware.
6. The wafer test method for discrete devices as recited in claim 5, wherein: and the control of the switch module is realized by sending instructions by the tester.
7. The wafer test method for discrete devices as recited in claim 1, wherein: in the third step, the test of each discrete device module is controlled by a test program.
8. The wafer test method for discrete devices of claim 7, wherein: in the test program, when testing different functions, test modules corresponding to the different functions are adopted.
9. The wafer test method for discrete devices as recited in claim 2, wherein: the IGBT test pads comprise 3 test pads corresponding to a grid electrode, an emitter electrode and a collector electrode, and the test pads of the collector electrode are located on the back face of the wafer.
10. The wafer test method for discrete devices as recited in claim 2, wherein: the test pads of the MOSFET comprise 3 test pads corresponding to the grid electrode, the source electrode and the drain electrode respectively.
11. The wafer test method for discrete devices as recited in claim 2, wherein: the test pad of resistance includes 2.
12. The wafer test method for discrete devices as recited in claim 1, wherein: in the third step, under the condition that the probes of the probe card are ensured to be in contact with all the test pads on the chip, the switch modules are controlled to be switched, so that the discrete device modules are sequentially tested.
13. The wafer test method for discrete devices according to claim 1 or 5, wherein: and step two, the test channel is formed by connecting a probe card channel and a tester channel.
14. The wafer test method for discrete devices as recited in claim 13, wherein: the switch module is disposed on the probe card channel of the probe card.
15. The wafer test method for discrete devices as recited in claim 13, wherein: in the second step, the switch module is arranged on an interface board which is connected with the probe card channel and the tester channel.
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| CN202111249965.0A CN114019338A (en) | 2021-10-26 | 2021-10-26 | Wafer test method of discrete device |
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| CN202111249965.0A CN114019338A (en) | 2021-10-26 | 2021-10-26 | Wafer test method of discrete device |
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| CN114019338A true CN114019338A (en) | 2022-02-08 |
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Citations (8)
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2021
- 2021-10-26 CN CN202111249965.0A patent/CN114019338A/en active Pending
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