CN114005920A

CN114005920A - LED chip with vertical structure and manufacturing method thereof

Info

Publication number: CN114005920A
Application number: CN202111422016.8A
Authority: CN
Inventors: 林志伟; 崔恒平; 蔡玉梅; 陈凯轩; 蔡海防
Original assignee: Xiamen Changelight Co Ltd
Current assignee: Xiamen Changelight Co Ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2022-02-01

Abstract

The invention provides a vertical structure LED chip and a manufacturing method thereof.A bonding layer, a metal reflector, a dielectric layer and an epitaxial lamination layer are sequentially arranged on the surface of a substrate, wherein the dielectric layer is provided with a dielectric hole, and the metal reflector is connected with the epitaxial lamination layer through an ohmic contact structure filled in the dielectric hole; on one hand, the ohmic contact structure is electrically connected with the second type semiconductor layer through the medium hole, so that the injection and conduction of current are ensured; meanwhile, the problem of weak binding force among the epitaxial lamination layer, the dielectric layer and the metal reflector is solved, and therefore the reliability of the chip is improved. On the other hand, the metal reflector and the dielectric layer form an ODR reflection structure, light rays radiated by the epitaxial lamination layer towards one side of the substrate return to the epitaxial lamination layer and are radiated out from the light emergent side, and the light emergent efficiency is improved.

Description

LED chip with vertical structure and manufacturing method thereof

Technical Field

The invention relates to the field of light emitting diodes, in particular to a vertical-structure LED chip and a manufacturing method thereof.

Background

A Light Emitting Diode (LED) has the advantages of high light emitting intensity, high efficiency, small volume, and long service life, and is considered as one of the most potential light sources. In recent years, LEDs have been widely used in daily life, for example, in the fields of illumination, signal display, backlight, vehicle lights, and large screen display, and these applications also put higher demands on the brightness and light emitting efficiency of LEDs.

Existing light emitting diodes include a horizontal type and a vertical type. The vertical type light emitting diode is obtained by a process of transferring the semiconductor barrier stack to another substrate such as a silicon, silicon carbide or metal substrate and removing the original epitaxially grown substrate, and can effectively improve the technical problems of light absorption, current crowding or poor heat dissipation caused by the epitaxially grown substrate compared with the horizontal type. The substrate is generally transferred by a bonding process, and the bonding is mainly performed by metal-metal high-temperature high-pressure bonding, that is, a metal bonding layer is formed between one side of the semiconductor barrier lamination and the substrate. The other side of the semiconductor barrier crystal lamination layer provides a light-emitting side, a wire electrode is arranged on the light-emitting side to provide current injection or outflow, and a substrate below the semiconductor barrier crystal lamination layer provides current outflow or inflow, so that a light-emitting diode with current passing through the semiconductor barrier crystal lamination layer vertically is formed.

In order to improve the light extraction efficiency, an ODR reflective structure is usually formed by designing a metal reflective layer and a dielectric layer on one side of a metal bonding layer, and the metal reflective layer is electrically connected to the first conductive type semiconductor layer through an opening of the dielectric layer, so as to reflect the light extracted from one side of the metal bonding layer to the light extraction side, thereby improving the light extraction efficiency. However, the dielectric layer, the epitaxial material and the metal belong to different material systems, and the lattice mismatch degree of the dielectric layer, the epitaxial material and the metal is large, so that the dielectric layer, the epitaxial material and the metal are easy to fall off, and the reliability of the LED chip is poor.

In view of the above, the present inventors have specially designed a vertical structure LED chip and a method for manufacturing the same.

Disclosure of Invention

The invention aims to provide a vertical structure LED chip and a manufacturing method thereof, and aims to solve the technical problem that the existing vertical structure LED chip is poor in reliability.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a vertical structure LED chip comprising:

a substrate;

the bonding layer, the metal reflector, the dielectric layer and the epitaxial lamination layer are sequentially stacked on the surface of the substrate; the dielectric layer is provided with a dielectric hole, and the metal reflector is connected with the epitaxial lamination layer through an ohmic contact structure filled in the dielectric hole; the epitaxial lamination layer comprises a second type semiconductor layer, an active region and a first type semiconductor layer which are sequentially stacked along a first direction; the first direction is perpendicular to the substrate and is directed to the epitaxial stack by the substrate;

a first electrode laminated on a surface of the first type semiconductor layer on a side away from the active region;

and a second electrode laminated on the back surface of the substrate.

Preferably, the filling height of the ohmic contact structure is higher than that of the dielectric layer along one side of the dielectric layer close to the metal reflecting layer.

Preferably, the height of the ohmic contact structure relative to the dielectric layer is 0-500 nm.

Preferably, the area ratio of the ohmic contact structure to the dielectric layer is 0.05-1, inclusive, along the same horizontal plane.

Preferably, the substrate comprises a silicon substrate or a silicon carbide substrate or a metal substrate.

Preferably, the dielectric layer has a plurality of dielectric holes distributed in an array, and the ohmic contact structure in the dielectric holes is in a cylindrical or conical shape.

Preferably, the bonding layer comprises one or more of Ti, In, Au.

Preferably, the metal mirror may be formed of at least one metal or alloy of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf.

Preferably, the ohmic contact structure includes a transparent conductive layer or a metal alloy.

The invention also provides a manufacturing method of the vertical structure LED chip, which is used for manufacturing any one of the vertical structure LED chips and comprises the following steps:

s01, providing a growth substrate;

s02, stacking an epitaxial lamination on the surface of the growth substrate, wherein the epitaxial lamination comprises a first type semiconductor layer, an active region and a second type semiconductor layer which are sequentially stacked along the growth direction;

s03, depositing an ohmic contact layer on the surface of the second type semiconductor layer;

s04, patterning the ohmic contact layer through photoetching and developing processes to form a plurality of ohmic contact structures which are arranged at intervals, exposing the second type semiconductor layer between every two adjacent ohmic contact structures, and reserving photoresist along the horizontal surface of each ohmic contact structure;

s05, forming a dielectric layer by evaporation, wherein the dielectric layer is respectively deposited on the exposed area of the second type semiconductor layer and the surface of the photoresist; the deposition height of the dielectric layer is lower than the vertical height of the ohmic contact structure;

s06, synchronously removing the photoresist on the surface of the ohmic contact structure and the dielectric layer on the surface of the photoresist through a stripping and photoresist removing process;

s07, manufacturing a metal reflector, wherein the metal reflector completely covers the dielectric layer and the ohmic contact structure;

s08, providing a substrate, and bonding the metal reflector surface and the substrate through a bonding layer to form a whole;

s09, stripping the growth substrate to expose the first type semiconductor layer;

s10, forming a first electrode on the exposed surface of the first type semiconductor layer;

and S11, forming a second electrode on the surface of the substrate on the side opposite to the bonding layer.

According to the technical scheme, the bonding layer, the metal reflector, the dielectric layer and the epitaxial lamination layer are sequentially arranged on the surface of the substrate, wherein the dielectric layer is provided with a dielectric hole, and the metal reflector is connected with the epitaxial lamination layer through the ohmic contact structure filled in the dielectric hole; on one hand, the ohmic contact structure is electrically connected with the second type semiconductor layer through the medium hole, so that the injection and conduction of current are ensured; meanwhile, the problem of weak binding force among the epitaxial lamination layer, the dielectric layer and the metal reflector is solved, and therefore the reliability of the chip is improved. On the other hand, the metal reflector and the dielectric layer form an ODR reflection structure, light rays radiated by the epitaxial lamination layer towards one side of the substrate return to the epitaxial lamination layer and are radiated out from the light emergent side, and the light emergent efficiency is improved.

Furthermore, the filling height of the ohmic contact structure is higher than that of the dielectric layer along the horizontal direction of one side of the dielectric layer close to the metal reflecting layer; the ohmic contact structure and the metal reflector can be enlarged while the mirror reflection area formed by the dielectric layer and the metal reflector is ensured, so that the current is easy to conduct and expand, and the internal quantum efficiency of the LED chip with the vertical structure is improved.

The manufacturing method of the LED chip with the vertical structure provided by the invention has the beneficial effects that the manufacturing process is simple and convenient, the cost is saved, and the production is convenient while the beneficial effects of the LED chip are realized.

Secondly, after an ohmic contact layer is deposited on the surface of the epitaxial lamination layer, patterning the ohmic contact layer by adopting photoetching and developing processes to form a plurality of ohmic contact structures which are arranged at intervals, exposing the second type semiconductor layer between every two adjacent ohmic contact structures, and reserving photoresist along the horizontal surface of each ohmic contact structure; next, when depositing the dielectric layer on the exposed region of the second type semiconductor layer and the surface of the photoresist in step S05, the deposition height of the dielectric layer can be easily lower than the vertical height of the ohmic contact structure; furthermore, the contact area between the ohmic contact structure and the metal reflector can be increased while the mirror reflection area formed by the dielectric layer and the metal reflector is ensured, so that the current is easy to conduct and expand, and the internal quantum efficiency of the LED chip with the vertical structure is improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an LED chip with a vertical structure according to an embodiment of the present invention;

fig. 2.1 to fig. 2.13 are schematic structural diagrams corresponding to steps of a method for manufacturing an LED chip with a vertical structure according to an embodiment of the present invention;

the symbols in the drawings illustrate that: 1. the semiconductor device comprises a growth substrate, a first type semiconductor layer, a first electrode, a second type semiconductor layer, a second electrode, a third type semiconductor layer, a fourth type semiconductor layer, a fifth type semiconductor layer, a sixth type semiconductor layer, a fourth type semiconductor layer, a sixth type semiconductor layer, a fourth type semiconductor layer.

Detailed Description

In order to make the content of the present invention clearer, the content of the present invention is further explained below with reference to the attached drawings. The invention is not limited to this specific embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, a vertical structure LED chip includes:

a substrate 9;

the bonding layer 8, the metal reflector 7, the dielectric layer 6 and the epitaxial lamination layer are sequentially laminated on the surface of the substrate 9; the dielectric layer 6 is provided with a dielectric hole, and the metal reflector 7 is connected with the epitaxial lamination layer through an ohmic contact structure 51 filled in the dielectric hole; the epitaxial lamination comprises a second type semiconductor layer 4, an active region 3 and a first type semiconductor layer 2 which are sequentially stacked along a first direction; the first direction is perpendicular to the substrate 9 and directed from the substrate 9 towards the epitaxial stack;

a first electrode 10 laminated on a surface of the first type semiconductor layer 2 on a side away from the active region 3;

and a second electrode 12 laminated on the back surface of the substrate 9.

The epitaxial stack is a semiconductor barrier stack obtained by MOCVD or other growth methods, the semiconductor barrier stack is a semiconductor material capable of providing conventional radiation such as ultraviolet, blue, green, yellow, red, infrared light, and the like, and specifically may be a material of 200 to 950nm, such as a common nitride, specifically, a gallium nitride-based semiconductor barrier stack, and the gallium nitride-based barrier stack is commonly doped with elements such as aluminum, indium, and the like, and mainly provides radiation of 200 to 550nm band; or common AlGaInP-based or AlGaAs-based semiconductor barrier crystal lamination, which mainly provides radiation in the wavelength band of 550-950 nm. The semiconductor barrier stack mainly comprises a second type semiconductor layer 4, an active region 3 and a first type semiconductor layer 2. The first type semiconductor layer 2 and the second type semiconductor layer 4 may be doped by n-type doping or P-type doping, respectively, to realize a material layer providing at least electrons or holes, respectively. The n-type semiconductor layer may be doped with an n-type dopant such as Si, Ge, or Sn, and the P-type doped semiconductor layer may be doped with a P-type dopant such as Mg, Zn, Ca, Sr, or Ba. The second-type semiconductor layer 4, the active region 3 and the first-type semiconductor layer 2 may be made of AlGaInN, GaN, AlGaN, AlGaInP, GaAs or AlGaAs. The second-type semiconductor layer 4 and the first-type semiconductor layer 2 include a capping layer providing electrons or holes, and may include other layer materials such as a current spreading layer, a window layer, an ohmic contact layer, etc., and are arranged in different layers according to the doping concentration or the composition content. The active region 3 is a region for providing light radiation by electron and hole recombination, different materials can be selected according to different light emitting wavelengths, and the active region 3 can be a periodic structure of a single quantum well or a multiple quantum well. By adjusting the composition ratio of the semiconductor material in the active region 3, light of different wavelengths is expected to be radiated.

It should be noted that the dielectric layer 6 may be formed of at least one of fluoride, nitride, oxide, and the like, specifically, at least one of ZnO, SiO2, SiOx, SiOxNy, Si3N4, Al2O3, TiOx, MgF, or GaF. The dielectric layer 6 is formed by combining at least one or more dielectric layers 6 with different refractive indexes, and the dielectric layer 6 is more preferably a light-transmitting dielectric layer 6, and at least 50% of light can pass through the dielectric layer 6. More preferably, the refractive index of the dielectric layer 6 is lower than the refractive index of the epitaxial stack.

The first electrode 10 is disposed on the light exit side of the epitaxial stack. The first electrode 10 mainly includes a pad portion, and the pad portion is mainly used for external routing in front electrode packaging. The bonding pad of the front electrode can be designed into different shapes, such as a cylinder or a square or other polygons, according to the actual routing requirement. As a preferred embodiment, the front electrode may further include an extension portion extending from the pad, the extension portion may be formed in a predetermined pattern shape, and the extension portion may have various shapes, particularly, a stripe shape.

The second electrode 12 in this embodiment is formed on the back side of the substrate 9 in a full-surface manner, the substrate 9 in this embodiment is a conductive supporting substrate 9, and the first electrode 10 and the second electrode 12 are formed on both sides of the substrate 9, so as to realize that current flows vertically through the epitaxial stack, thereby providing a uniform current density.

The first electrode 10 and the second electrode 12 are preferably made of a metal material. The pad portion and the extension portion of the first electrode 10 may further include a metal material that enables good ohmic contact with the semiconductor epitaxial material.

In this embodiment, the filling height of the ohmic contact structure 51 is higher than that of the dielectric layer 6 along the side of the dielectric layer 6 close to the metal reflective layer.

In the present embodiment, the height of the ohmic contact structure 51 relative to the dielectric layer 6 is 0-500 nm.

In this embodiment, the area ratio of the ohmic contact structure 51 to the dielectric layer 6 along the same horizontal plane is 0.05 to 1, inclusive.

In the present embodiment, the ohmic contact structure 51 includes a transparent conductive layer or a metal alloy.

In the present embodiment, the substrate 9 includes a silicon substrate, a silicon carbide substrate, or a metal substrate.

In this embodiment, the dielectric layer 6 has a plurality of dielectric holes distributed in an array, and the ohmic contact structures 51 in the dielectric holes are in a cylindrical or conical shape.

In the present embodiment, the bonding layer 8 includes one or more of Ti, In, and Au.

In the present embodiment, the metal mirror 7 may be formed of at least one metal or alloy of Ag, Ni, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, and Hf.

s01, as shown in fig. 2.1, providing a growth substrate 1;

s02, as shown in fig. 2.2, stacking an epitaxial stack on the surface of the growth substrate 1, the epitaxial stack including a first type semiconductor layer 2, an active region 3 and a second type semiconductor layer 4 stacked in sequence along the growth direction;

s03, as shown in figure 2.3, depositing an ohmic contact layer 5 on the surface of the second type semiconductor layer 4;

s04, as shown in fig. 2.4, patterning the ohmic contact layer 5 by photolithography and development processes to form a plurality of ohmic contact structures 51 arranged at intervals as shown in fig. 2.5, wherein the second type semiconductor layer 4 is exposed between two adjacent ohmic contact structures 51, and the photoresist L is remained along the horizontal surface of the ohmic contact structures 51;

s05, as shown in fig. 2.6, evaporating to form a dielectric layer 6, wherein the dielectric layer 6 is deposited on the exposed area of the second type semiconductor layer 4 and the surface of the photoresist L; the deposition height of the dielectric layer 6 is lower than the vertical height of the ohmic contact structure 51;

s06, as shown in fig. 2.7, the photoresist L on the surface of the ohmic contact structure 51 and the dielectric layer 6 on the surface of the photoresist L are removed simultaneously by a stripping and stripping process;

s07, as shown in fig. 2.8, fabricating a metal mirror 7, wherein the metal mirror 7 completely covers the dielectric layer 6 and the ohmic contact structure 51;

s08, as shown in fig. 2.9, providing a substrate 9, and bonding the surface of the metal mirror 7 and the substrate 9 through the bonding layer 8 to form an integral structure as shown in fig. 2.10;

s09, as shown in fig. 2.11, the growth substrate 1 is peeled off to expose the first type semiconductor layer 2;

s10, as shown in fig. 2.12, forming a first electrode 10 on the exposed surface of the first type semiconductor layer 2;

s11, as shown in fig. 2.13, forming a second electrode 12 on the surface of the substrate 9 facing away from the bonding layer 8.

According to the technical scheme, the bonding layer 8, the metal reflector 7, the dielectric layer 6 and the epitaxial lamination layer are sequentially arranged on the surface of the substrate 9, wherein the dielectric layer 6 is provided with a dielectric hole, and the metal reflector 7 is connected with the epitaxial lamination layer through the ohmic contact structure 51 filled in the dielectric hole; on one hand, the ohmic contact structure 51 is electrically connected with the second type semiconductor layer 4 through the dielectric hole, so that the injection and conduction of current are ensured; meanwhile, the problem of weak binding force between the epitaxial lamination layer and the dielectric layer 6 and between the epitaxial lamination layer and the metal reflector 7 is solved, and therefore the reliability of the chip is improved. On the other hand, the metal reflector 7 and the dielectric layer 6 form an ODR reflection structure, light rays radiated from the epitaxial lamination layer towards the substrate 9 side return to the epitaxial lamination layer and are radiated out from the light-emitting side, and the light-emitting efficiency is improved.

Further, in the horizontal direction along one side of the dielectric layer 6 close to the metal reflective layer, the filling height of the ohmic contact structure 51 is higher than that of the dielectric layer 6; the contact area between the ohmic contact structure 51 and the metal reflector 7 can be increased while the mirror reflection area formed by the dielectric layer 6 and the metal reflector 7 is ensured, so that the current is easily conducted and expanded, and the internal quantum efficiency of the LED chip with the vertical structure is further improved.

Secondly, after the ohmic contact layer 5 is deposited on the surface of the epitaxial lamination layer, the ohmic contact layer 5 is patterned by adopting photoetching and developing processes to form a plurality of ohmic contact structures 51 which are arranged at intervals, the second type semiconductor layer 4 is exposed between every two adjacent ohmic contact structures 51, and photoresist is reserved along the horizontal surface of each ohmic contact structure 51; next, when depositing the dielectric layer 6 on the exposed region of the second type semiconductor layer 4 and the surface of the photoresist in step S05, the deposition height of the dielectric layer 6 is lower than the vertical height of the ohmic contact structure 51; furthermore, while the mirror reflection area formed by the dielectric layer 6 and the metal reflector 7 is ensured, the contact area between the ohmic contact structure 51 and the metal reflector 7 can be increased, so that the current is easily conducted and expanded, and the internal quantum efficiency of the vertical-structure LED chip is improved.

The device provided by the embodiment of the present invention has the same implementation principle and technical effect as the method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the method embodiments without reference to the device embodiments. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the foregoing systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A vertical structure LED chip, comprising:

a substrate;

and a second electrode laminated on the back surface of the substrate.

2. The vertical geometry LED chip of claim 1 wherein the ohmic contact structure is filled to a greater height than the dielectric layer along a side of the dielectric layer adjacent to the metal reflector layer.

3. The vertical geometry LED chip of claim 2 wherein the height of the ohmic contact structure above the dielectric layer is in the range of 0-500 nm.

4. The vertical structure LED chip of claim 1, wherein the ohmic contact structure and the dielectric layer have an area ratio of 0.05-1, inclusive, along the same horizontal plane.

5. The vertical geometry LED chip of claim 1 wherein the substrate comprises a silicon substrate.

6. The vertical structure LED chip of claim 1, wherein the dielectric layer has a plurality of dielectric holes distributed in an array, and the ohmic contact structures in the dielectric holes are in a shape of a column or a cone.

7. The vertical geometry LED chip of claim 1 wherein the bonding layer comprises one or more of Ti, In, Au.

8. A method for manufacturing the vertical structure LED chip according to any one of claims 1 to 7, comprising the steps of:

s01, providing a growth substrate;

9. The method of claim 8, wherein the height of the ohmic contact structure relative to the dielectric layer is 0-500 nm.

10. The method of claim 8, wherein the ohmic contact structure and the dielectric layer have an area ratio of 0.05-1, inclusive, along the same horizontal plane.