CN114005837A - Manufacturing method of semiconductor device and semiconductor device - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: providing a stop layer and a stack layer on the stop layer, wherein the stop layer is provided with a raised structure on the side facing away from the stack layer; and forming a gate gap structure which penetrates through the stack layer and extends into the stop layer, wherein the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure. The invention can reduce the risk of electric leakage between the common source electrode layer and the grid electrode layer and improve the performance of the semiconductor device.

Description

Manufacturing method of semiconductor device and semiconductor device

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.

Background

In the semiconductor device, a gap is easily formed between the gate gap structure and the substrate due to the difference of film layer stress. When the substrate is removed, the interlayer insulating layer in the stack layer may be etched through the gap, so that when the common source layer is subsequently deposited, the common source layer is electrically connected to the gate layer in the stack layer through the gap, and a leakage risk exists.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor device and the semiconductor device, which can reduce the risk of electric leakage between a common source layer and a grid layer and improve the performance of the semiconductor device.

The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:

providing a stop layer and a stack layer on the stop layer, wherein the stop layer is provided with a raised structure on the side facing away from the stack layer;

and forming a gate gap structure which penetrates through the stack layer and extends into the stop layer, wherein the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure.

Further preferably, the gate slit structure also extends into the protrusion structure.

Further preferably, the step of providing a stop layer comprises:

forming a groove in a substrate;

forming the stop layer on the substrate, and the stop layer filling the groove to form the protruding structure in the groove.

Further preferably, the base includes a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer;

the step of forming a recess in the substrate includes:

providing the substrate, a first insulating layer on the substrate, and a sacrificial layer on the first insulating layer;

forming the groove in the sacrificial layer;

forming the second insulating layer on the sacrificial layer, wherein the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove.

Further preferably, after the step of forming the gate gap structure extending through the stacked layer and into the stop layer, the method further includes:

removing the substrate;

and forming a common source electrode layer on one side of the stop layer, which is far away from the stack layer, and covering the protruding structure by the common source electrode layer.

Further preferably, the gate slit structure includes a semiconductor layer penetrating through the stack layer and extending into the stop layer, and an isolation layer disposed around the semiconductor layer.

Accordingly, the present invention also provides a semiconductor device comprising:

the device comprises a stop layer, a first electrode and a second electrode, wherein one side of the stop layer is provided with a convex structure;

the stack layer is positioned on one side, away from the raised structure, of the stop layer; and the number of the first and second groups,

and the gate gap structure penetrates through the stack layer and extends into the stop layer, and the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure.

Further preferably, the gate slit structure also extends into the protrusion structure.

Further preferably, the semiconductor device further includes a common source layer;

the common source layer is positioned on one side of the stop layer, which is far away from the stack layer, and covers the protruding structure.

Further preferably, the gate slit structure includes a semiconductor layer penetrating through the stack layer and extending into the stop layer, and an isolation layer disposed around the semiconductor layer.

The invention has the beneficial effects that: the method comprises the steps of providing a stopping layer and a stack layer positioned on the stopping layer, wherein the stopping layer is provided with a protruding structure on one side deviating from the stack layer to form a gate gap structure penetrating through the stack layer and extending into the stopping layer, and the orthographic projection of the bottom of the gate gap structure on the stopping layer is positioned in the protruding structure so as to completely separate a substrate from the gate gap structure and the stack layer through the stopping layer, so that the substrate cannot be affected by subsequent removal of the substrate, the risk of electric leakage between a subsequently formed common source layer and a gate layer in the stack layer is reduced, and the performance of the semiconductor device is improved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2a to fig. 2i are schematic structural diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 3 is a schematic partial structural diagram of a semiconductor device according to an embodiment of the present invention.

Detailed Description

Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.

In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

As shown in fig. 1, a method for manufacturing a semiconductor device according to an embodiment of the present invention, the semiconductor device includes, but is not limited to, a three-dimensional memory, and the method includes steps 101 to 102, specifically as follows:

step 101, providing a stop layer and a stack layer on the stop layer, wherein the stop layer has a raised structure on a side facing away from the stack layer.

In the embodiment of the invention, the stop layer is provided with the convex structure, the convex structure is positioned at the bottom of the stop layer, and the convex structure is convex towards the direction departing from the stop layer. The stack layer is on top of the stop layer, i.e. the bump structure and the stack layer are on opposite sides of the stop layer.

Specifically, the providing the stop layer in step 101 includes:

forming a groove in a substrate;

forming the stop layer on the substrate, and the stop layer filling the groove to form the protruding structure in the groove.

Wherein the base may include a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer, and the step of forming the groove in the base includes:

providing the substrate, a first insulating layer on the substrate, and a sacrificial layer on the first insulating layer;

forming the groove in the sacrificial layer;

forming the second insulating layer on the sacrificial layer, wherein the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove.

In particular, step 101 corresponds to fig. 2a to 2 e. As shown in fig. 2a, a substrate 11 is provided, and a first insulating layer 12 is formed on the substrate 11 using a thin film deposition process. Then, a sacrificial layer 13 is formed on the first insulating layer 12 using a thin film deposition process. The thin film deposition process may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser assisted deposition, or the like. The substrate 11 may be a silicon substrate, or may be a substrate including another element semiconductor or a compound semiconductor. The first insulating layer 12 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride. The sacrificial layer 13 may be a semiconductor layer such as polysilicon.

As shown in fig. 2b, a recess 10 is formed in the sacrificial layer 13 using an etching process. The etching process may be an anisotropic etching process, such as a plasma etching process, or an isotropic etching process, such as a wet etching process. The recess 10 does not extend through the sacrificial layer 13, i.e. the depth of the recess 10 is smaller than the thickness of the sacrificial layer 13. The cross-section of the groove 10 may be circular, rectangular, etc., and is not particularly limited thereto.

As shown in fig. 2c, a second insulating layer 14 is formed on the sacrificial layer 13 using a thin film deposition process, and the second insulating layer 14 covers the inner surface of the groove 10. Since the groove 10 does not penetrate the sacrificial layer 13, the second insulating layer 14 is spaced from the first insulating layer 12 by the sacrificial layer 13, so that the second insulating layer 14 is not etched when the first insulating layer 12 is etched and removed later. Meanwhile, the second insulating layer 14 isolates the sacrificial layer 13 from the stop layer 2 to be formed later, so that the stop layer 2 is not etched when the sacrificial layer 13 is removed by etching later. The thickness of the second insulating layer 14 is thinner, and the second insulating layer 14 is only located on the sidewall and the bottom of the groove 10, so the groove 10 is not filled. The second insulating layer 14 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride.

After the second insulating layer 14 is formed, the substrate 11, the first insulating layer 12, the sacrificial layer 13, and the second insulating layer 14 constitute a base 1, and the base 1 has a groove 10 therein.

As shown in fig. 2d, a thin film deposition process is used to form the stop layer 2 on the second insulating layer 14, and the stop layer 2 fills the groove 10, so as to form a protruding structure 21 in the groove 10, and the protruding structure 21 protrudes toward one side of the substrate 1. The shape of the protruding structure 21 matches the shape of the groove 10, i.e. the cross section of the protruding structure 21 may be circular, rectangular, etc., and is not limited herein. Then, the upper surface of the stop layer 2 is subjected to chemical mechanical polishing to ensure the flatness of the upper surface of the stop layer 2. The material of the stop layer 2 may be a semiconductor material such as polysilicon.

As shown in fig. 2e, a stack layer 3 is formed on the stop layer 2 by using a thin film deposition process, i.e. the stack layer 3 is located on a side of the stop layer 2 facing away from the bump structure 21.

The stack layer 3 may include a plurality of interlayer sacrificial layers 31 and interlayer insulating layers 32 alternately stacked in a longitudinal direction, which is a direction perpendicular to the upper surface of the stop layer 2. The number of stacked layers of the interlayer sacrifice layer 31 and the interlayer insulating layer 32 is not limited, and is, for example, 48 layers, 64 layers, 128 layers, or the like. The interlayer sacrificial layer 31 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the interlayer insulating layer 32 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

As shown in fig. 2e, a storage channel structure 6 longitudinally penetrating through the stacked layer 3, the stop layer 2 and the second insulating layer 14 and extending into the sacrificial layer 13 is formed in the stacked layer 3, and the storage channel structure 6 includes an isolation layer 61, a channel layer 62 disposed around the isolation layer 61, and a storage medium layer 63 disposed around the channel layer 62. The storage medium layer 63 includes a tunnel layer (not shown in the figure) provided around the peripheral side of the channel layer 62, a charge storage layer (not shown in the figure) provided around the peripheral side of the tunnel layer, and a charge blocking layer (not shown in the figure) provided around the peripheral side of the charge storage layer. Among them, the isolation layer 61 may be an oxide such as silicon oxide, the channel layer 62 may be polysilicon, etc., the tunnel layer may be an oxide such as silicon oxide, silicon nitride, silicon oxynitride, etc., the charge storage layer may be an insulating layer including quantum dots or nanocrystals or a compound containing nitrogen and silicon, and the charge blocking layer may be an oxide such as silicon oxide.

And 102, forming a gate gap structure which penetrates through the stack layer and extends into the stop layer, wherein the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure.

In the embodiment of the invention, the number of the gate gap structures is the same as that of the protrusion structures, namely, the number of the gate gap structures can be at least one, the number of the protrusion structures can be at least one, and at least one gate gap structure and at least one protrusion structure are arranged in a one-to-one correspondence manner.

In particular, step 102 corresponds to fig. 2f to 2 g. As shown in fig. 2f, a gate gap 40 is first formed through the stacked layer 3 and extending into the stop layer 2. Because the thickness of the stop layer 2 is relatively thin, the protruding structure 21 is arranged on the side of the stop layer 2 departing from the stack layer 3, and the gate gap 40 corresponds to the protruding structure 21, so that the stop layer 2 is prevented from penetrating through the stop layer 2 due to the excessively large extending depth of the gate gap 40, and the stop layer 2 is ensured to surround the bottom of the gate gap 40. The cross-sectional area of the protruding structure 21 may be larger than the cross-sectional area of the bottom of the gate slit 40, i.e. the orthographic projection of the bottom of the gate slit 40 on the stop layer 2 is located within the protruding structure 21, so that the gate slit 40 may also extend into the protruding structure 21.

The interlayer sacrificial layer 31 in the stacked layer 3 is then replaced with a gate layer 33 through a gate gap 40, the gate layer 33 including but not limited to tungsten, cobalt, copper, aluminum, doped silicon or doped silicide.

As shown in fig. 2g, the gate slit structure 4 is formed in the gate slit 40 such that the gate slit structure 4 penetrates the stack layer 3 and extends into the stop layer 2. The cross-sectional area of the bottom of the protruding structure 21 may be larger than the cross-sectional area of the gate slit structure 4, i.e. the orthographic projection of the bottom of the gate slit structure 4 on the stop layer 2 is located within the protruding structure 21, so that the gate slit structure 4 may also extend into the protruding structure 21. Because the thickness of the stop layer 2 is relatively thin, the protruding structure 21 is arranged, and the protruding structure 21 and the gate slit structure 4 are arranged correspondingly, so that the stop layer 2 can surround the bottom of the gate slit structure 4.

The gate slit structure 4 may be an insulating layer, i.e., the gate slit 40 is filled with an insulating layer to form the gate slit structure 4. The insulating layer includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride. As shown in fig. 2g, the gate gap structure 4 may also include a semiconductor layer 41 penetrating through the stacked layer 3 and extending into the stop layer 2, and a spacer layer 42 disposed around the semiconductor layer 41, that is, the spacer layer 42 is formed on the sidewall and the bottom of the gate gap 40, and then the semiconductor layer 41 is filled in the gate gap 40, so that the semiconductor layer 41 and the spacer layer 42 form the gate gap structure 4. Semiconductor layer 41 may be a semiconductor material such as polysilicon, and spacer layer 42 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride.

Due to the different materials of the second semiconductor 41 and the spacer layer 42, by adjusting the film thicknesses of the semiconductor layer 41 and the spacer layer 42 in the gate slit structure 4, a stress window (stress window) of the gate slit structure 4 can be increased, and a process window (wafer window) for adjusting the deformation of the semiconductor device by the gate slit structure 4 is enlarged.

In addition, a transition layer (not shown) may be formed on the peripheral side of the gate slit structure 4 (i.e., between the sidewall of the gate slit structure 4 and the stack layer 3), and a barrier layer (not shown) may be formed on the peripheral side of the transition layer (i.e., between the transition layer and the stack layer 3). The barrier layer includes, but is not limited to, alumina and the transition layer includes, but is not limited to, titanium nitride.

Further, after the step S102 of forming a gate gap structure that penetrates through the stacked layer and extends into the stop layer, the method further includes:

removing the substrate;

and forming a common source electrode layer on one side of the stop layer, which is far away from the stack layer, and covering the protruding structure by the common source electrode layer.

As shown in fig. 2h, the substrate 11, the first insulating layer 12, the sacrificial layer 13, and the second insulating layer 14 are sequentially removed by an etching process. Since the second insulating layer 14 and the storage medium layer 63 of the storage channel structure 6 are made of the same material, when the second insulating layer 14 is removed, the storage medium layer 63 at the bottom of the storage channel structure 6 (i.e., the storage medium layer 63 at the side of the stop layer 2 away from the stack layer 3) is removed at the same time to expose the channel layer 62 at the bottom of the storage channel structure 6.

Then, as shown in fig. 2i, a thin film deposition process is used to form the common source layer 5 on the side of the stop layer 2 away from the stack layer 3, and the common source layer 5 covers the bump structure 21. In addition, the common source layer 5 covers the channel layer 62 at the bottom of the storage channel structure 6 to connect with the channel layer 62. The common source layer 5 may be a semiconductor material such as polysilicon.

It should be noted that the gate gap structure in the prior art extends through the stack layer, the stop layer and the second insulating layer and into the sacrificial layer, and the gate gap structure includes a semiconductor layer and an isolation layer disposed around the semiconductor layer. The thickness of the isolation layer is small, the thickness of the semiconductor layer is large, so that local stress of the gate gap structure is different, and gaps possibly exist among the bottom of the gate gap structure, the sacrificial layer, the second insulation layer and the stop layer. Since the sacrificial layer is made of the same material as the stop layer, the stop layer is etched through the gap to form an opening in the stop layer when the sacrificial layer is removed. Because the second insulating layer and the interlayer insulating layer in the stack layer are made of the same material, when the second insulating layer is removed, the interlayer insulating layer in the stack layer is etched through the gap so as to form an opening in the interlayer insulating layer. Then, when the common source layer is formed, the common source layer is deposited to the stop layer and the opening in the interlayer insulating layer through the gap, and is easily electrically connected with the gate layer in the stack layer, so that a leakage risk exists between the common source layer and the gate layer.

Based on this, the gate slit structure 4 in the present application extends through the stacked layer 3 and into the stop layer 2, since the stop layer 2 has the protrusion structure 21 on the side facing away from the stacked layer 3, and the orthographic projection of the bottom of the gate slit structure 4 on the stop layer 2 is located in the protrusion structure 21, so that the stop layer 2 can completely surround the bottom of the gate slit structure 4, thereby completely spacing the gate slit structure 4 from the substrate 1, and the stop layer 2 is completely spaced from the sacrificial layer 13 by the second insulating layer 14. The stop layer 2 is not etched when the sacrificial layer 13 in the substrate 1 is removed, and the interlayer insulating layer 32 in the stack layer 3 is not etched when the second insulating layer 14 in the substrate 1 is removed. Since the stop layer 2 and the interlayer insulating layer 32 in the stack layer 3 are not etched, after the common source layer 5 is formed, the common source layer 5 is not electrically connected to the gate electrode layer 33 in the stack layer 3, thereby reducing the risk of leakage between the common source layer 5 and the gate electrode layer 33.

As can be seen from the above, the method for manufacturing a semiconductor device according to the embodiment of the invention can provide the stop layer and the stack layer located on the stop layer, where the stop layer has the protrusion structure on a side away from the stack layer, to form the gate slit structure that penetrates through the stack layer and extends into the stop layer, and the orthographic projection of the bottom of the gate slit structure on the stop layer is located in the protrusion structure, so that the stop layer completely separates the substrate from the gate slit structure and the stack layer, and the substrate is subsequently removed without affecting the stack layer, thereby reducing the risk of leakage between the subsequently formed common source layer and the gate layer in the stack layer, and improving the performance of the semiconductor device.

Correspondingly, the embodiment of the invention also provides a semiconductor device which can be manufactured by the manufacturing method of the semiconductor device in the embodiment.

As shown in fig. 3, the present embodiment provides a semiconductor device including, but not limited to, a three-dimensional memory. The semiconductor device comprises a stop layer 2, a stack layer 3 and a gate gap structure 4.

Wherein one side of the stop layer 2 has a raised structure 21, the raised structure 21 being raised towards the side facing away from the stop layer 2. The stop layer 2 may be a semiconductor material such as polysilicon.

The stack layer 3 is located on a side of the stop layer 2 facing away from the bump structure 21. The stack layer 3 may include a plurality of gate layers 33 and interlayer insulating layers 32 alternately stacked in a longitudinal direction, which is a direction perpendicular to the upper surface of the stop layer 2. The number of stacked layers of the gate layer 33 and the interlayer insulating layer 32 is not limited, and is, for example, 48 layers, 64 layers, 128 layers, or the like. The gate layer 33 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, and the interlayer insulating layer 32 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride.

The semiconductor device further comprises a memory channel structure 6, the memory channel structure 6 extending through the stack layer 3 and the stop layer 2. The memory channel structure 6 includes an isolation layer 61, a channel layer 62 disposed around the isolation layer 61, and a memory medium layer 63 disposed around the channel layer 62. The storage medium layer 63 includes a tunnel layer (not shown in the figure) provided around the peripheral side of the channel layer 62, a charge storage layer (not shown in the figure) provided around the peripheral side of the tunnel layer, and a charge blocking layer (not shown in the figure) provided around the peripheral side of the charge storage layer.

The gate slit structure 4 penetrates the stack layer 3 and extends into the stop layer 2, and the gate slit structure 4 corresponds to the protrusion structure 21. Due to the fact that the thickness of the stop layer 2 is small, the protruding structure 21 is arranged on the side, away from the stack layer 3, of the stop layer 2, so that the situation that the gate slit structure 4 penetrates through the stop layer 2 due to too large extending depth can be avoided, and the stop layer 2 surrounds the bottom of the gate slit structure 4 is guaranteed.

The cross-sectional area of the protruding structure 21 may be larger than the cross-sectional area of the bottom of the gate slit structure 4, i.e. the orthographic projection of the bottom of the gate slit structure 4 on the stop layer 2 is located within the protruding structure 21, so that the gate slit structure 4 may also extend into the protruding structure 21.

The number of the protruding structures 21 is the same as that of the gate slit structures 4, that is, the number of the protruding structures 21 is at least one, the number of the gate slit structures 4 is at least one, and the at least one protruding structure 21 and the at least one gate slit structure 4 are arranged in a one-to-one correspondence manner.

The gate slit structure 4 may be an insulating layer, and the gate slit structure 4 may also include a semiconductor layer 41 penetrating the stacked layers 3 and extending into the stop layer 2, and a spacer layer 42 disposed around the semiconductor layer 41. Semiconductor layer 41 may be a semiconductor material such as polysilicon, and spacer layer 42 includes, but is not limited to, any one or combination of silicon oxide, silicon nitride, and silicon oxynitride.

Due to the fact that the semiconductor 41 and the spacing layer 42 are made of different materials, the stress window of the gate gap structure 4 can be increased by adjusting the film thicknesses of the semiconductor 41 and the spacing layer 42 in the gate gap structure 4, and the process window of the gate gap structure 4 for regulating and controlling the deformation of a semiconductor device is enlarged.

The semiconductor device may further include a common source layer 5, the common source layer 5 being located on a side of the stop layer 2 facing away from the stack layer 3, and the common source layer 5 covering the bump structure 21. The common source layer 5 is also connected to the channel layer 62 in the storage channel structure 6, i.e. the channel layer 62 in the storage channel structure 6 may extend into the common source layer 5. The common source layer 5 may be a semiconductor material such as polysilicon.

The semiconductor device provided by the embodiment of the invention can provide the stop layer and the stack layer positioned on the stop layer, wherein the stop layer is provided with the bulge structure at one side away from the stack layer to form the gate gap structure which penetrates through the stack layer and extends into the stop layer, and the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the bulge structure, so that the substrate, the gate gap structure and the stack layer are completely separated by the stop layer, the stack layer is not affected when the substrate is removed subsequently, the risk of electric leakage between the common source layer formed subsequently and the gate layer in the stack layer is reduced, and the performance of the semiconductor device is improved.

In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:

providing a stop layer and a stack layer on the stop layer, wherein the stop layer is provided with a raised structure on the side facing away from the stack layer;

and forming a gate gap structure which penetrates through the stack layer and extends into the stop layer, wherein the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure.

2. The method of claim 1, wherein the gate slit structure further extends into the raised structure.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of providing a stop layer comprises:

forming a groove in a substrate;

forming the stop layer on the substrate, and the stop layer filling the groove to form the protruding structure in the groove.

4. The method for manufacturing a semiconductor device according to claim 3, wherein the base includes a substrate, a first insulating layer, a sacrificial layer, and a second insulating layer;

the step of forming a recess in the substrate includes:

providing the substrate, a first insulating layer on the substrate, and a sacrificial layer on the first insulating layer;

forming the groove in the sacrificial layer;

forming the second insulating layer on the sacrificial layer, wherein the second insulating layer covers the inner surface of the groove; the stop layer is located on the second insulating layer and fills the groove.

5. The method of fabricating a semiconductor device according to claim 3, further comprising, after the step of forming a gate gap structure extending through the stacked layers and into the stop layer:

removing the substrate;

and forming a common source electrode layer on one side of the stop layer, which is far away from the stack layer, and covering the protruding structure by the common source electrode layer.

6. The method of claim 1, wherein the gate gap structure comprises a semiconductor layer extending through the stacked layers and into the stop layer, and an isolation layer disposed around the semiconductor layer.

7. A semiconductor device, comprising:

the device comprises a stop layer, a first electrode and a second electrode, wherein one side of the stop layer is provided with a convex structure;

the stack layer is positioned on one side, away from the raised structure, of the stop layer; and the number of the first and second groups,

and the gate gap structure penetrates through the stack layer and extends into the stop layer, and the orthographic projection of the bottom of the gate gap structure on the stop layer is positioned in the protrusion structure.

8. The semiconductor device of claim 7, wherein the gate slot structure further extends into the raised structure.

9. The semiconductor device according to claim 7, further comprising a common source layer;

the common source layer is positioned on one side of the stop layer, which is far away from the stack layer, and covers the protruding structure.

10. The semiconductor device of claim 7, wherein the gate aperture structure comprises a semiconductor layer extending through the stacked layers and into the stop layer, and an isolation layer disposed around the semiconductor layer.

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