JP2022124290A - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Abstract

To prevent dielectric breakdown from occurring even when semiconductor devices with trench gate structures are miniaturized.SOLUTION: A semiconductor device 10 has a substrate 1 having a trench 7, and a gate electrode layer 3 that fills the interior of the trench 7 and whose thickness formed on the substrate 1 is thicker than the lower limit and included within a range of less than 1/2 the width L of the short side in the trench 7.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a semiconductor device having a trench gate structure and a method of manufacturing the semiconductor device.

In Patent Document 1, by providing a region where no trench is formed between a trench surrounding a small trench isolation resistor and a trench surrounding another small trench isolation resistor adjacent to the small trench isolation resistor, A semiconductor device is disclosed in which the thickness of an interlayer insulating film is reduced.

In such a semiconductor device having a trench gate structure, the trench may be filled with an insulating material or a conductive material to form an insulating layer or a conductive layer depending on the application of the semiconductor.

FIG. 5 is a diagram showing a schematic example of a conventional semiconductor device 20 having a trench gate structure. 5A shows a cross-sectional view of the semiconductor device 20, and FIG. 5B shows a top plan view of the semiconductor device 20 shown in FIG. 5A.

The semiconductor device 20 includes, for example, a substrate 1, a gate oxide film 2, a gate electrode layer 3, an intermediate insulating film 4, a gate electrode 5 having a contact 5A electrically connected to the gate electrode layer 3, a source electrode 6, and a drain (not shown). A trench 7 is formed in the substrate 1 containing the electrodes.

The gate electrode layer 3 is made of, for example, phosphorus-doped polysilicon. As shown in FIG. 5A, in order to form the gate electrode layer 3 inside the trench 7, the thickness from the surface of the substrate 1 must be equal to the width of the short side of the trench 7 shown in FIG. 5B. It is necessary to laminate polysilicon on the substrate 1 so that the thickness is 1/2 of L (hereinafter referred to as "reference thickness") or more. This is because, when polysilicon is laminated from the surface of the substrate 1 to a thickness less than the reference thickness, the polysilicon is partially formed in the recessed trench 7 formed from the surface of the substrate 1 toward the inside of the substrate 1 . A portion where silicon is not formed may occur. In such a case, a chemical solution or the like may enter unintentionally into a place where polysilicon is not formed, degrading the quality of the semiconductor device 20 .

For these reasons, in the conventional semiconductor device 20 having the trench gate structure, the thickness of the gate electrode layer 3 located on the surface of the substrate 1 is greater than or equal to the reference thickness.

On the other hand, since the thickness of the gate electrode layer 3 on the surface of the substrate 1 cannot be made less than the reference thickness, the thickness of the intermediate insulating film 4, for example, should be reduced as much as possible in order to meet the demand for miniaturization of the semiconductor device 20. Thinning techniques may be taken.

JP 2009-259936 A

However, if the intermediate insulating film 4 is made too thin, for example, the source electrode 6 and the gate electrode layer 3 on the surface of the substrate 1 may be electrically connected to cause dielectric breakdown.

DISCLOSURE OF THE INVENTION The present invention has been proposed in order to solve the above-described problems, and is a semiconductor device that is less prone to dielectric breakdown than conventional ones even when a semiconductor device having a trench gate structure is miniaturized, and a semiconductor device. It aims at providing the manufacturing method of.

A semiconductor device according to the present invention includes a substrate having a trench region, a gate electrode layer having a first region filled in the trench region, and a second region extending around the first region. wherein the thickness of the second region is thicker than a preset lower limit value and falls within a range of less than half the width of the short side of the trench region. do.

On the other hand, a method of manufacturing a semiconductor device according to the present invention includes a trench forming step of forming a trench region from the surface of a substrate, and a thickness of at least the periphery of the trench region being 1/2 of the width of the short side of the trench region. a gate electrode layer forming step of forming a gate electrode layer made of polysilicon having a thickness greater than or equal to the above; and a first etching step of etching the gate electrode layer so as to be included in a range less than 1/2 of the width of the short side of the trench region; and above the surface of the substrate while maintaining an electrical connection between a first gate electrode layer on the surface of the substrate to be located in the trench region and a second gate electrode layer located in the trench region. and a second etching step of etching and removing the gate electrode layer other than the first gate electrode layer.

According to the present invention, it is possible to provide a semiconductor device in which dielectric breakdown is less likely to occur than in the prior art even when a semiconductor device having a trench gate structure is miniaturized, and a method for manufacturing the semiconductor device. have.

It is a figure which shows the schematic example of the semiconductor device which has a trench gate structure. It is a figure which shows an example of the manufacturing condition of a semiconductor device from a trench formation process to a gate electrode layer formation process. It is a figure which shows an example of the manufacturing condition of a semiconductor device in a 1st etching process and a 2nd etching process. It is a figure which shows an example of the manufacturing condition of a semiconductor device in an intermediate insulating film formation process and an electrode formation process. 1 is a diagram showing a schematic example of a conventional semiconductor device having a trench gate structure; FIG.

Hereinafter, this embodiment will be described with reference to the drawings. The same constituent elements and the same processing are given the same reference numerals throughout the drawings, and overlapping descriptions are omitted.

<Structure of semiconductor device>
FIG. 1 is a diagram showing a schematic example of a semiconductor device 10 having a trench gate structure according to this embodiment. 1A shows a cross-sectional view of the semiconductor device 10, and FIG. 1B shows a plan view of the semiconductor device 10 shown in FIG. 1A as viewed from above.

The semiconductor device 10 has a substrate 1, a gate oxide film 2, a gate electrode layer 3, an intermediate insulating film 4, and a contact 5A electrically connected to the gate electrode layer 3, like the conventional semiconductor device 20 shown in FIG. It includes a gate electrode 5, a source electrode 6, and a drain electrode (not shown). The substrate 1 is composed of, for example, a silicon (Si) substrate, and a trench 7 having a rectangular opening is formed in the substrate 1 . The substrate 1 is not limited to a silicon substrate, and may be a silicon carbide (SiC) substrate or an SOS (Silicon-on-Sapphire) substrate obtained by epitaxially growing silicon on a sapphire substrate.

The semiconductor device 10 shown in FIG. 1 differs from the conventional semiconductor device 20 shown in FIG. The difference is that the thickness of the first gate electrode layer 3A is half the width L of the short side of the trench 7 shown in FIG. 1B, that is, less than the reference thickness.

As already explained, the thickness of the gate electrode layer 3A located on the surface of the substrate 1 is such that the region of the gate electrode layer 3 where the trench 7 is filled with polysilicon, that is, the second gate electrode layer 3B. In order to form it, it is necessary to make it more than the reference thickness.

Therefore, in the semiconductor device 10, the gate electrode layer 3 is formed by laminating polysilicon over the entire substrate 1 so that the thickness of the gate electrode layer 3 located on the surface of the substrate 1 becomes equal to or larger than the reference thickness. . Thereafter, after etching the gate electrode layer 3 so that the thickness of the gate electrode layer 3 formed over the entire substrate 1 is less than 1/2 of the reference thickness, the gate electrode layer 3 above the surface of the substrate 1 is etched. An unnecessary part is removed to form a gate electrode layer 3 having a stepped cross section as shown in FIG. 1(A).

Since the gate electrode layer 3 is connected to the gate electrode 5 , among the gate electrode layers 3 before etching above the surface of the substrate 1 , the first gate electrode located in the direction in which the gate electrode 5 exists when viewed from the trench 7 . Layer 3A will remain on the surface of substrate 1 .

That is, if the short side width L of the trench 7 in the semiconductor device 10 is 1 μm, the thickness of the first gate electrode layer 3A is less than 0.5 μm. Actually, the first gate electrode layer 3A and the second gate electrode layer 3B are integrated, but for convenience of explanation, as shown in FIG. The regions of the first gate electrode layer 3A and the second gate electrode layer 3B in the gate electrode layer 3 are clearly shown by showing the imaginary boundary separating the electrode layers 3B.

The second gate electrode layer 3B is an example of the first region of the gate electrode layer 3 filled in the trench 7 of the gate electrode layer 3, and the first gate electrode layer 3A is the first region of the gate electrode layer 3. It is an example of the second region of the gate electrode layer 3 extending around the second gate electrode layer 3B. "The gate electrode layer 3 extending around the second gate electrode layer 3B" refers to the gate electrode layer 3 extending to the outside of the trench 7 while being electrically connected to the second gate electrode layer 3B. Say things.

The substrate 1, the gate oxide film 2, the intermediate insulating film 4, and the gate electrode 5 stacked above or below the first gate electrode layer 3A of the semiconductor device 10 have respective thicknesses different from those of the conventional semiconductor device 20. , the thickness of the first gate electrode layer 3A is thinner than that of the conventional semiconductor device 20, and the step between the first gate electrode layer 3A and the second gate electrode layer 3B is small. Therefore, the thickness of the resist formed on the gate electrode layer 3 can be reduced in the manufacturing process of the semiconductor device 10, which will be described later. Therefore, since the resist pattern can be miniaturized, it is possible to miniaturize the dimension of the element pattern formed in the semiconductor device 10, such as the contact, and to improve the accuracy.

Further, when the thickness of the entire semiconductor device 10 is the same as that of the conventional semiconductor device 20, the thickness of the first gate electrode layer 3A can be made thinner than that of the conventional semiconductor device 20. The thickness of the intermediate insulating film 4 on the electrode layer 3A can be increased. Therefore, reliability can be improved more than the conventional semiconductor device 20. FIG.

The thinner the thickness of the first gate electrode layer 3A, the better. The thickness must be thicker than the preset lower limit. That is, the thickness of the first gate electrode layer 3A is included in a range that is thicker than the lower limit and less than the reference thickness.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of the semiconductor device 10 shown in FIG. 1 will be described with reference to FIGS.

[Step 1: Trench Forming Step]
First, trenches 7 are formed in the substrate 1 by performing dry etching or the like on the substrate 1 (see FIG. 2A).

[Step 2: Gate oxide film forming step]
The substrate 1 is heated in an atmosphere containing oxygen to form the gate oxide film 2 on the surface of the substrate 1 and the inner wall of the trench 7 (see FIG. 2B). In the step of forming the gate oxide film 2, it is preferable to form the gate oxide film 2 while heating the substrate 1 from 800.degree. C. to 1000.degree.

[Step 3: Gate electrode layer forming step]
A polysilicon film is formed on the surface of the substrate 1 so that the thickness of the gate electrode layer 3 above the surface of the substrate 1 is 1/2 of the width L of the short side of the trench 7, that is, the reference thickness or more. (See FIG. 2(C)). As a result, the inside of trench 7 is filled with polysilicon, and the polysilicon density in gate electrode layer 3 becomes uniform.

For example, when the reference thickness is 1 μm, the gate electrode layer 3 having a thickness of 0.5 μm or more (for example, 0.8 μm) is formed on the surface of the substrate 1 .

As a method for forming the gate electrode layer 3, for example, CVD (Chemical Vapor Deposition) or the like is used.

[Step 4: First etching step]
The thickness of the gate electrode layer 3 formed above the surface of the substrate 1 is thicker than the preset lower limit value and is within a range of less than 1/2 of the reference thickness. Etching is performed (see FIG. 3A).

For example, if the reference thickness is 1 μm, the first etching step forms a gate electrode layer 3 with a thickness of 0.4 μm, which is less than half the reference thickness, above the surface of the substrate 1 . be done.

[Step 5: Second etching step]
In the gate electrode layer 3, a resist 8 is applied to the gate electrode layer 3 on the surface of the substrate 1 which will be located under the gate electrode 5, that is, the position of the gate electrode layer 3 which will be the first gate electrode layer 3A. (See FIG. 3(B)). In this case, in order to maintain the electrical connection between the first gate electrode layer 3A and the second gate electrode layer 3B located in the trench 7 even after etching, the resist 8 is applied to the extent that the entire opening of the trench 7 is not covered. A resist 8 is applied so as to protrude above the trench 7 .

The gate electrode layer 3 above the surface of the substrate 1 is then etched. The area of the gate electrode layer 3 to which the resist 8 is applied, that is, the first gate electrode layer 3A is not removed by etching. The gate electrode layer 3 other than the first gate electrode layer 3A above the surface of is removed, and the gate electrode layer 3 having a stepped cross section is formed (see FIG. 3C).

[Step 6: Intermediate insulating film forming step]
An intermediate insulating film 4 is formed to cover the surfaces of the gate oxide film 2 and the gate electrode layer 3 (see FIG. 4A). In the semiconductor device 10, for example, the thickness of the intermediate insulating film 4 located on the second gate electrode layer 3B where the thickness of the intermediate insulating film 4 is the thickest is set to 1 μm.

[Step 7: Electrode Forming Step]
A contact 5A reaching the first gate electrode layer 3A is formed in the intermediate insulating film 4 using photolithography and etching. A gate electrode 5 is formed by burying aluminum or the like in the contact 5A, and a source electrode 6 and a drain electrode (not shown) also made of aluminum or the like are formed in the semiconductor device 10 (see FIG. 4B).

As described above, the semiconductor device 10 shown in FIG. 1 is manufactured.

As described above, the thickness of the first gate electrode layer 3A in the gate electrode layer 3 is changed by etching in the first etching process. Affected by the etching that takes place.

It is known that there is a shape processing error of ±0.1 μm due to etching. Therefore, in the electrode forming process, if etching is performed to form the contact 5A penetrating the intermediate insulating film 4, this etching unintentionally thins the surface of the first gate electrode layer 3A by 0.1 μm at most. It may get lost.

Considering that the etching in the first etching step may also reduce the thickness of the first gate electrode layer 3 by 0.1 μm from the design value, the designed thickness of the first gate electrode layer 3 The thickness must be greater than the product of 0.1 μm, which is the maximum processing error of etching, and the number of times of etching that affects the thickness of the first gate electrode layer 3A. When manufacturing the semiconductor device 10 according to the present embodiment, the number of times of etching that affects the thickness of the first gate electrode layer 3A is two. If the thickness is more than 0.2 μm, which is twice as large as 0.1 μm, the first gate electrode layer 3A will not be etched so that the thickness of the first gate electrode layer 3A becomes 0 μm, that is, the first gate electrode layer 3A will no longer exist. can be avoided.

Therefore, the thickness obtained by multiplying the maximum processing error of etching by the number of times of etching after the first etching step that affects the thickness of the first gate electrode layer 3A becomes the lower limit.

In this embodiment, the gate electrode layer 3 is formed by filling the trench 7 with polysilicon and then stacking polysilicon on the surface of the substrate 1 to form the gate electrode layer 3 . The method of manufacturing the semiconductor device 10 in which the thickness of the electrode layer 3A is less than half the width L of the short side of the trench 7 has been described. Naturally, the manufacturing method can be applied regardless of the properties of the material that constitutes the layer on the surface of the substrate 1 . For example, a layer on the surface of substrate 1 may be composed of an insulator.

Thus, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be made to the above-described embodiments without departing from the gist of the invention, and forms with such changes or improvements are also included in the technical scope of the present invention.

1 substrate 2 gate oxide film 3 gate electrode layer 3A first gate electrode layer 3B second gate electrode layer 4 intermediate insulating film 5 gate electrode 5A contact 6 source electrode 7 trench 8 resist 10 semiconductor device 20 conventional semiconductor device

Claims (6)

a substrate having a trench region;
a gate electrode layer having a first region filled in the trench region and a second region extending around the first region;
A semiconductor device comprising
The semiconductor device, wherein the thickness of the second region is thicker than a preset lower limit value and falls within a range of less than half the width of the short side of the trench region. 2. The semiconductor device according to claim 1, wherein said lower limit value is set according to the number of times of etching that affects the thickness of said second region. 3. The semiconductor device according to claim 1, wherein said lower limit is 0.2 [mu]m. a trench forming step of forming a trench region from the surface of the substrate;
a gate electrode layer forming step of forming a gate electrode layer made of polysilicon such that the thickness at least in the periphery of the trench region is 1/2 or more of the width of the short side of the trench region;
The thickness of the gate electrode layer at least around the trench region is greater than a preset lower limit and is within a range of less than 1/2 of the width of the short side of the trench region. a first etching step for etching the gate electrode layer;
maintaining an electrical connection between a first gate electrode layer on the surface of the substrate which is to be located under the gate electrode and a second gate electrode layer located within the trench region among the gate electrode layers; a second etching step above to etch away the gate electrode layer other than the first gate electrode layer above the surface of the substrate;
A method of manufacturing a semiconductor device comprising: 5. The manufacturing of a semiconductor device according to claim 4, wherein said lower limit value in said first etching step is set according to the number of times of etching performed after said first etching step, which affects the thickness of said first gate electrode layer. Method. 6. The method of manufacturing a semiconductor device according to claim 4, wherein said lower limit value in said first etching step is set to 0.2 [mu]m.

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